TW550739B - Trench structure for semiconductor devices - Google Patents

Trench structure for semiconductor devices Download PDF

Info

Publication number
TW550739B
TW550739B TW091114617A TW91114617A TW550739B TW 550739 B TW550739 B TW 550739B TW 091114617 A TW091114617 A TW 091114617A TW 91114617 A TW91114617 A TW 91114617A TW 550739 B TW550739 B TW 550739B
Authority
TW
Taiwan
Prior art keywords
trenches
semiconductor
groove
peripheral
contact layer
Prior art date
Application number
TW091114617A
Other languages
English (en)
Inventor
Ashok Challa
Original Assignee
Fairchild Semiconductor
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor filed Critical Fairchild Semiconductor
Application granted granted Critical
Publication of TW550739B publication Critical patent/TW550739B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0814—Diodes only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

550739 A7 五、發明説明（ 本發明概有關於半導體元件。特別是，有關一種可用 來增強半導體元件之性能的溝槽結構。 (請先閱讀背面之注意事項再填窝本頁) 目月ίΐ已有多種的半導體元件被普遍地使用於電源用途 中。其中一種裝置係為肖特基障壁（Sch〇uky bardei<)。一肖 特基障壁乃包含一金屬/半導體介面，其功能宛如一整流器 而可供控制電流的傳輸。 用來測量一肖特基障壁整流器之阻斷能力的指標，係 為其崩潰電壓。在本文中所述之崩潰電壓係指最大的反向 電壓，其可被支持穿過該裝置，而仍可提供阻絕功能者。 在肖特基P早壁整流裔中的崩潰通常係為一種“突崩，，式崩 潰’其主要係可歸因於習稱‘‘衝擊離子化，，的現象。 -訂| 豢- 第1圖係示出一基本肖特基障壁整流器1〇的戴面圖。一 第一金屬層100會被設在一半導體層102上。典型地，該半 導體層102係由一形成漂移區的磊晶層1〇4，及一較重地摻 雜之基材106所構成。重摻雜的基材1〇6及一第二金屬層1〇8 會為該裝置提供一電阻式接觸。 施一反向偏壓VREV通過該肖特基障壁整流器1〇將可 造成一空乏區110，通過其中則該所施電壓的一大部份將會 減降。當該反向電壓增加時，則在空乏區i 1〇中的電場將會 、變大。該等增大的電場會使電荷載子加速，若充分地加速， 則可藉與摻雜劑原子的碰撞，而導致電子/電洞對的形成。 所產生的載子愈多，則將有更多的載子會變成具有足夠的 能量來造成衝擊離子化。因此，衝擊離子化會成為一雪球 效應’藉著連續及倍增地撞擊，將能造成電子/電洞對的串 -4 550739 A7 B7___ 五、發明説明（2 ) 級。最後將會達到一點，至其衝擊離子化的速率太大，而 使該裝置不能再支持任何更多的反向偏壓施加通過它為 止。此電壓極限通常在該領域中係被稱為“突崩電壓’’。 在第1圖中所示的基本肖特基障壁整流器10會被其反 向阻斷能力所限制，因為電場會傾向於集聚在該金屬層100 的邊緣處。因此，用來終結該肖特基障壁整流器的技術已 被找出。有兩種普遍用來減少該邊緣效應的技術，係為一 局部氧化的矽結構(LOCOS)，以及一擴散場環結構，曾被 揭示於 “Modern Power Devices” 中，by B.J.Baglia，1987, Reprinted Edition, ρρ·437〜438。該兩種技術乃被示於第2 及3圖中。該二種習知技術皆具有減少集結在該金屬邊緣之 電場的功效，因此乃可達到較高的崩潰電壓。 另一種被推薦可在一肖特基障壁整流器中來達到甚至 更佳之反向阻絕能力的技術，乃被揭示於Wilamowski，B.M. 的“Schottky Diodes with High Breakdown Voltages，” 中， Solid State Electron.，26, 491 〜493(1983)。在該論文中所推 薦的結構之截面，乃示於第4圖中，其係被稱為接面障壁控 制式肖特基整流器（即“JBS”整流器）。有一連串的P型區400 會被設在該裝置之漂移區402中及其表面處。該等p型區 400會形如網幕來減低靠近該表面的電場。由於在表面處的 電％會決疋該裝置的崩潰電壓，故加入該等p型區4 〇 〇將可 造成較高的崩潰電壓。 该JB S整流态之一不佳特性係有關於該p_n接面，其係 被形成於P型區400和漂移區4〇2之間。對具有高反向崩潰 本紙張尺度適用中國國表標準（CNS) Α4規格（21〇\297公楚） ..... 、可 (請先閱讀背面之注意事項再填寫本頁) 550739 A7 _B7_ 五、發明説明（3 ) 電壓之矽裝置而言，在該肖特基障壁能達到一合理的正向 傳導電流之前，乃需要一超過(K7V的正向偏壓。不幸的是， 高於0.7V的電壓會具有導通該p-n接面的作用。而當導通 時，少數載子將會被引入，其將會減緩該裝置的切換速度。 切換速度的減降乃是不佳的，尤其是若該肖特基障壁整流 器被使用於切換用途時，例如開關式電源供應器等。
為克服該JBS整流器之正向偏壓限制，另一種變化裝 置結構亦曾被提供，其乃利用一連串併排成行的金屬氧化 物半導體（MOS)溝槽來取代該等P型區。此MOS障壁肖特基 整流器（即“MBS整流器”）係被推薦於B.J· Baglia的“New Concepts in Power Rectifiers，’’中，Proceedings of the Third International Workshop on the Physics of Semiconductor Devices，November 24-28, World Scientific Publ. Singapore， 1985. — MBS整流器50的截面乃示於第5A圖中。其包含一第 一金屬層508，於上則設有一半導體層502。典型地，該半 體層502係由一形成漂移區的磊晶層504，及一較重摻雜的 基材506所構成。該重摻雜的基材506及第一金屬層5 08會為 該裝置提供一電阻性接觸。該MBS整流器50亦包含許多併 列的溝槽512等設在磊晶層504中，其各皆終結（或“併接”) 於一終結溝槽514，該終結溝槽514基本上係垂直於該等併 列溝槽5 12而來延伸。該終結溝槽514及併列溝槽5 12等會以 一介電質516，例如氧化矽來覆襯，並被填滿一導電材料 518，例如金屬（如第5A圖所示）或摻雜的多晶矽。一第二金 屬層520的被覆設在該結構的整個表面上。請注意在第5A 6 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） 550739 A7 B7 五、發明説明（4 ) (請先閲讀背面之注意事項再填寫本頁) 圖中，該金屬層520係被示出僅部份地覆蓋該表面。惟如此 作為使該整流器50之各下層構造，其可能被該金屬層520 所覆蓋者，能夠被看到。該MBS整流器50的金屬/半導體障 壁將會被形成於該第二金屬層520與位於各併列溝槽512之 間的凸台522頂面之間的接面處。 在許多方面，該MBS整流器會優於該JBS整流器。但 是，其在反向阻絕能力上亦有所限制。該等限制可由第5B 圖來示出，其乃示出第5A圖中之MBS整流器的頂視圖或 “佈局”圖。在各凸台522兩端的箭號，指向“E”(“E”電場）者 係用來表示，在反向偏壓的情況下，電場如何傾向於朝向 該等凸台522的末端集結。該電場集結現象，係由於該等區 域比該半導體層502的其它區域更快地空乏所致。因此，於 第5A圖中所示之該MBS整流器的崩潰電壓將會被決定，故 而會被第5B圖中所示的溝槽結構形狀所限制。 -般而言，依據目前所知的各種觀點，一斷開的溝槽 結構將可加強半導體裝置的崩潰特性。例如，如將於後更 詳細的說明，一肖特基障壁整流器當與本發明的農開溝槽 整合時，相較於習知結構所能達到者，將會顯示出更強的 反向阻絕能力。 依據本發明的第一概念，一 MOS溝槽結構會與一半導 體裝置來整合，而得以加強該半導體裝置的崩潰特性，乃 包含-半導體基材；多數併排的溝槽設在該基材中，每一 併排溝槽皆由兩端、側壁及一底部所形成，且每二相鄰的 併排溝槽係由包含該半導體裝置的凸台所分開，該等凸台 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） 五、發明説明（5 ) =具有—凸台寬度；及-周邊溝槽係^兩端、侧壁、及一 二部所形成’該«溝槽至少會部份地"”併 等併排溝#的東m ί Pa1隔來與該 、、槽的末知刀開，一介電材料會覆襯該等併排溝样 及周邊溝槽的端部、側壁盘底 曰 ”底口P，以及一導電材料完全填 /雨該專以介電質覆襯的溝槽。 本發明之此概念及其它相關者，現將與本發明之優點 和對其實質的進-步瞭解’參照本說明書的其餘部份及所 附圖式等，而來一起說明如下。 圖式之簡單說明 第1圖為一基本肖特基障壁整流器的截面圖； 第2圖為一可消減邊緣效應之具有局部氧化矽結構 (LOCOS)的肖特基障壁整流器之截面圖； 第3圖為一可消減邊緣效應之具有擴散場環結構的肖 特基障壁整流器之截面圖； 第4圖為一具有許多擴散區之肖特基障壁整流器的截 面圖，該等擴散區會一起形如一網幕來加強該整流器的反 向阻絕能力； 第5A圖為一 M0S障壁肖特基整流器的立體截面圖； 第5B圖為第5A圖中之該^^”章壁肖特基整流器的頂 視圖； 第6 A圖為本發明一實施例之立體截面圖，乃示出本發 明之斷開溝槽結構概念與一肖特基障壁整流器的整合； 第6B圖為第6A圖中所示裝置的佈局圖； 本紙張尺度適用中國國家標準（CNS)A4規格（210X297公爱） 550739 A7 B7
f (請先閲讀背面之注意事項再填寫本頁) 第7圖為一點線圖，乃示出並比較許多具有類似於第 6 A和6B圖所示之溝槽結構的肖特基障壁整流器，以及具有 類似於第5 A和5B圖所示之溝槽結構的肖特基障壁整流哭 等，所測得的崩潰電壓；及 第8圖一立體截面圖，示出本發明之斷開溝槽結構概念 與一雙擴散射頻場效應電晶體的整合。 、? 請參閱第6A圖，所示出之一半導體裝置結構6〇係依據 本發明之一實施例，而包含一肖特基障壁整流器整合一 MOS溝槽結構。該裝置結構60包含一第一金屬層6〇〇，其 上5又有一半導體層602。該半導體層6 02可包—單獨的石夕 層，或如第6Α圖所示，包含一磊晶層6〇4(或“漂移，，區）及一 較重摻雜的基材606。該重換雜的基材6〇6會與該第一金屬 層600來為該裝置提供一電阻性接觸。該裝置結構6〇亦包括 一 M0S溝槽結構，其含有多數的併排溝槽612與一周邊槽 槽614設在該磊晶層604中。周邊溝槽具有預定的規格和距 離’其較佳尺寸會被提供於後。該周邊溝槽614與併排溝槽 612等會被覆襯一介電質616。該等以介電質覆襯的溝槽會 被填滿一導電材料（未示於第6A圖中），例如金屬或摻雜的 多晶矽。雖亦未示於第6 A圖中，有一第二金屬層會被覆設 在該裝置結構的整個表面上。該金屬/半導體障壁即形成於 該第二金屬層與設在併排溝槽612間之凸台618的頂面之間 的接面處。 第6A圖所示之該肖特基障壁整流器的頂視或“佈局” 圖乃被示於第6B圖中。如所示，具有寬度WT的併排溝槽612 本紙張尺度適用中國國家標準（CNS) A4規格⑵狀撕公楚） 五、發明説明（7 ) ^會被以凸台寬产為來分開。並以-具有^尺寸的門 隙來與該周邊溝槽614分開。該等間隙乃用來減少 圖中所示之習知刪整流器中可見到的電場集結作用。在 一較佳貧施例中，該Wg係大致等於Wm/2。 使用第6A與6B圖中所示的“斷開溝槽，，結構，將會產生 比使用第5B圖所示之習知溝槽結構所可得到者高出甚多 =崩潰電壓。第7圖係比較許多分別具有如第6a、6b圖與 第5A、5B圖之不同溝槽結構的肖特基障壁整流器所測得的 崩潰電壓。由該等樣本範例，乃可看出本發明之實施例的 崩潰電壓會比具有習知溝槽結構之例高出丨〇 v以上。 本發明之“斷開溝槽，，概念並不僅限使用於肖特基障壁 整流器類型的裝置中。事實上，本發明的發明人等亦曾思 量該等“斷開溝槽，，結構當可與任何其它半導體裝置來整 合，而對其性能有所助益。此基本概念係包含一系列並排 的溝槽及一可擇的垂向周邊溝槽設在一半導體層中。本發 明之此概念的一應用例乃示於第8圖中。 第8圖係示出本發明另一實施例之該溝槽結構與一雙 重擴散的射頻％效應電晶體（即RF FET)之整合。rf FET係 為一垂直裝置，包含源極區800其具有一第一種導電性（例η 型）而被設在具有第二種導電性（例如ρ型）的井802中；一第 一種導電性的汲極804乃具有一汲極接觸部806 ; 一第一種 導電性的磊晶層808設在該等井802與汲極804之間；及一閘 極810覆設在一閘氧化物812上。雖未示於第8圖中，但該等 源極區800將會互相連接來形成單一源極。該rf FET本身 10 本紙張尺度適用中國國家標準（CNS) Α4規格（210X297公釐） 550739 發明説明 的操作係公知於該領域中，故不再冗述。 與該RF FET等人姜总达 / °書係為一糸列的併排溝槽814及一周 :溝編，_象本發明之另一實施例來形成一函 槽RFFET 80。該周邊及併排溝槽816與814等皆會被覆 1電貝818。該等以介電質覆襯的溝槽將會被-導電材 料(未播第8圖）來填滿，例如金屬或摻雜多晶石夕。又，雖 ;第圖中‘電金屬亦會被覆設在該RF FET基材 80的整個頂面上。 雖以上為本發明之一較佳實施例的完整描述’但各種 變化、修正及等效結構等亦可使用。例如，本發明之基本 的_開漠槽”概念亦可與其它類型的半導體裝置整合， 來增強其崩潰特性。因此，本發明的斷開溝槽概念乃不 被視為僅可供應用於在此所提供之肖特基障壁整流器 RFFET等例中。為此及其它的理由，故上述說明並不應傲 :來限制本發明的範圍，其乃應由所附申請專利範圍來界 疋° 本紙張尺度適用中國國家標準（as) A4規格（2〗〇X297公爱） 而 應 及 被
f (請先閲讀背面之注意事項再填寫本頁) 、一 =& 11 550739 A7 B7 五、發明説明（9 ) 元件標號對照 10…肖特基障壁整流器 512…溝槽 50…MBS整流器 514…終結溝槽 60···半導體裝置結構 516、616、818…介電質 80-.MOS溝槽RF FET 518…導電材料 100、508、600···第一金屬層 522、618…凸台 102、602···半導體層 612、814…併排溝槽 104、504、604、808···磊 614、816…周邊溝槽 晶層 800…源極區 106、506、606···基材 802…井 108、520···第二金屬層 804···汲極 110…空乏區 806…汲極接觸部 400…P型區 810…閘極 402…漂移區 502…半導體層 812…閘氧化物 f (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS) Α4規格（210X297公釐） 12

Claims (1)

  1. 550739 、申清專利範園 槽^_半導體裝置整合而可增強該 ，-衣置的朋>貝特性，該M〇s溝槽結構包含·· 一半導體基材； 多數的併排溝槽設在該半導體基 壁及底部所形成，且各二相鄰的= 該半導體裝置的凸台所分開，而铜具有— 一周邊溝槽係由端部、侧壁及底部所形成，該周邊 至少會部份地包圍該等併排溝槽，且該周邊溝槽合 一介電材料覆襯該等併排與周邊溝槽，·及 -導電材料完全填滿該等介電材料覆襯的溝槽。 2.如申請專利範隊項之娜㈣槽結構 槽對周邊溝槽的間隔係約等於該凸台寬度的_半:排屢 3·如申請專利範圍第1項之M0S溝槽結構，其中該半 基材包含： ' — 一半導體接觸層其中設有該等溝槽；及 一磊晶生成的半導體層設在該接觸層的第一主表 面上，而具有較低於該接觸層的摻雜濃产。 4·如申請專利範圍第3項之MOS溝槽結構，更包含： 一第一金屬接觸層設斧f半導體接觸二二相反 的第二主表面上。 ' 輪、 置 t 5·如申請專利範圍第4項之MO&1，其中該半導體掌 本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） 六、申請專利範圍 更包含 而…第二災覆蓋在該等凸台及介電材料覆概 而填滿v電材排溝槽和周邊溝槽上。 6. -種MOS溝槽結肖特基障壁整流器整合而可 乓強該半導體裝置·潰特性，該m〇s溝槽結構包含： 一半導體接觸層； 一磊晶生成的半導體層設在該接觸層之一第一主 表面上，而具有_較低於該接觸層的摻雜濃度； 一第一金屬接觸層設在該半導體接觸層之一相反 的弟一主表面上； 夕數的併排溝槽設在該磊晶生成的半導體層中，該 各溝槽係ώ端部、侧壁及底部所形成，且各二相鄰的併 排溝槽係被具有一凸台寬度的凸台來分開； 一周邊溝槽係由端部、側壁及底部來形成，該周邊 溝槽至少會部份地包圍該等併排溝槽，且該周邊溝槽會 以一併排溝槽對周邊溝槽的間隔來與該等併排溝槽的 端部隔開； 一介電材料覆襯著該等併排與周邊溝槽； ‘電材料完全填滿該等覆襯著介電材料的溝 槽；及 一第二金屬接觸層覆蓋該等凸台及填滿導電材料 的併排溝槽和周邊溝槽。 如申請專利範圍第6項之結構，其中該第一與第二金屬 接觸層係包含該肖特基障壁整流器的陰極及陽極接觸 部0 550739 六、申請專利範圚 8. =請專利_第6項之結構，其中該併麟 溝槽的間隔係該凸台寬度的-半。 9. 種MOS溝槽結讀矣一射頻場效應電 =而可料前^^潰特性，獅s溝槽料 一半導體接觸層具有-第-種導電性；及 ^ 猫日日生成的半導體層設在該半導體接觸層之一 第一表面上，而具有與該半導體接觸層同種的導電性， 但具有較高的摻雜濃度； 一第一金屬接觸層設在該半導體接觸層之一相反 的弟二主表面上； 訂 多數的併排溝槽設在該蟲晶生成的半導體層上，該 各溝槽係由端部、侧壁及底部所形成，而各二相鄰的併 排溝槽係被具有一凸台寬度的凸台所分開； 周邊溝槽係由端部、侧壁及底部所形成，該周邊 t 溝槽會至少部份地包圍該等併排溝槽，且該周邊溝槽係 以一併排溝槽對周邊溝槽間隔來與該等併排溝槽的端 部隔開； 曰 一介電材料覆襯著該等併排與周邊溝槽；及 一導電材料完全填滿該等覆襯著介電材料的溝槽。 1〇.如申請專利範圍第9項之結構，其中該RF FET包含： 多數第二種導電性的井區設在該等凸台的上邊角 處，在一凸台中之各二井區係以一間隙來分開·， 該第一種導電性的源極區設在該等井區中·及 本紙張尺度適用中國國家標準（⑽）A4規格（210X297公楚） 550739 申清專利範園 閘極區覆設在該等源極區及在各凸台中之部份間 U·如申請專利範項之結構，其中該併排溝槽對周邊 溝槽的間隔係磁乘寒、凸台寬度的一半。 12· γ種MOS溝槽結;半導體裝置整合而可增強該 半導體裝置的崩潰特性Γ包含： 曰人 一半導體基材； 多數的併排溝槽設在該半導體基材中； 周邊溝槽與该等併排溝槽分開，並至少部份地包 圍該等併排溝槽； 一介電材料覆襯著該等溝槽的底部和側壁；及 ‘電材料完全填滿該等覆概著介電材料的溝槽。 本紙張尺度適用中國國家標準（CNS) Α4規格（210X297公釐) 16
TW091114617A 2001-07-03 2002-07-02 Trench structure for semiconductor devices TW550739B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/898,133 US6683363B2 (en) 2001-07-03 2001-07-03 Trench structure for semiconductor devices

Publications (1)

Publication Number Publication Date
TW550739B true TW550739B (en) 2003-09-01

Family

ID=25408993

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091114617A TW550739B (en) 2001-07-03 2002-07-02 Trench structure for semiconductor devices

Country Status (6)

Country Link
US (1) US6683363B2 (zh)
JP (1) JP4328616B2 (zh)
AU (1) AU2002329197A1 (zh)
DE (1) DE10297021B4 (zh)
TW (1) TW550739B (zh)
WO (1) WO2003005416A2 (zh)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7786533B2 (en) * 2001-09-07 2010-08-31 Power Integrations, Inc. High-voltage vertical transistor with edge termination structure
JP3701227B2 (ja) * 2001-10-30 2005-09-28 三菱電機株式会社 半導体装置及びその製造方法
US7652326B2 (en) 2003-05-20 2010-01-26 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
CN103199017B (zh) * 2003-12-30 2016-08-03 飞兆半导体公司 形成掩埋导电层方法、材料厚度控制法、形成晶体管方法
FR2879024A1 (fr) * 2004-12-08 2006-06-09 St Microelectronics Sa Peripherie de composant unipolaire vertical
US7535057B2 (en) * 2005-05-24 2009-05-19 Robert Kuo-Chang Yang DMOS transistor with a poly-filled deep trench for improved performance
US7595542B2 (en) * 2006-03-13 2009-09-29 Fairchild Semiconductor Corporation Periphery design for charge balance power devices
US7592668B2 (en) * 2006-03-30 2009-09-22 Fairchild Semiconductor Corporation Charge balance techniques for power devices
KR101630734B1 (ko) 2007-09-21 2016-06-16 페어차일드 세미컨덕터 코포레이션 전력 소자
US20090085148A1 (en) * 2007-09-28 2009-04-02 Icemos Technology Corporation Multi-directional trenching of a plurality of dies in manufacturing superjunction devices
US8174067B2 (en) * 2008-12-08 2012-05-08 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US8304829B2 (en) * 2008-12-08 2012-11-06 Fairchild Semiconductor Corporation Trench-based power semiconductor devices with increased breakdown voltage characteristics
US8227855B2 (en) * 2009-02-09 2012-07-24 Fairchild Semiconductor Corporation Semiconductor devices with stable and controlled avalanche characteristics and methods of fabricating the same
US8148749B2 (en) * 2009-02-19 2012-04-03 Fairchild Semiconductor Corporation Trench-shielded semiconductor device
US8049276B2 (en) * 2009-06-12 2011-11-01 Fairchild Semiconductor Corporation Reduced process sensitivity of electrode-semiconductor rectifiers
US8319290B2 (en) 2010-06-18 2012-11-27 Fairchild Semiconductor Corporation Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
CN102315253A (zh) * 2010-06-30 2012-01-11 力士科技股份有限公司 一种半导体功率器件的布局设计
CN102569428B (zh) * 2010-12-21 2015-06-03 上海华虹宏力半导体制造有限公司 纵向电压控制变容器及其制备方法
US8872278B2 (en) 2011-10-25 2014-10-28 Fairchild Semiconductor Corporation Integrated gate runner and field implant termination for trench devices
US9331197B2 (en) 2013-08-08 2016-05-03 Cree, Inc. Vertical power transistor device
US10868169B2 (en) 2013-09-20 2020-12-15 Cree, Inc. Monolithically integrated vertical power transistor and bypass diode
US10600903B2 (en) * 2013-09-20 2020-03-24 Cree, Inc. Semiconductor device including a power transistor device and bypass diode
US9553184B2 (en) * 2014-08-29 2017-01-24 Nxp Usa, Inc. Edge termination for trench gate FET
US9397213B2 (en) 2014-08-29 2016-07-19 Freescale Semiconductor, Inc. Trench gate FET with self-aligned source contact
US20160247879A1 (en) * 2015-02-23 2016-08-25 Polar Semiconductor, Llc Trench semiconductor device layout configurations
US9680003B2 (en) 2015-03-27 2017-06-13 Nxp Usa, Inc. Trench MOSFET shield poly contact
WO2017187856A1 (ja) * 2016-04-27 2017-11-02 三菱電機株式会社 半導体装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4974059A (en) * 1982-12-21 1990-11-27 International Rectifier Corporation Semiconductor high-power mosfet device
US5262336A (en) 1986-03-21 1993-11-16 Advanced Power Technology, Inc. IGBT process to produce platinum lifetime control
US4796070A (en) * 1987-01-15 1989-01-03 General Electric Company Lateral charge control semiconductor device and method of fabrication
US5233215A (en) 1992-06-08 1993-08-03 North Carolina State University At Raleigh Silicon carbide power MOSFET with floating field ring and floating field plate
US5430324A (en) 1992-07-23 1995-07-04 Siliconix, Incorporated High voltage transistor having edge termination utilizing trench technology
US5365102A (en) * 1993-07-06 1994-11-15 North Carolina State University Schottky barrier rectifier with MOS trench
EP0698919B1 (en) 1994-08-15 2002-01-16 Siliconix Incorporated Trenched DMOS transistor fabrication using seven masks
US5597765A (en) 1995-01-10 1997-01-28 Siliconix Incorporated Method for making termination structure for power MOSFET
US5949124A (en) 1995-10-31 1999-09-07 Motorola, Inc. Edge termination structure
DE19611045C1 (de) * 1996-03-20 1997-05-22 Siemens Ag Durch Feldeffekt steuerbares Halbleiterbauelement
US5612567A (en) * 1996-05-13 1997-03-18 North Carolina State University Schottky barrier rectifiers and methods of forming same
US5972741A (en) * 1996-10-31 1999-10-26 Sanyo Electric Co., Ltd. Method of manufacturing semiconductor device
US5877528A (en) 1997-03-03 1999-03-02 Megamos Corporation Structure to provide effective channel-stop in termination areas for trenched power transistors
US6104054A (en) * 1998-05-13 2000-08-15 Texas Instruments Incorporated Space-efficient layout method to reduce the effect of substrate capacitance in dielectrically isolated process technologies
US6252258B1 (en) * 1999-08-10 2001-06-26 Rockwell Science Center Llc High power rectifier
JP2001102576A (ja) * 1999-09-29 2001-04-13 Sanyo Electric Co Ltd 半導体装置

Also Published As

Publication number Publication date
US6683363B2 (en) 2004-01-27
JP2004535064A (ja) 2004-11-18
AU2002329197A1 (en) 2003-01-21
WO2003005416A3 (en) 2003-09-25
US20030006452A1 (en) 2003-01-09
DE10297021T5 (de) 2004-08-05
JP4328616B2 (ja) 2009-09-09
WO2003005416A2 (en) 2003-01-16
DE10297021B4 (de) 2012-02-23

Similar Documents

Publication Publication Date Title
TW550739B (en) Trench structure for semiconductor devices
US11081554B2 (en) Insulated gate semiconductor device having trench termination structure and method
US10069005B2 (en) Termination design for high voltage device
US8680643B2 (en) Junction barrier Schottky (JBS) with floating islands
US6750508B2 (en) Power semiconductor switching element provided with buried electrode
JP4702822B2 (ja) 終端構造及びトレンチ金属酸化膜半導体素子
US11658241B2 (en) Vertical trench gate MOSFET with integrated Schottky diode
US6710418B1 (en) Schottky rectifier with insulation-filled trenches and method of forming the same
US7196397B2 (en) Termination design with multiple spiral trench rings
US20150162410A1 (en) Termination design by metal strapping guard ring trenches shorted to a body region to shrink termination area
US20040222461A1 (en) Lateral semiconductor device with low on-resistance and method of making the same
US20100006927A1 (en) Charge Balance Techniques for Power Devices
CN111081779B (zh) 一种屏蔽栅沟槽式mosfet及其制造方法
US20220384627A1 (en) Semiconductor device
US10164087B2 (en) Semiconductor device and method of manufacturing same
JP2009038318A (ja) 半導体装置
US9059147B1 (en) Junction barrier schottky (JBS) with floating islands
JP2005531141A (ja) 端部構造を有する半導体装置
CN112447847A (zh) 半导体装置及其制造方法
JP2006049455A (ja) トレンチ型絶縁ゲート半導体装置
De Souza et al. A novel area efficient floating field limiting ring edge termination technique
JP5938242B2 (ja) ダイオード
CN113875021A (zh) 空间高效的高压终端及其制造工艺
KR20060006220A (ko) 쇼트키 장벽접합을 갖는 반도체 소자 및 그 제조방법

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees