JP4318607B2 - 強誘電体キャパシタの製造方法 - Google Patents

強誘電体キャパシタの製造方法 Download PDF

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Publication number
JP4318607B2
JP4318607B2 JP2004220156A JP2004220156A JP4318607B2 JP 4318607 B2 JP4318607 B2 JP 4318607B2 JP 2004220156 A JP2004220156 A JP 2004220156A JP 2004220156 A JP2004220156 A JP 2004220156A JP 4318607 B2 JP4318607 B2 JP 4318607B2
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JP
Japan
Prior art keywords
film
forming
interlayer insulating
etching
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004220156A
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English (en)
Japanese (ja)
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JP2006041246A5 (https=
JP2006041246A (ja
Inventor
敏雄 伊東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lapis Semiconductor Co Ltd
Original Assignee
Oki Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Semiconductor Co Ltd filed Critical Oki Semiconductor Co Ltd
Priority to JP2004220156A priority Critical patent/JP4318607B2/ja
Priority to US11/105,439 priority patent/US7157288B2/en
Publication of JP2006041246A publication Critical patent/JP2006041246A/ja
Publication of JP2006041246A5 publication Critical patent/JP2006041246A5/ja
Application granted granted Critical
Publication of JP4318607B2 publication Critical patent/JP4318607B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/694—Electrodes comprising noble metals or noble metal oxides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials

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  • Semiconductor Memories (AREA)
JP2004220156A 2004-07-28 2004-07-28 強誘電体キャパシタの製造方法 Expired - Fee Related JP4318607B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2004220156A JP4318607B2 (ja) 2004-07-28 2004-07-28 強誘電体キャパシタの製造方法
US11/105,439 US7157288B2 (en) 2004-07-28 2005-04-14 Method of producing ferroelectric capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004220156A JP4318607B2 (ja) 2004-07-28 2004-07-28 強誘電体キャパシタの製造方法

Publications (3)

Publication Number Publication Date
JP2006041246A JP2006041246A (ja) 2006-02-09
JP2006041246A5 JP2006041246A5 (https=) 2006-11-30
JP4318607B2 true JP4318607B2 (ja) 2009-08-26

Family

ID=35905912

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004220156A Expired - Fee Related JP4318607B2 (ja) 2004-07-28 2004-07-28 強誘電体キャパシタの製造方法

Country Status (2)

Country Link
US (1) US7157288B2 (https=)
JP (1) JP4318607B2 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4621081B2 (ja) * 2005-07-07 2011-01-26 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
JP4838613B2 (ja) * 2006-03-28 2011-12-14 富士通セミコンダクター株式会社 半導体装置の製造方法
JP2009071241A (ja) * 2007-09-18 2009-04-02 Seiko Epson Corp 半導体装置及びその製造方法
US8451308B2 (en) 2009-07-31 2013-05-28 Ricoh Company, Ltd. Image forming apparatus

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0131743B1 (ko) * 1993-12-28 1998-04-15 김주용 디램셀의 저장전극 형성방법
US6495413B2 (en) * 2001-02-28 2002-12-17 Ramtron International Corporation Structure for masking integrated capacitors of particular utility for ferroelectric memory integrated circuits
US6423592B1 (en) * 2001-06-26 2002-07-23 Ramtron International Corporation PZT layer as a temporary encapsulation and hard mask for a ferroelectric capacitor
US20030143853A1 (en) * 2002-01-31 2003-07-31 Celii Francis G. FeRAM capacitor stack etch
US6753247B1 (en) * 2002-10-31 2004-06-22 Advanced Micro Devices, Inc. Method(s) facilitating formation of memory cell(s) and patterned conductive
US7001821B2 (en) * 2003-11-10 2006-02-21 Texas Instruments Incorporated Method of forming and using a hardmask for forming ferroelectric capacitors in a semiconductor device

Also Published As

Publication number Publication date
US7157288B2 (en) 2007-01-02
US20060046315A1 (en) 2006-03-02
JP2006041246A (ja) 2006-02-09

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