JP4295680B2 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 41
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- 101100537098 Mus musculus Alyref gene Proteins 0.000 description 1
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Description
Id=IM−Σi=0〜kIleaki
IM1=Id1−Σi=0〜kIleak1i
IM2=Id2+Σi=0〜kIleak2i
Vdi=(V1−V2’)×Ri/(Ri+R)
Vdij=(V1−V2’)×Rij/(Rij+R+Rbsj)
図1に、複数のメモリセルアレイ10からなるバンク構造を採用するメモリセルアレイ構成と各メモリセルアレイの読み出し動作に関連する主要部分のブロック構成を示す。各メモリセルアレイ10は、図2に例示するクロスポイントタイプのメモリセルアレイ構造で、電気抵抗の変化により3値以上の多値情報を記憶する可変抵抗素子からなるメモリセルMCを行方向及び列方向に夫々複数アレイ状に配列し、行方向に延伸する複数のデータ線(行選択線)DLと列方向に延伸する複数のビット線(列選択線)BLを備え、同一行のメモリセルMCの夫々が、可変抵抗素子の一端側を同じデータ線DLに接続し、同一列のメモリセルMCの夫々が、可変抵抗素子の他端側を同じビット線BLに接続して構成されている。メモリセルアレイ10は、一例として、16行×16列または64行×64列のアレイサイズで、この場合、データ線とビット線は夫々16本である。尚、以下の説明において、メモリセルMCが記憶する多値情報は4値(2ビット)の場合を想定する。
次に、メモリセルアレイ中のメモリセルの抵抗状態の各種分布パターン(パターンA〜H)について、図8を参照して説明する。尚、図8は、各分布パターンの特徴を説明するために、8行×12列の簡略的なアレイサイズを示しているが、このアレイサイズは必ずしも実際のアレイサイズを示すものではない。尚、図8において、網掛け部分(濃色部分)が高抵抗メモリセルが分布している領域を表している。
Ib0=Σi=0〜nIdi
これは、強磁性金属体と、反磁性絶縁体との2相にて、状態が変化することによって、メモリセル素子を構成するPCMO等のMn酸化物系材料の抵抗値が変化することを利用するものである。
上記第1実施形態では、図1において、選択された1つのメモリセルアレイ10から1つのデータ線を選択して1つのメモリセルの4値データを読み出す場合に、3つのセンス回路15を並列に使用して、3つのリファレンスレベルとの比較を同時に行う場合を説明したが、1つのセンス回路15を3つのリファレンスレベルに対して時間的に順番に切り替えて使用する形態について説明する。
VHRmax > Vref
Vref > VLRmin
Vmeas < VLRmin
Vmeas > VHRmax
11: データ線ドライブ回路
12: ビット線ドライブ回路
13: 行デコーダ
14: 列デコーダ
15: センス回路
20a、20b: 第1リファレンスレベル用のリファレンスメモリセルアレイ
20c、20d: 第2リファレンスレベル用のリファレンスメモリセルアレイ
20e、20f: 第3リファレンスレベル用のリファレンスメモリセルアレイ
21: データ線ドライブ回路
22: ビット線ドライブ回路
24: 列デコーダ
30: 行読出し電圧供給回路
31: 行電圧変位抑制回路
32: NチャネルMOSFET
33: フィードバック回路部(インバータ)
40: 列読出し電圧供給回路
41: 列電圧変位抑制回路
42: PチャネルMOSFET
43、44: CMOS転送ゲート
45: 列選択回路
46: NチャネルMOSFET
47: フィードバック回路部(インバータ)
51: 第1電流電圧変換回路部
52: 第2電流電圧変換回路部
53: 比較回路
54,55、58: PチャネルMOSFET
56、57、59,60: NチャネルMOSFET
70、71: アレイ選択トランジスタ
Vcc: 電源電圧
Vss: 接地電圧
Vref0、Vref1: リファレンスメモリセルアレイ対の出力電圧
Vm: 行読出し電圧供給回路の出力電圧(負荷PMOSのドレイン電圧)
BL: ビット線
DL: データ線
GBL: グローバルビット線
GDL: グローバルデータ線
MC: メモリセル
Claims (5)
- 電気抵抗の変化により3値以上の多値情報を記憶する可変抵抗素子からなるメモリセルを行方向及び列方向に夫々複数配列し、行方向に延伸する複数の行選択線と列方向に延伸する複数の列選択線を備え、同一行の前記メモリセルの夫々が、前記可変抵抗素子の一端側を同じ前記行選択線に接続し、同一列の前記メモリセルの夫々が、前記可変抵抗素子の他端側を同じ前記列選択線に接続してなるメモリセルアレイを有する半導体記憶装置であって、
前記列選択線の夫々に、読出し選択時に所定の第1電圧を供給し、読出し非選択時に前記第1電圧と異なる第2電圧を供給する列読出し電圧供給回路を備え、
前記行選択線の夫々に、読出し時に前記第2電圧を供給する行読出し電圧供給回路を備え、
読出し時において、選択された前記行選択線を流れる電流を、非選択の前記行選択線を流れる電流と分離して検知して、選択された前記メモリセルの電気抵抗状態を検知するセンス回路を備え、
読出し時において、少なくとも選択された前記行選択線に対して、供給した電圧レベルの変位を抑制する行電圧変位抑制回路を備え、
前記メモリセルが記憶する多値情報の各記憶レベルを対応する前記可変抵抗素子の抵抗値の分布範囲の大小順に並べた場合の隣接する2つの前記記憶レベル間の各リファレンスレベルが、選択された前記メモリセルの電気抵抗が前記2つの記憶レベルの高抵抗側の抵抗状態にある高抵抗メモリセルの読出し時において選択された前記行選択線を流れる電流が前記メモリセルアレイの他の非選択の前記メモリセルの電気抵抗状態の分布パターンに依存して最大状態となる第1電流状態と、選択された前記メモリセルの電気抵抗が前記2つの記憶レベルの低抵抗側の抵抗状態にある低抵抗メモリセルの読出し時において選択された前記行選択線を流れる電流が前記メモリセルアレイの他の非選択の前記メモリセルの電気抵抗状態の分布パターンに依存して最小状態となる第2電流状態の中間状態のリファレンス電流によって夫々規定され、
前記センス回路が、選択された前記行選択線を流れる電流と前記各リファレンスレベルに対応する前記各リファレンス電流と比較可能に構成されていることを特徴とする半導体記憶装置。 - 前記センス回路は、
選択された前記行選択線を流れる電流を読出し電圧レベルに変換する第1電流電圧変換回路部と、
前記各リファレンスレベルの前記第1電流状態を各別に近似的に実現する第1リファレンス電流発生回路と、
前記各リファレンスレベルの前記第2電流状態を各別に近似的に実現する第2リファレンス電流発生回路と、
前記各リファレンスレベルの前記リファレンス電流をリファレンス電圧レベルに各別に変換する第2電流電圧変換回路部と、
前記読出し電圧レベルと前記各リファレンス電圧レベルを比較する比較回路と、
を備えてなることを特徴とする請求項1に記載の半導体記憶装置。 - 前記各リファレンスレベルの前記第1リファレンス電流発生回路と前記第2リファレンス電流発生回路の夫々は、前記メモリセルと同じ前記可変抵抗素子からなるリファレンスメモリセルを備えてなる前記メモリセルアレイと等価な構成のリファレンスメモリセルアレイと、前記列読出し電圧供給回路と等価な構成のリファレンス列読出し電圧供給回路と、前記行読出し電圧供給回路と等価な構成のリファレンス行読出し電圧供給回路と、を備え、
前記各リファレンスレベルの前記第1リファレンス電流発生回路の前記リファレンスメモリセルアレイにおける前記リファレンスメモリセルの電気抵抗状態の分布パターンは、選択された前記リファレンスメモリセルアレイの行選択線を流れる電流が前記各リファレンスレベルの前記第1電流状態となる第1分布パターンに設定され、
前記各リファレンスレベルの前記第2リファレンス電流発生回路の前記リファレンスメモリセルアレイにおける前記リファレンスメモリセルの電気抵抗状態の分布パターンは、選択された前記リファレンスメモリセルアレイの行選択線を流れる電流が前記各リファレンスレベルの前記第2電流状態となる第2分布パターンに設定されていることを特徴とする請求項2に記載の半導体記憶装置。 - 前記リファレンスメモリセルアレイの前記リファレンスメモリセル、前記行選択線、及び、前記列選択線の各個数は、前記メモリセルアレイの前記メモリセル、前記行選択線、及び、前記列選択線の対応する各個数と同じであることを特徴とする請求項3に記載の半導体記憶装置。
- 前記メモリセルアレイを複数備え、
複数の前記メモリセルアレイの内の少なくとも2つの前記メモリセルアレイに対する前記センス回路が、前記第1リファレンス電流発生回路と前記第2リファレンス電流発生回路を共通に利用することを特徴とする請求項2〜4の何れか1項に記載の半導体記憶装置。
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TW094119850A TWI289846B (en) | 2004-06-15 | 2005-06-15 | Semiconductor memory device |
US11/154,376 US7239540B2 (en) | 2004-06-15 | 2005-06-15 | Semiconductor memory device |
KR1020050051302A KR100681790B1 (ko) | 2004-06-15 | 2005-06-15 | 반도체 기억장치 |
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JP4153901B2 (ja) * | 2004-06-15 | 2008-09-24 | シャープ株式会社 | 半導体記憶装置 |
JP4762720B2 (ja) * | 2006-01-05 | 2011-08-31 | 富士通株式会社 | 磁気半導体記憶装置の読出し回路 |
US8027184B2 (en) | 2006-03-06 | 2011-09-27 | Nec Corporation | Semiconductor storage device and operating method of the same |
US8395199B2 (en) | 2006-03-25 | 2013-03-12 | 4D-S Pty Ltd. | Systems and methods for fabricating self-aligned memory cell |
JP4199781B2 (ja) | 2006-04-12 | 2008-12-17 | シャープ株式会社 | 不揮発性半導体記憶装置 |
US8454810B2 (en) | 2006-07-14 | 2013-06-04 | 4D-S Pty Ltd. | Dual hexagonal shaped plasma source |
US7932548B2 (en) | 2006-07-14 | 2011-04-26 | 4D-S Pty Ltd. | Systems and methods for fabricating self-aligned memory cell |
KR101446581B1 (ko) * | 2006-07-31 | 2014-10-06 | 쌘디스크 3디 엘엘씨 | 멀티-레벨 수동 소자 메모리 셀 어레이를 판독하는 방법과 장치 |
US7542338B2 (en) * | 2006-07-31 | 2009-06-02 | Sandisk 3D Llc | Method for reading a multi-level passive element memory cell array |
US8279704B2 (en) | 2006-07-31 | 2012-10-02 | Sandisk 3D Llc | Decoder circuitry providing forward and reverse modes of memory array operation and method for biasing same |
US7542337B2 (en) * | 2006-07-31 | 2009-06-02 | Sandisk 3D Llc | Apparatus for reading a multi-level passive element memory cell array |
US8308915B2 (en) | 2006-09-14 | 2012-11-13 | 4D-S Pty Ltd. | Systems and methods for magnetron deposition |
US8164941B2 (en) * | 2006-12-27 | 2012-04-24 | Hynix Semiconductor Inc. | Semiconductor memory device with ferroelectric device and refresh method thereof |
KR100886215B1 (ko) | 2006-12-27 | 2009-03-02 | 삼성전자주식회사 | 저항체를 이용한 비휘발성 메모리 장치 |
US8139432B2 (en) | 2006-12-27 | 2012-03-20 | Samsung Electronics Co., Ltd. | Variable resistance memory device and system thereof |
US7400521B1 (en) * | 2007-01-12 | 2008-07-15 | Qimoda Ag | Integrated circuit, memory chip and method of evaluating a memory state of a resistive memory cell |
KR100919565B1 (ko) * | 2007-07-24 | 2009-10-01 | 주식회사 하이닉스반도체 | 상 변화 메모리 장치 |
JP5161981B2 (ja) * | 2008-12-11 | 2013-03-13 | 株式会社日立製作所 | 半導体装置 |
US7889585B2 (en) * | 2008-12-18 | 2011-02-15 | Qualcomm Incorporated | Balancing a signal margin of a resistance based memory circuit |
JP5379337B1 (ja) | 2012-03-29 | 2013-12-25 | パナソニック株式会社 | クロスポイント型抵抗変化不揮発性記憶装置 |
US9183910B2 (en) | 2012-05-31 | 2015-11-10 | Samsung Electronics Co., Ltd. | Semiconductor memory devices for alternately selecting bit lines |
US8861256B2 (en) * | 2012-09-28 | 2014-10-14 | Hewlett-Packard Development Company, L.P. | Data storage in memory array with less than half of cells in any row and column in low-resistance states |
US8949567B2 (en) | 2013-02-26 | 2015-02-03 | Seagate Technology Llc | Cross-point resistive-based memory architecture |
EP3100132B1 (en) | 2014-01-31 | 2021-06-30 | Hewlett-Packard Development Company, L.P. | Output voltage to serial communicaton port |
JP2020087493A (ja) * | 2018-11-26 | 2020-06-04 | キオクシア株式会社 | 半導体記憶装置 |
JP6887457B2 (ja) * | 2019-03-01 | 2021-06-16 | 力晶積成電子製造股▲ふん▼有限公司Powerchip Semiconductor Manufacturing Corporation | 基準電圧発生回路及び不揮発性半導体記憶装置 |
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JP4187197B2 (ja) * | 2002-11-07 | 2008-11-26 | シャープ株式会社 | 半導体メモリ装置の制御方法 |
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JP2006004479A (ja) | 2006-01-05 |
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