JP4294696B2 - 半導体装置の製造方法および製造装置、ならびに記憶媒体 - Google Patents

半導体装置の製造方法および製造装置、ならびに記憶媒体 Download PDF

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Publication number
JP4294696B2
JP4294696B2 JP2007024212A JP2007024212A JP4294696B2 JP 4294696 B2 JP4294696 B2 JP 4294696B2 JP 2007024212 A JP2007024212 A JP 2007024212A JP 2007024212 A JP2007024212 A JP 2007024212A JP 4294696 B2 JP4294696 B2 JP 4294696B2
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Japan
Prior art keywords
chamber
gas
semiconductor device
manufacturing
nitriding
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Expired - Fee Related
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JP2007024212A
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English (en)
Japanese (ja)
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JP2008192739A (ja
JP2008192739A5 (https=
Inventor
卓司 佐古
勇作 柏木
宏至 戸島
薫 前川
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Priority to JP2007024212A priority Critical patent/JP4294696B2/ja
Priority to TW097100722A priority patent/TW200842977A/zh
Priority to US12/024,445 priority patent/US20080184543A1/en
Publication of JP2008192739A publication Critical patent/JP2008192739A/ja
Publication of JP2008192739A5 publication Critical patent/JP2008192739A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32192—Microwave generated discharge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/27—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
    • H10P70/277—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers the processing being a planarisation of conductive layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/047—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein
    • H10W20/048—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein by using plasmas or gaseous environments, e.g. by nitriding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/055—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
JP2007024212A 2007-02-02 2007-02-02 半導体装置の製造方法および製造装置、ならびに記憶媒体 Expired - Fee Related JP4294696B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2007024212A JP4294696B2 (ja) 2007-02-02 2007-02-02 半導体装置の製造方法および製造装置、ならびに記憶媒体
TW097100722A TW200842977A (en) 2007-02-02 2008-01-08 Method and apparatus for manufacturing semiconductor device, and storage medium for executing the method
US12/024,445 US20080184543A1 (en) 2007-02-02 2008-02-01 Method and apparatus for manufacturing semiconductor device, and storage medium for executing the method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007024212A JP4294696B2 (ja) 2007-02-02 2007-02-02 半導体装置の製造方法および製造装置、ならびに記憶媒体

Publications (3)

Publication Number Publication Date
JP2008192739A JP2008192739A (ja) 2008-08-21
JP2008192739A5 JP2008192739A5 (https=) 2008-10-16
JP4294696B2 true JP4294696B2 (ja) 2009-07-15

Family

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Family Applications (1)

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JP2007024212A Expired - Fee Related JP4294696B2 (ja) 2007-02-02 2007-02-02 半導体装置の製造方法および製造装置、ならびに記憶媒体

Country Status (3)

Country Link
US (1) US20080184543A1 (https=)
JP (1) JP4294696B2 (https=)
TW (1) TW200842977A (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008028850A1 (en) * 2006-09-04 2008-03-13 Koninklijke Philips Electronics N.V. CuSiN/SiN DIFFUSION BARRIER FOR COPPER IN INTEGRATED-CIRCUIT DEVICES
JP5781720B2 (ja) 2008-12-15 2015-09-24 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
JP5582727B2 (ja) 2009-01-19 2014-09-03 株式会社東芝 半導体装置の製造方法及び半導体装置
KR20120064966A (ko) * 2010-12-10 2012-06-20 에스케이하이닉스 주식회사 반도체 장치 제조 방법
US9330915B2 (en) * 2013-12-10 2016-05-03 Taiwan Semiconductor Manufacturing Co., Ltd. Surface pre-treatment for hard mask fabrication
US9385086B2 (en) 2013-12-10 2016-07-05 Taiwan Semiconductor Manufacturing Co., Ltd. Bi-layer hard mask for robust metallization profile
JP5856227B2 (ja) * 2014-05-26 2016-02-09 ルネサスエレクトロニクス株式会社 半導体装置
JP2016111104A (ja) * 2014-12-03 2016-06-20 株式会社Ｊｏｌｅｄ 薄膜半導体基板の製造方法
JP6593635B2 (ja) * 2014-12-24 2019-10-23 株式会社ジェイテクト 樹脂製部材の製造方法
KR20240041664A (ko) * 2022-09-23 2024-04-01 주식회사 에이치피에스피 반도체 소자의 제조 방법
JP2025099459A (ja) * 2023-12-21 2025-07-03 東京エレクトロン株式会社 基板処理方法及び基板処理装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000063956A1 (en) * 1999-04-20 2000-10-26 Sony Corporation Method and apparatus for thin-film deposition, and method of manufacturing thin-film semiconductor device
DE69940114D1 (de) * 1999-08-17 2009-01-29 Applied Materials Inc Oberflächenbehandlung von kohlenstoffdotierten SiO2-Filmen zur Erhöhung der Stabilität während der O2-Veraschung
US6756239B1 (en) * 2003-04-15 2004-06-29 Hewlett-Packard Development Company, L.P. Method for constructing a magneto-resistive element
JP4516447B2 (ja) * 2005-02-24 2010-08-04 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP4509864B2 (ja) * 2005-05-30 2010-07-21 東京エレクトロン株式会社 プラズマ処理方法およびプラズマ処理装置
DE102006056624B4 (de) * 2006-11-30 2012-03-29 Globalfoundries Inc. Verfahren zur Herstellung einer selbstjustierten CuSiN-Deckschicht in einem Mikrostrukturbauelement
US7718548B2 (en) * 2006-12-06 2010-05-18 Applied Materials, Inc. Selective copper-silicon-nitride layer formation for an improved dielectric film/copper line interface

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Publication number Publication date
JP2008192739A (ja) 2008-08-21
TW200842977A (en) 2008-11-01
US20080184543A1 (en) 2008-08-07

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