JP4250616B2 - 半導体集積回路装置及びその製造方法 - Google Patents
半導体集積回路装置及びその製造方法 Download PDFInfo
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- JP4250616B2 JP4250616B2 JP2005141573A JP2005141573A JP4250616B2 JP 4250616 B2 JP4250616 B2 JP 4250616B2 JP 2005141573 A JP2005141573 A JP 2005141573A JP 2005141573 A JP2005141573 A JP 2005141573A JP 4250616 B2 JP4250616 B2 JP 4250616B2
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- Prior art keywords
- film
- insulator
- floating gate
- sti
- integrated circuit
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- 239000004065 semiconductor Substances 0.000 title claims description 30
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 239000012212 insulator Substances 0.000 claims description 18
- 125000006850 spacer group Chemical group 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 9
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 25
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 23
- 229920005591 polysilicon Polymers 0.000 description 23
- 230000015654 memory Effects 0.000 description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 230000000694 effects Effects 0.000 description 14
- 238000005530 etching Methods 0.000 description 8
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 238000010306 acid treatment Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Description
Cp=Cono/(Cono+Cox)
と表され、Conoに強く依存する。Conoは、制御ゲートと浮遊ゲートとの間の容量である。
Claims (3)
- 半導体基板上に、ゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上に、浮遊ゲートとなる第1の膜を形成する工程と、
前記浮遊ゲートとなる第1の膜上に、前記基板にトレンチを形成する際のマスク材を形成する工程と、
前記マスク材をマスクに用いて、前記第1の膜を貫通して前記基板にトレンチを形成する工程と、
前記トレンチに、絶縁物を埋め込む工程と、
前記マスク材を除去するとともに、前記絶縁物を少なくとも平面方向に後退させる工程と、
前記絶縁物の側壁上に、スペーサを形成する工程と、
前記スペーサ間に、浮遊ゲートとなる第2の膜を形成する工程と、
前記スペーサを除去し、前記絶縁物の側壁が露出する空間を形成する工程と、
前記絶縁物を、前記空間から後退させる工程と
を具備し、前記絶縁物は深さ方向にも後退され、前記空間は、前記絶縁物と前記第2の膜との間から前記絶縁物と前記第1の膜との間にかけて形成されることを特徴とする半導体集積回路装置の製造方法。 - 前記第2の膜は、前記スペーサの上面が露出するように、前記スペーサ間に形成されることを特徴とする請求項1に記載の半導体集積回路装置の製造方法。
- 絶縁物によって分離されたアクティブエリアと、
前記アクティブエリア上に、これと絶縁されて形成され、側面を前記絶縁物に挟まれた
浮遊ゲートと、を備え、
前記浮遊ゲートは、
第1の膜と、第2の膜との積層構造であり、
前記浮遊ゲートのワード線に沿った断面形状の少なくとも一部が、逆台形であり、前記絶縁物の表面が、セル部において平坦であり、周辺回路部において凸型形状であることを特徴とする半導体集積回路装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005141573A JP4250616B2 (ja) | 2005-05-13 | 2005-05-13 | 半導体集積回路装置及びその製造方法 |
US11/338,707 US7494869B2 (en) | 2005-05-13 | 2006-01-25 | Semiconductor integrated circuit device and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005141573A JP4250616B2 (ja) | 2005-05-13 | 2005-05-13 | 半導体集積回路装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006319202A JP2006319202A (ja) | 2006-11-24 |
JP4250616B2 true JP4250616B2 (ja) | 2009-04-08 |
Family
ID=37419684
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005141573A Expired - Fee Related JP4250616B2 (ja) | 2005-05-13 | 2005-05-13 | 半導体集積回路装置及びその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7494869B2 (ja) |
JP (1) | JP4250616B2 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8642441B1 (en) | 2006-12-15 | 2014-02-04 | Spansion Llc | Self-aligned STI with single poly for manufacturing a flash memory device |
US7948021B2 (en) * | 2007-04-27 | 2011-05-24 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method of fabricating the same |
TW200913169A (en) * | 2007-09-13 | 2009-03-16 | Powerchip Semiconductor Corp | Method of fabricating flash memory |
JP2009194244A (ja) | 2008-02-15 | 2009-08-27 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
JP4703669B2 (ja) | 2008-02-18 | 2011-06-15 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
JP5522915B2 (ja) * | 2008-09-30 | 2014-06-18 | ローム株式会社 | 半導体記憶装置およびその製造方法 |
US8551858B2 (en) | 2010-02-03 | 2013-10-08 | Spansion Llc | Self-aligned SI rich nitride charge trap layer isolation for charge trap flash memory |
CN104658978A (zh) * | 2013-11-19 | 2015-05-27 | 中芯国际集成电路制造(上海)有限公司 | 快闪存储器和快闪存储器的制作方法 |
JP5781190B2 (ja) * | 2014-04-07 | 2015-09-16 | ローム株式会社 | 半導体記憶装置 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4237344B2 (ja) * | 1998-09-29 | 2009-03-11 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP4131896B2 (ja) | 2000-03-31 | 2008-08-13 | 株式会社東芝 | 不揮発性半導体記憶装置の製造方法 |
JP4068286B2 (ja) * | 2000-06-30 | 2008-03-26 | 株式会社東芝 | 半導体装置の製造方法 |
KR100426483B1 (ko) * | 2001-12-22 | 2004-04-14 | 주식회사 하이닉스반도체 | 플래쉬 메모리 셀의 제조 방법 |
JP2004022819A (ja) * | 2002-06-17 | 2004-01-22 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2004235313A (ja) * | 2003-01-29 | 2004-08-19 | Renesas Technology Corp | 半導体装置 |
US6838342B1 (en) * | 2003-10-03 | 2005-01-04 | Promos Technologies, Inc. | Nonvolatile memory fabrication methods comprising lateral recessing of dielectric sidewalls at substrate isolation regions |
KR100554516B1 (ko) * | 2004-06-29 | 2006-03-03 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
-
2005
- 2005-05-13 JP JP2005141573A patent/JP4250616B2/ja not_active Expired - Fee Related
-
2006
- 2006-01-25 US US11/338,707 patent/US7494869B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20060258092A1 (en) | 2006-11-16 |
JP2006319202A (ja) | 2006-11-24 |
US7494869B2 (en) | 2009-02-24 |
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