JP4179736B2 - 半導体素子実装済部品の製造方法及び半導体素子実装済完成品の製造方法 - Google Patents

半導体素子実装済部品の製造方法及び半導体素子実装済完成品の製造方法 Download PDF

Info

Publication number
JP4179736B2
JP4179736B2 JP2000212613A JP2000212613A JP4179736B2 JP 4179736 B2 JP4179736 B2 JP 4179736B2 JP 2000212613 A JP2000212613 A JP 2000212613A JP 2000212613 A JP2000212613 A JP 2000212613A JP 4179736 B2 JP4179736 B2 JP 4179736B2
Authority
JP
Japan
Prior art keywords
semiconductor element
thermoplastic resin
semiconductor
manufacturing
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000212613A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001093926A (ja
JP2001093926A5 (https=
Inventor
法人 塚原
尚士 秋口
秀規 宮川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2000212613A priority Critical patent/JP4179736B2/ja
Publication of JP2001093926A publication Critical patent/JP2001093926A/ja
Publication of JP2001093926A5 publication Critical patent/JP2001093926A5/ja
Application granted granted Critical
Publication of JP4179736B2 publication Critical patent/JP4179736B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/241—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for passive devices or passive elements
    • H10W44/248—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for passive devices or passive elements for antennas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Credit Cards Or The Like (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2000212613A 1999-07-16 2000-07-13 半導体素子実装済部品の製造方法及び半導体素子実装済完成品の製造方法 Expired - Fee Related JP4179736B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000212613A JP4179736B2 (ja) 1999-07-16 2000-07-13 半導体素子実装済部品の製造方法及び半導体素子実装済完成品の製造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP11-202847 1999-07-16
JP20284799 1999-07-16
JP2000212613A JP4179736B2 (ja) 1999-07-16 2000-07-13 半導体素子実装済部品の製造方法及び半導体素子実装済完成品の製造方法

Publications (3)

Publication Number Publication Date
JP2001093926A JP2001093926A (ja) 2001-04-06
JP2001093926A5 JP2001093926A5 (https=) 2005-06-09
JP4179736B2 true JP4179736B2 (ja) 2008-11-12

Family

ID=26513604

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000212613A Expired - Fee Related JP4179736B2 (ja) 1999-07-16 2000-07-13 半導体素子実装済部品の製造方法及び半導体素子実装済完成品の製造方法

Country Status (1)

Country Link
JP (1) JP4179736B2 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4529319B2 (ja) * 2001-06-27 2010-08-25 日亜化学工業株式会社 半導体チップとその製造方法
JP5035580B2 (ja) * 2001-06-28 2012-09-26 ナガセケムテックス株式会社 弾性表面波デバイスおよびその製法
JP2003092311A (ja) * 2001-09-17 2003-03-28 Nagase & Co Ltd 突起電極付ｉｃチップの実装方法
JP2003092310A (ja) * 2001-09-17 2003-03-28 Nagase & Co Ltd 封止樹脂付突起電極付ｉｃチップとその製造方法
US7176055B2 (en) 2001-11-02 2007-02-13 Matsushita Electric Industrial Co., Ltd. Method and apparatus for manufacturing electronic component-mounted component, and electronic component-mounted component
DE10250541B9 (de) * 2002-10-29 2004-09-16 Infineon Technologies Ag Elektronisches Bauteil mit Unterfüllstoffen aus Thermoplasten und Verfahren zu dessen Herstellung
JP2004152982A (ja) 2002-10-30 2004-05-27 Matsushita Electric Ind Co Ltd 電子部品実装済部品の製造方法、及び該電子部品実装済部品を備えた電子部品実装済完成品の製造方法、並びに電子部品実装済完成品
EP3547380B1 (en) * 2010-02-09 2023-12-20 Nichia Corporation Light emitting device
WO2011145794A1 (ko) 2010-05-18 2011-11-24 서울반도체 주식회사 파장변환층을 갖는 발광 다이오드 칩과 그 제조 방법, 및 그것을 포함하는 패키지 및 그 제조 방법
CN103003966B (zh) * 2010-05-18 2016-08-10 首尔半导体株式会社 具有波长变换层的发光二级管芯片及其制造方法，以及包括其的封装件及其制造方法

Also Published As

Publication number Publication date
JP2001093926A (ja) 2001-04-06

Similar Documents

Publication Publication Date Title
EP1204136B1 (en) Method of fabricating a packaged semiconductor device
US6664645B2 (en) Method of mounting a semiconductor chip, circuit board for flip-chip connection and method of manufacturing the same, electromagnetic wave readable data carrier and method of manufacturing the same, and electronic component module for an electromagnetic wave readable data carrier
JP3889856B2 (ja) 突起電極付きプリント配線基板の製造方法
US6544428B1 (en) Method for producing a multi-layer circuit board using anisotropic electro-conductive adhesive layer
US5918113A (en) Process for producing a semiconductor device using anisotropic conductive adhesive
US7276436B2 (en) Manufacturing method for electronic component module and electromagnetically readable data carrier
JPH10270624A (ja) チップサイズパッケージ及びその製造方法
JP4179736B2 (ja) 半導体素子実装済部品の製造方法及び半導体素子実装済完成品の製造方法
JP2005166012A (ja) Ｒｆｉｄタグの製造方法
JP3916405B2 (ja) 電子部品実装済部品の製造方法、電子部品実装済完成品の製造方法、及び半導体部品実装済完成品
JP2003142797A (ja) 電子部品実装済完成品の製造方法及び電子部品実装済完成品
US20050275088A1 (en) Circuit module and method for manufacturing the same
JP3891743B2 (ja) 半導体部品実装済部品の製造方法、半導体部品実装済完成品の製造方法、及び半導体部品実装済完成品
JP4170491B2 (ja) 接触型非接触型共用ｉｃカードの製造方法
JPH10157353A (ja) 無線カードおよびその製造方法
JP4209574B2 (ja) 半導体部品実装済部品の製造方法
JP2004153000A (ja) プリント基板の製造方法およびそれにより製造されるプリント基板
JP4030220B2 (ja) 半導体チップの実装構造
JP3979797B2 (ja) 電子部品実装済部品の製造方法、電子部品実装済完成品の製造方法、及び半導体部品実装済完成品
JP3881195B2 (ja) 半導体部品実装済部品の製造方法、半導体部品実装済部品、半導体部品実装済完成品の製造方法、及び半導体部品実装済完成品
JP2004062634A (ja) 非接触通信媒体の接合方法および非接触通信媒体
JP2796625B2 (ja) 電子桟器

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040830

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040830

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050420

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20061010

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061208

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080430

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080625

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080729

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080826

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110905

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110905

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120905

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130905

Year of fee payment: 5

LAPS Cancellation because of no payment of annual fees