JP4173970B2 - メモリシステム及びメモリモジュール - Google Patents

メモリシステム及びメモリモジュール Download PDF

Info

Publication number
JP4173970B2
JP4173970B2 JP2002075369A JP2002075369A JP4173970B2 JP 4173970 B2 JP4173970 B2 JP 4173970B2 JP 2002075369 A JP2002075369 A JP 2002075369A JP 2002075369 A JP2002075369 A JP 2002075369A JP 4173970 B2 JP4173970 B2 JP 4173970B2
Authority
JP
Japan
Prior art keywords
memory
wiring
signal
address
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002075369A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003271538A (ja
JP2003271538A5 (enExample
Inventor
英樹 大坂
豊彦 小松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2002075369A priority Critical patent/JP4173970B2/ja
Priority to PCT/JP2003/002428 priority patent/WO2003079202A1/ja
Publication of JP2003271538A publication Critical patent/JP2003271538A/ja
Publication of JP2003271538A5 publication Critical patent/JP2003271538A5/ja
Application granted granted Critical
Publication of JP4173970B2 publication Critical patent/JP4173970B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
JP2002075369A 2002-03-19 2002-03-19 メモリシステム及びメモリモジュール Expired - Fee Related JP4173970B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2002075369A JP4173970B2 (ja) 2002-03-19 2002-03-19 メモリシステム及びメモリモジュール
PCT/JP2003/002428 WO2003079202A1 (en) 2002-03-19 2003-03-03 Memory system using directional coupler for address

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002075369A JP4173970B2 (ja) 2002-03-19 2002-03-19 メモリシステム及びメモリモジュール

Publications (3)

Publication Number Publication Date
JP2003271538A JP2003271538A (ja) 2003-09-26
JP2003271538A5 JP2003271538A5 (enExample) 2005-09-08
JP4173970B2 true JP4173970B2 (ja) 2008-10-29

Family

ID=28035364

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002075369A Expired - Fee Related JP4173970B2 (ja) 2002-03-19 2002-03-19 メモリシステム及びメモリモジュール

Country Status (2)

Country Link
JP (1) JP4173970B2 (enExample)
WO (1) WO2003079202A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6930904B2 (en) 2002-11-22 2005-08-16 Sun Microsystems, Inc. Circuit topology for high-speed memory access
JP4741226B2 (ja) * 2003-12-25 2011-08-03 株式会社日立製作所 半導体メモリモジュール、およびメモリシステム
JP2006011926A (ja) * 2004-06-28 2006-01-12 Ricoh Co Ltd シリアルデータ転送システム、シリアルデータ転送装置、シリアルデータ転送方法及び画像形成装置
KR100688515B1 (ko) 2005-01-06 2007-03-02 삼성전자주식회사 메모리 모듈 및 시스템
KR100703728B1 (ko) 2005-01-11 2007-04-05 삼성전자주식회사 전자 기기
US7577760B2 (en) 2005-05-10 2009-08-18 Samsung Electronics Co., Ltd. Memory systems, modules, controllers and methods using dedicated data and control busses
JP4382842B2 (ja) 2007-09-18 2009-12-16 富士通株式会社 メモリ制御回路，遅延時間制御装置，遅延時間制御方法および遅延時間制御プログラム
US8503211B2 (en) 2009-05-22 2013-08-06 Mosaid Technologies Incorporated Configurable module and memory subsystem
CN103035279B (zh) * 2011-09-30 2015-07-08 无锡江南计算技术研究所 消除ddr3负载差异影响的传输线结构及形成方法、内存结构

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0784863A (ja) * 1993-09-20 1995-03-31 Hitachi Ltd 情報処理装置およびそれに適した半導体記憶装置
JPH07271712A (ja) * 1994-03-29 1995-10-20 Japan Radio Co Ltd メモリアクセス方法及びこれを用いたフレームメモリアクセス装置
JPH08335871A (ja) * 1995-06-07 1996-12-17 Matsushita Electron Corp 半導体装置
JP3546613B2 (ja) * 1996-10-25 2004-07-28 株式会社日立製作所 回路基板
JPH10242412A (ja) * 1997-02-24 1998-09-11 Fujitsu Ltd 配線基板及びメモリ実装配線基板
JP3820843B2 (ja) * 1999-05-12 2006-09-13 株式会社日立製作所 方向性結合式メモリモジュール
JP3880286B2 (ja) * 1999-05-12 2007-02-14 エルピーダメモリ株式会社 方向性結合式メモリシステム
JP3757757B2 (ja) * 2000-05-18 2006-03-22 株式会社日立製作所 リード優先メモリシステム
KR100351053B1 (ko) * 2000-05-19 2002-09-05 삼성전자 주식회사 종단저항을 내장하는 메모리 모듈 및 이를 포함하여 다중채널구조를 갖는 메모리 모듈
KR100335501B1 (ko) * 2000-06-09 2002-05-08 윤종용 향상된 데이터 버스 성능을 갖는 메모리 모듈
KR100335504B1 (ko) * 2000-06-30 2002-05-09 윤종용 제어 및 어드레스 버스를 공유하는 2채널 메모리 시스템및 이에 채용되는 메모리 모듈
TW530248B (en) * 2000-08-09 2003-05-01 Hitachi Ltd Data transmission system of directional coupling type using forward wave and reflective wave

Also Published As

Publication number Publication date
JP2003271538A (ja) 2003-09-26
WO2003079202A1 (en) 2003-09-25

Similar Documents

Publication Publication Date Title
US6742098B1 (en) Dual-port buffer-to-memory interface
US20240144992A1 (en) High capacity memory system using standard controller component
KR100444365B1 (ko) 진행파 및 반사파를 사용한 방향성 결합형 데이터 전달시스템
US7024518B2 (en) Dual-port buffer-to-memory interface
US6937494B2 (en) Memory module, memory chip, and memory system
KR100348726B1 (ko) 방향성 결합식 메모리 모듈
JP3821678B2 (ja) メモリ装置
US7095661B2 (en) Semiconductor memory module, memory system, circuit, semiconductor device, and DIMM
US6877079B2 (en) Memory system having point-to-point bus configuration
US7079446B2 (en) DRAM interface circuits having enhanced skew, slew rate and impedance control
US7061784B2 (en) Semiconductor memory module
JP3757757B2 (ja) リード優先メモリシステム
KR100442870B1 (ko) 스터브 버스 구조를 갖는 메모리 시스템
WO1999046687A1 (en) Data transmitter
JPWO1999046687A1 (ja) データ伝送装置
JP2001027918A (ja) 方向性結合式メモリシステム
JP2001256175A (ja) メモリシステム
JP2001256772A (ja) メモリモジュール
KR20040091580A (ko) 메모리 모듈 및 메모리 시스템
JP2003050738A (ja) キャリブレーション方法及びメモリシステム
US10141314B2 (en) Memories and methods to provide configuration information to controllers
CN102859598A (zh) 平衡式裸片上终结
JP4173970B2 (ja) メモリシステム及びメモリモジュール
US6276844B1 (en) Clustered, buffered simms and assemblies thereof
US7323789B2 (en) Multiple chip package and IC chips

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050314

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050314

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20050314

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080201

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080212

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080411

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080513

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080711

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080805

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080815

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110822

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110822

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110822

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120822

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120822

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130822

Year of fee payment: 5

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees