JP4156781B2 - 半導体メモリ集積回路 - Google Patents

半導体メモリ集積回路 Download PDF

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Publication number
JP4156781B2
JP4156781B2 JP2000159480A JP2000159480A JP4156781B2 JP 4156781 B2 JP4156781 B2 JP 4156781B2 JP 2000159480 A JP2000159480 A JP 2000159480A JP 2000159480 A JP2000159480 A JP 2000159480A JP 4156781 B2 JP4156781 B2 JP 4156781B2
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JP
Japan
Prior art keywords
pulse
address
clock
circuit
stage decoder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000159480A
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English (en)
Japanese (ja)
Other versions
JP2001344978A (ja
JP2001344978A5 (enExample
Inventor
輝男 高際
正美 増田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2000159480A priority Critical patent/JP4156781B2/ja
Priority to US09/866,065 priority patent/US6501702B2/en
Priority to KR10-2001-0029680A priority patent/KR100439924B1/ko
Publication of JP2001344978A publication Critical patent/JP2001344978A/ja
Publication of JP2001344978A5 publication Critical patent/JP2001344978A5/ja
Application granted granted Critical
Publication of JP4156781B2 publication Critical patent/JP4156781B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
    • G11C29/832—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption with disconnection of faulty elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/781—Masking faults in memories by using spares or by reconfiguring using programmable devices combined in a redundant decoder
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Pulse Circuits (AREA)
JP2000159480A 2000-05-30 2000-05-30 半導体メモリ集積回路 Expired - Fee Related JP4156781B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2000159480A JP4156781B2 (ja) 2000-05-30 2000-05-30 半導体メモリ集積回路
US09/866,065 US6501702B2 (en) 2000-05-30 2001-05-25 Semiconductor memory integrated circuit
KR10-2001-0029680A KR100439924B1 (ko) 2000-05-30 2001-05-29 반도체 메모리 집적 회로

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000159480A JP4156781B2 (ja) 2000-05-30 2000-05-30 半導体メモリ集積回路

Publications (3)

Publication Number Publication Date
JP2001344978A JP2001344978A (ja) 2001-12-14
JP2001344978A5 JP2001344978A5 (enExample) 2007-08-16
JP4156781B2 true JP4156781B2 (ja) 2008-09-24

Family

ID=18663793

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000159480A Expired - Fee Related JP4156781B2 (ja) 2000-05-30 2000-05-30 半導体メモリ集積回路

Country Status (3)

Country Link
US (1) US6501702B2 (enExample)
JP (1) JP4156781B2 (enExample)
KR (1) KR100439924B1 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITRM20010298A1 (it) * 2001-05-31 2002-12-02 Micron Technology Inc Interfaccia di comando di utilizzatore con decodificatore programmabile.
KR100481179B1 (ko) * 2002-09-10 2005-04-07 삼성전자주식회사 퓨즈를 구비한 회로 및 이를 이용한 반도체 장치
JP2004152348A (ja) * 2002-10-29 2004-05-27 Renesas Technology Corp 信号生成回路
KR100615596B1 (ko) * 2004-12-22 2006-08-25 삼성전자주식회사 반도체 장치
US7263024B2 (en) * 2005-10-17 2007-08-28 Lattice Semiconductor Corporation Clock reset address decoder for block memory
JP5563183B2 (ja) 2007-02-15 2014-07-30 ピーエスフォー ルクスコ エスエイアールエル 半導体メモリ集積回路
US8861301B2 (en) 2012-06-08 2014-10-14 Freescale Semiconductor, Inc. Clocked memory with latching predecoder circuitry
US8743651B2 (en) 2012-06-08 2014-06-03 Freescale Semiconductor, Inc. Clocked memory with word line activation during a first portion of the clock cycle
US20150279451A1 (en) * 2014-03-27 2015-10-01 Qualcomm Incorporated Edge-triggered pulse latch
KR102816578B1 (ko) 2020-08-14 2025-06-04 삼성전자주식회사 듀티 조절 회로, 이를 포함하는 지연 동기 루프 회로 및 반도체 메모리 장치

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100224681B1 (ko) * 1997-01-10 1999-10-15 윤종용 반도체 메모리 장치의 로우 어드레스 제어 회로
KR100257867B1 (ko) * 1997-11-15 2000-06-01 윤종용 2차 캐시를 구비한 시스템 장치 및 동기형 메모리 장치
JP4117944B2 (ja) 1998-07-31 2008-07-16 富士通株式会社 半導体記憶装置
JP4159657B2 (ja) 1998-07-13 2008-10-01 株式会社ルネサステクノロジ 同期型半導体記憶装置
JP2000132968A (ja) 1998-10-28 2000-05-12 Hitachi Ltd 半導体集積回路装置
KR100313515B1 (ko) * 1999-07-26 2001-11-15 김영환 반도체 메모리의 칼럼 구제 회로

Also Published As

Publication number Publication date
US6501702B2 (en) 2002-12-31
JP2001344978A (ja) 2001-12-14
KR100439924B1 (ko) 2004-07-12
KR20010109145A (ko) 2001-12-08
US20010048632A1 (en) 2001-12-06

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