JP4145984B2 - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

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Publication number
JP4145984B2
JP4145984B2 JP06731498A JP6731498A JP4145984B2 JP 4145984 B2 JP4145984 B2 JP 4145984B2 JP 06731498 A JP06731498 A JP 06731498A JP 6731498 A JP6731498 A JP 6731498A JP 4145984 B2 JP4145984 B2 JP 4145984B2
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JP
Japan
Prior art keywords
data
output
storage means
data storage
clock signal
Prior art date
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Expired - Fee Related
Application number
JP06731498A
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English (en)
Japanese (ja)
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JPH11265581A5 (enExample
JPH11265581A (ja
Inventor
伸朗 大塚
修 平林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP06731498A priority Critical patent/JP4145984B2/ja
Priority to US09/268,688 priority patent/US6154393A/en
Publication of JPH11265581A publication Critical patent/JPH11265581A/ja
Publication of JPH11265581A5 publication Critical patent/JPH11265581A5/ja
Application granted granted Critical
Publication of JP4145984B2 publication Critical patent/JP4145984B2/ja
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Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

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  • Static Random-Access Memory (AREA)
  • Dram (AREA)
JP06731498A 1998-03-17 1998-03-17 半導体記憶装置 Expired - Fee Related JP4145984B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP06731498A JP4145984B2 (ja) 1998-03-17 1998-03-17 半導体記憶装置
US09/268,688 US6154393A (en) 1998-03-17 1999-03-16 Semiconductor memory device of double-data rate mode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP06731498A JP4145984B2 (ja) 1998-03-17 1998-03-17 半導体記憶装置

Publications (3)

Publication Number Publication Date
JPH11265581A JPH11265581A (ja) 1999-09-28
JPH11265581A5 JPH11265581A5 (enExample) 2005-09-08
JP4145984B2 true JP4145984B2 (ja) 2008-09-03

Family

ID=13341449

Family Applications (1)

Application Number Title Priority Date Filing Date
JP06731498A Expired - Fee Related JP4145984B2 (ja) 1998-03-17 1998-03-17 半導体記憶装置

Country Status (2)

Country Link
US (1) US6154393A (enExample)
JP (1) JP4145984B2 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4023953B2 (ja) * 1999-06-22 2007-12-19 株式会社ルネサステクノロジ 不揮発性半導体記憶装置
KR100341576B1 (ko) 1999-06-28 2002-06-22 박종섭 반도체메모리장치의 파이프데이터 입력 제어 방법 및 장치
KR100507866B1 (ko) 1999-06-28 2005-08-18 주식회사 하이닉스반도체 디디알 에스디램의 파이프래치 출력단 프리차지 구조
JP2001167580A (ja) * 1999-12-07 2001-06-22 Toshiba Corp 半導体記憶装置
US6504767B1 (en) * 2000-08-30 2003-01-07 Micron Technology, Inc. Double data rate memory device having output data path with different number of latches
JP2002304886A (ja) * 2001-04-06 2002-10-18 Nec Corp 半導体記憶装置
KR100543906B1 (ko) * 2001-12-29 2006-01-23 주식회사 하이닉스반도체 어드레스 핀의 수를 줄인 동기식 반도체 메모리 소자
JP2003272382A (ja) 2002-03-20 2003-09-26 Mitsubishi Electric Corp 半導体記憶装置
JP4305871B2 (ja) * 2003-09-08 2009-07-29 富士通株式会社 レジスタファイル及びその記憶素子
US6914849B2 (en) * 2003-10-16 2005-07-05 International Business Machines Corporation Method and apparatus for reducing power consumption in a memory array with dynamic word line driver/decoders
KR100604948B1 (ko) 2005-08-17 2006-07-31 삼성전자주식회사 동기식 메모리장치의 웨이브 파이프라인 구조의 출력회로
KR100660639B1 (ko) 2005-12-02 2006-12-21 삼성전자주식회사 더블 데이터 레이트 반도체 장치의 데이터 출력 회로 및이를 구비하는 반도체 장치
KR100772842B1 (ko) * 2006-08-22 2007-11-02 삼성전자주식회사 데이터 패쓰 조절기능을 갖는 반도체 메모리 장치
US7707378B2 (en) * 2006-11-30 2010-04-27 Intel Corporation DDR flash implementation with hybrid row buffers and direct access interface to legacy flash functions
US7751275B2 (en) * 2008-01-25 2010-07-06 Broadcom Corporation Double data rate-single data rate input block and method for using same
US10658029B2 (en) * 2018-09-21 2020-05-19 Qualcomm Incorporated High bandwidth double-pumped memory

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5530955A (en) * 1991-04-01 1996-06-25 Matsushita Electric Industrial Co., Ltd. Page memory device capable of short cycle access of different pages by a plurality of data processors
JP3176228B2 (ja) * 1994-08-23 2001-06-11 シャープ株式会社 半導体記憶装置
JP2888201B2 (ja) * 1996-07-30 1999-05-10 日本電気株式会社 半導体メモリ集積回路
JP3191720B2 (ja) * 1997-04-11 2001-07-23 日本電気株式会社 マルチプレクサ

Also Published As

Publication number Publication date
JPH11265581A (ja) 1999-09-28
US6154393A (en) 2000-11-28

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