JP4108637B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4108637B2 JP4108637B2 JP2004110875A JP2004110875A JP4108637B2 JP 4108637 B2 JP4108637 B2 JP 4108637B2 JP 2004110875 A JP2004110875 A JP 2004110875A JP 2004110875 A JP2004110875 A JP 2004110875A JP 4108637 B2 JP4108637 B2 JP 4108637B2
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- JP
- Japan
- Prior art keywords
- package
- semiconductor chip
- lead
- semiconductor device
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
Memory)向けSOJ(Small Outline J-Leaded)について記載されている。
Claims (4)
- 平面形状が、一対の長辺と一対の短辺とを有する長方形から成り、複数の電極が中央部に形成された表面と、前記表面と反対側の裏面とを有する半導体チップと、
平面形状が、前記半導体チップの長辺と並ぶように形成された一対の長辺と、前記半導体チップの短辺と並ぶように形成された一対の短辺とを有する長方形から成り、前記半導体チップの表面と同一方向に位置するパッケージ表面と、前記パッケージ表面と反対側のパッケージ裏面とを有し、前記半導体チップを封止するパッケージと、
前記パッケージに封止され、前記半導体チップ側に位置する一端部と、前記一端部と反対側に位置し、前記パッケージの長辺から突出する他端部とを有する複数のリードと、
前記パッケージに封止され、前記半導体チップの短辺と前記パッケージの短辺の間に位置し、前記複数のリードのうちの前記パッケージの短辺に最も近いリードと一体に形成され、前記パッケージ表面から前記パッケージ裏面に向かって屈曲する分岐部と、
前記パッケージに封止され、前記複数のリードの一端部と前記半導体チップの複数の電極とをそれぞれ電気的に接続する複数のワイヤと、
を含み、
前記半導体チップの短辺と前記パッケージの短辺の間隔は、前記半導体チップの長辺と前記パッケージの長辺の間隔よりも広いことを特徴とする半導体装置。 - 前記パッケージの厚さ方向ほぼ真ん中に位置する分岐部を有するリードを前記長方形パッケージの両短辺側の前記半導体チップ及び前記リードが存在しない領域それぞれに設けたことを特徴とする請求項1に記載の半導体装置。
- 前記分岐部を有するリードは、それぞれ同一形状であることを特徴とする請求項2に記載の半導体装置。
- 前記複数のリードそれぞれの一部は前記半導体チップの表面に絶縁テープを介して固定されることを特徴とする請求項3に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004110875A JP4108637B2 (ja) | 2004-04-05 | 2004-04-05 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004110875A JP4108637B2 (ja) | 2004-04-05 | 2004-04-05 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26960495A Division JP3872530B2 (ja) | 1995-10-18 | 1995-10-18 | 半導体装置およびその製造に用いるリードフレーム |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007177896A Division JP4837628B2 (ja) | 2007-07-06 | 2007-07-06 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004200728A JP2004200728A (ja) | 2004-07-15 |
JP4108637B2 true JP4108637B2 (ja) | 2008-06-25 |
Family
ID=32768396
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004110875A Expired - Fee Related JP4108637B2 (ja) | 2004-04-05 | 2004-04-05 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4108637B2 (ja) |
-
2004
- 2004-04-05 JP JP2004110875A patent/JP4108637B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2004200728A (ja) | 2004-07-15 |
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