JP4099329B2 - 部品混載実装方法 - Google Patents

部品混載実装方法 Download PDF

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Publication number
JP4099329B2
JP4099329B2 JP2001384502A JP2001384502A JP4099329B2 JP 4099329 B2 JP4099329 B2 JP 4099329B2 JP 2001384502 A JP2001384502 A JP 2001384502A JP 2001384502 A JP2001384502 A JP 2001384502A JP 4099329 B2 JP4099329 B2 JP 4099329B2
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JP
Japan
Prior art keywords
component
chip
bare
circuit board
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001384502A
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English (en)
Japanese (ja)
Other versions
JP2003188521A (ja
JP2003188521A5 (enExample
Inventor
健 ▲高▼野
邦男 桜井
実 山本
裕一 本川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2001384502A priority Critical patent/JP4099329B2/ja
Publication of JP2003188521A publication Critical patent/JP2003188521A/ja
Publication of JP2003188521A5 publication Critical patent/JP2003188521A5/ja
Application granted granted Critical
Publication of JP4099329B2 publication Critical patent/JP4099329B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
JP2001384502A 2001-12-18 2001-12-18 部品混載実装方法 Expired - Fee Related JP4099329B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001384502A JP4099329B2 (ja) 2001-12-18 2001-12-18 部品混載実装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001384502A JP4099329B2 (ja) 2001-12-18 2001-12-18 部品混載実装方法

Publications (3)

Publication Number Publication Date
JP2003188521A JP2003188521A (ja) 2003-07-04
JP2003188521A5 JP2003188521A5 (enExample) 2005-07-21
JP4099329B2 true JP4099329B2 (ja) 2008-06-11

Family

ID=27594218

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001384502A Expired - Fee Related JP4099329B2 (ja) 2001-12-18 2001-12-18 部品混載実装方法

Country Status (1)

Country Link
JP (1) JP4099329B2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008021843A (ja) * 2006-07-13 2008-01-31 Seiko Epson Corp 配線基板の製造方法、多層配線基板の製造方法
CN107799507B (zh) * 2016-08-29 2020-02-04 鸿富锦精密工业（深圳）有限公司 背光系统及其制造方法
US10651233B2 (en) * 2018-08-21 2020-05-12 Northrop Grumman Systems Corporation Method for forming superconducting structures
CN112018143A (zh) * 2019-05-28 2020-12-01 云谷（固安）科技有限公司 微发光二极管显示基板、显示面板及其制作方法、显示装置
CN118919456B (zh) * 2024-10-10 2024-12-06 常州科瑞尔科技有限公司 Dsc模块倒装贴合系统及制作方法

Also Published As

Publication number Publication date
JP2003188521A (ja) 2003-07-04

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