JP4021104B2 - バンプ電極を有する半導体装置 - Google Patents

バンプ電極を有する半導体装置 Download PDF

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Publication number
JP4021104B2
JP4021104B2 JP22284799A JP22284799A JP4021104B2 JP 4021104 B2 JP4021104 B2 JP 4021104B2 JP 22284799 A JP22284799 A JP 22284799A JP 22284799 A JP22284799 A JP 22284799A JP 4021104 B2 JP4021104 B2 JP 4021104B2
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JP
Japan
Prior art keywords
semiconductor device
bump electrode
protective film
bump
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP22284799A
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English (en)
Japanese (ja)
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JP2001053100A5 (https=
JP2001053100A (ja
Inventor
紀幸 木村
聖明 門井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP22284799A priority Critical patent/JP4021104B2/ja
Priority to US09/632,324 priority patent/US6563216B1/en
Publication of JP2001053100A publication Critical patent/JP2001053100A/ja
Publication of JP2001053100A5 publication Critical patent/JP2001053100A5/ja
Application granted granted Critical
Publication of JP4021104B2 publication Critical patent/JP4021104B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP22284799A 1999-08-05 1999-08-05 バンプ電極を有する半導体装置 Expired - Fee Related JP4021104B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP22284799A JP4021104B2 (ja) 1999-08-05 1999-08-05 バンプ電極を有する半導体装置
US09/632,324 US6563216B1 (en) 1999-08-05 2000-08-04 Semiconductor device having a bump electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22284799A JP4021104B2 (ja) 1999-08-05 1999-08-05 バンプ電極を有する半導体装置

Publications (3)

Publication Number Publication Date
JP2001053100A JP2001053100A (ja) 2001-02-23
JP2001053100A5 JP2001053100A5 (https=) 2005-11-24
JP4021104B2 true JP4021104B2 (ja) 2007-12-12

Family

ID=16788845

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22284799A Expired - Fee Related JP4021104B2 (ja) 1999-08-05 1999-08-05 バンプ電極を有する半導体装置

Country Status (2)

Country Link
US (1) US6563216B1 (https=)
JP (1) JP4021104B2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10008462B2 (en) 2015-09-18 2018-06-26 Samsung Electronics Co., Ltd. Semiconductor package

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7034402B1 (en) * 2000-06-28 2006-04-25 Intel Corporation Device with segmented ball limiting metallurgy
KR100448344B1 (ko) * 2002-10-22 2004-09-13 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지 제조 방법
US6864578B2 (en) * 2003-04-03 2005-03-08 International Business Machines Corporation Internally reinforced bond pads
US7180195B2 (en) * 2003-12-17 2007-02-20 Intel Corporation Method and apparatus for improved power routing
JP4010311B2 (ja) * 2004-09-06 2007-11-21 セイコーエプソン株式会社 半導体装置および半導体装置の製造方法
JP4606145B2 (ja) * 2004-12-09 2011-01-05 セイコーエプソン株式会社 半導体装置及びその製造方法
DE102005009358B4 (de) * 2005-03-01 2021-02-04 Snaptrack, Inc. Lötfähiger Kontakt und ein Verfahren zur Herstellung
US20060211167A1 (en) * 2005-03-18 2006-09-21 International Business Machines Corporation Methods and systems for improving microelectronic i/o current capabilities
US8319343B2 (en) * 2005-09-21 2012-11-27 Agere Systems Llc Routing under bond pad for the replacement of an interconnect layer
US7952206B2 (en) * 2005-09-27 2011-05-31 Agere Systems Inc. Solder bump structure for flip chip semiconductor devices and method of manufacture therefore
JP4708148B2 (ja) 2005-10-07 2011-06-22 ルネサスエレクトロニクス株式会社 半導体装置
JP4738971B2 (ja) * 2005-10-14 2011-08-03 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
US8552560B2 (en) * 2005-11-18 2013-10-08 Lsi Corporation Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing
US7888257B2 (en) * 2007-10-10 2011-02-15 Agere Systems Inc. Integrated circuit package including wire bonds
US8183698B2 (en) * 2007-10-31 2012-05-22 Agere Systems Inc. Bond pad support structure for semiconductor device
JP2008047943A (ja) * 2007-11-01 2008-02-28 Renesas Technology Corp 半導体装置
JP4585564B2 (ja) * 2007-12-13 2010-11-24 ルネサスエレクトロニクス株式会社 半導体装置
JP2008160168A (ja) * 2008-03-26 2008-07-10 Seiko Epson Corp 半導体装置及びその製造方法
JP2010267641A (ja) * 2009-05-12 2010-11-25 Panasonic Corp 半導体装置
JP5259674B2 (ja) * 2010-10-18 2013-08-07 ルネサスエレクトロニクス株式会社 半導体装置
KR102658923B1 (ko) 2016-09-12 2024-04-18 삼성전자주식회사 반도체 장치 및 반도체 패키지

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5220199A (en) * 1988-09-13 1993-06-15 Hitachi, Ltd. Semiconductor integrated circuit device in which a semiconductor chip is mounted with solder bumps for mounting to a wiring substrate
JPH04212426A (ja) * 1990-06-21 1992-08-04 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP3238011B2 (ja) * 1994-07-27 2001-12-10 株式会社東芝 半導体装置
US5686762A (en) * 1995-12-21 1997-11-11 Micron Technology, Inc. Semiconductor device with improved bond pads
US6022792A (en) * 1996-03-13 2000-02-08 Seiko Instruments, Inc. Semiconductor dicing and assembling method
KR100307385B1 (ko) * 1997-03-05 2001-12-15 구본준, 론 위라하디락사 액정표시장치의구조및그제조방법
KR100255591B1 (ko) * 1997-03-06 2000-05-01 구본준 박막 트랜지스터 어레이의 배선 연결 구조 및 그 제조 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10008462B2 (en) 2015-09-18 2018-06-26 Samsung Electronics Co., Ltd. Semiconductor package

Also Published As

Publication number Publication date
JP2001053100A (ja) 2001-02-23
US6563216B1 (en) 2003-05-13

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