JP3944764B2 - 集積回路及び集積回路の製造方法 - Google Patents

集積回路及び集積回路の製造方法 Download PDF

Info

Publication number
JP3944764B2
JP3944764B2 JP2001193836A JP2001193836A JP3944764B2 JP 3944764 B2 JP3944764 B2 JP 3944764B2 JP 2001193836 A JP2001193836 A JP 2001193836A JP 2001193836 A JP2001193836 A JP 2001193836A JP 3944764 B2 JP3944764 B2 JP 3944764B2
Authority
JP
Japan
Prior art keywords
conductive
integrated circuit
conductive runners
bonding pads
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001193836A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002093918A (ja
JP2002093918A5 (OSRAM
Inventor
ラヤン ヴィヴィアン
ハーバート シリング トーマス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agere Systems LLC
Original Assignee
Agere Systems LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems LLC filed Critical Agere Systems LLC
Publication of JP2002093918A publication Critical patent/JP2002093918A/ja
Publication of JP2002093918A5 publication Critical patent/JP2002093918A5/ja
Application granted granted Critical
Publication of JP3944764B2 publication Critical patent/JP3944764B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Automation & Control Theory (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
JP2001193836A 2000-06-27 2001-06-27 集積回路及び集積回路の製造方法 Expired - Fee Related JP3944764B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/604,519 US6833557B1 (en) 2000-06-27 2000-06-27 Integrated circuit and a method of manufacturing an integrated circuit
US09/604519 2000-06-27

Publications (3)

Publication Number Publication Date
JP2002093918A JP2002093918A (ja) 2002-03-29
JP2002093918A5 JP2002093918A5 (OSRAM) 2004-07-22
JP3944764B2 true JP3944764B2 (ja) 2007-07-18

Family

ID=24419923

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001193836A Expired - Fee Related JP3944764B2 (ja) 2000-06-27 2001-06-27 集積回路及び集積回路の製造方法

Country Status (5)

Country Link
US (1) US6833557B1 (OSRAM)
JP (1) JP3944764B2 (OSRAM)
KR (1) KR100823043B1 (OSRAM)
GB (1) GB2368973A (OSRAM)
TW (1) TW512511B (OSRAM)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7888672B2 (en) 2002-11-23 2011-02-15 Infineon Technologies Ag Device for detecting stress migration properties
DE10254756B4 (de) * 2002-11-23 2011-07-07 Infineon Technologies AG, 81669 Vorrichtung und Verfahren zur Erfassung von Stressmigrations-Eigenschaften
JP4949733B2 (ja) * 2006-05-11 2012-06-13 ルネサスエレクトロニクス株式会社 半導体装置
KR100764660B1 (ko) * 2006-11-01 2007-10-08 삼성전기주식회사 주파수 종속 특성을 가지는 다중 배선의 신호 천이시뮬레이션 방법
DE102014222203B3 (de) * 2014-10-30 2016-03-10 Infineon Technologies Ag Überprüfung von Randschäden
US20190250208A1 (en) * 2018-02-09 2019-08-15 Qualcomm Incorporated Apparatus and method for detecting damage to an integrated circuit

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6387736A (ja) * 1986-09-30 1988-04-19 Nec Corp 半導体装置
JP2842598B2 (ja) * 1988-12-01 1999-01-06 日本電気株式会社 半導体集積回路
JPH04199651A (ja) * 1990-11-29 1992-07-20 Fujitsu Ltd 半導体装置およびその製造方法
JPH06177221A (ja) * 1992-12-07 1994-06-24 Fujitsu Ltd 信頼性評価用半導体装置及び信頼性評価用の評価パターンを内蔵した製品ｌｓｉ、ウエハー
JP3269171B2 (ja) * 1993-04-08 2002-03-25 セイコーエプソン株式会社 半導体装置およびそれを有した時計
JPH07201855A (ja) * 1993-12-28 1995-08-04 Fujitsu Ltd 半導体装置
JP3270807B2 (ja) * 1995-06-29 2002-04-02 シャープ株式会社 テープキャリアパッケージ
KR100190927B1 (ko) * 1996-07-18 1999-06-01 윤종용 슬릿이 형성된 금속막을 구비한 반도체 칩 장치
JP3111938B2 (ja) * 1997-09-16 2000-11-27 日本電気株式会社 半導体装置

Also Published As

Publication number Publication date
GB2368973A (en) 2002-05-15
GB0115078D0 (en) 2001-08-15
TW512511B (en) 2002-12-01
US6833557B1 (en) 2004-12-21
KR20020001632A (ko) 2002-01-09
KR100823043B1 (ko) 2008-04-17
JP2002093918A (ja) 2002-03-29

Similar Documents

Publication Publication Date Title
JP5011459B2 (ja) 集積回路の試験方法
CN102034794B (zh) 测试结构及测试半导体衬底的方法
US6633083B2 (en) Barrier layer integrity test
CN107037350B (zh) 具有监控链及测试导线的集成电路测试结构
US8323990B2 (en) Reliability test structure for multilevel interconnect
KR100538725B1 (ko) 다층 배선을 갖는 반도체 집적 회로 장치
US6897475B2 (en) Test structure and related methods for evaluating stress-induced voiding
US20130038334A1 (en) Test structure, method and circuit for simultaneously testing time dependent dielectric breakdown and electromigration or stress migration
US7301239B2 (en) Wiring structure to minimize stress induced void formation
US8174010B2 (en) Unified test structure for stress migration tests
US8648592B2 (en) Semiconductor device components and methods
JP3944764B2 (ja) 集積回路及び集積回路の製造方法
US20070130551A1 (en) Non-destructive evaluation of microstructure and interface roughness of electrically conducting lines in semiconductor integrated circuits in deep sub-micron regime
US7098054B2 (en) Method and structure for determining thermal cycle reliability
US20070210306A1 (en) Test pattern for measuring contact short at first metal level
CN115377069B (zh) 应力迁移测试结构及应力迁移测试方法
KR100638042B1 (ko) 캘빈 저항 검사용 패턴 및 이 패턴이 형성된 반도체 장치
Sullivan Reliability considerations for copper metallizations in ULSI circuits
KR100450260B1 (ko) 박막의 파괴강도 시험방법
KR200258235Y1 (ko) 메탈배선의 테스트 소자의 구조
JP2000243800A (ja) 配線のエレクトロマイグレーション耐性評価方法
KR20030048896A (ko) 금속 배선의 침식 평가용 패턴 구조
TW200428584A (en) Pattern and method for testing interconnects

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050926

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20061016

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20070116

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20070119

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070209

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070305

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20070328

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070328

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110420

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110420

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120420

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130420

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130420

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140420

Year of fee payment: 7

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees