JP3871352B2 - 薄膜ｓｏｉ装置及びその製造方法 - Google Patents

薄膜ｓｏｉ装置及びその製造方法 Download PDF

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JP3871352B2
JP3871352B2 JP18816194A JP18816194A JP3871352B2 JP 3871352 B2 JP3871352 B2 JP 3871352B2 JP 18816194 A JP18816194 A JP 18816194A JP 18816194 A JP18816194 A JP 18816194A JP 3871352 B2 JP3871352 B2 JP 3871352B2
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silicon layer
drift region
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JPH0766428A (ja
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エル マーチャント スティーブン
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Koninklijke Philips NV
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Description

【０００１】
【産業上の利用分野】
本発明は、埋込絶縁層と、この埋込絶縁層上の珪素層と、この珪素層上の上側絶縁層とを具える薄膜ＳＯＩ装置であって、前記の珪素層が、横方向に延在するドリフト領域と、このドリフト領域の一端部でこの珪素層の上方にゲート電極を有するゲート領域と、前記の一端部とは反対側のドリフト領域の端部のドレイン領域と、前記のゲート領域から横方向で分離されたソース領域とを具えている当該薄膜ＳＯＩ装置に関するものである。
本発明は又、このようなＳＯＩ装置の製造方法にも関するものである。
【０００２】
【従来の技術】
このような装置は欧州特許第５４９０４２号明細書に記載されており既知であり、これを図１に示す。高電圧集積回路技術における主な問題は、構成素子や副回路区分の分離問題に対する満足な解決策を見出すことにある。この既知の装置では、ＳＯＩトランジスタのドリフト領域４が約２００〜３００ｎｍの厚さの薄肉珪素（シリコン）層として設けられている。この装置では、絶縁層が酸化物である。この珪素層上の上側酸化物層６はこの珪素層の下側の埋込酸化物層２と同じ厚さとするのが好ましい。この構造の利点は、ドリフト領域４をその上下両方から空乏化できる為、ドリフト領域４における移動電荷を２倍にしうるということである。これにより装置のオン抵抗を減少させる。この既知の装置では、基板３上の埋込酸化物層２の厚さが１〜３ミクロンの範囲にあり、上側酸化物層６の厚さも１〜３ミクロンの範囲にある。この既知の装置の場合、珪素層１のドリフト領域４が極めて薄肉である、すなわち０．１〜０．４ミクロンである個所で５００〜９００Ｖの範囲の高い降服電圧が得られる。
【０００３】
更に、この既知の装置では、ドリフト領域４にゲート領域の付近でドーピング濃度の少ない横方向の線形ドーピング領域が設けられている。又、ドリフト領域４上には電界プレート７が設けられている。ゲート領域１における珪素層上には、薄肉のゲート酸化物８があり、その上に多結晶ゲート電極１３が位置している。このゲート電極の横方向の延在範囲は薄肉の横方向の線形ドーピング領域を被覆するものである。ＳＯＩ装置はｎ+ 導電型のソース及びドレイン領域１０を有し、これらソース及びドレイン領域はそれぞれゲート領域及びドリフト領域に隣接する。ソース領域はｐ+ ソース層１１をも有し、従ってソース接点１２はソース領域１０とソース層１１との双方に接触している。ソース領域はｐ型本体９上に形成されている。ソース領域、ドレイン領域及びゲート電極１３の各々には電気接点１２が接触されている。
この既知の構造のものは高降服電圧特性を有するＳＯＩ半導体装置を構成するものである。
【０００４】
【発明が解決しようとする課題】
しかし、上述した既知の装置には、ブリッジ回路で遭遇するような、ソース高電位形態で順方向電流の飽和が大きくなるという問題がある。すなわち、ソースが高電位にフロートさせられると、順方向電流が比較的小さくなる。
【０００５】
本発明の目的は、この問題を回避することにより上述した従来の構造を改善せんとするにある。
【０００６】
【課題を解決するための手段】
本発明は、埋込絶縁層と、この埋込絶縁層上の珪素層と、この珪素層上の上側絶縁層とを具える薄膜ＳＯＩ装置であって、前記の珪素層が、横方向に延在するドリフト領域と、このドリフト領域の一端部のゲート領域であってこのゲート領域の上のゲート誘電体の上にゲート電極を有する当該ゲート領域と、前記の一端部とは反対側のドリフト領域の端部のドレイン領域と、前記のゲート領域から横方向で分離されたソース領域とを具えている当該薄膜ＳＯＩ装置において、
前記のドリフト領域が厚肉部分と薄肉部分との双方を有しており、前記のドリフト領域のドーピング濃度はゲート領域からドレイン領域の方向へ増大するように分布されており、前記のドリフト領域の薄肉部分は厚肉部分よりもドレイン領域に隣接して設けられていることを特徴とする。
【０００７】
ソース高電位動作中、ドリフト領域は電子の空乏化状態となる。しかし、ドリフト領域の厚肉部分には空乏化が行われない。ドリフト領域は横方向の線形ドーピング領域を有し、ドリフト領域の薄肉部分はドリフト領域の全長の１／３〜２／３の長さに亘って延在させ、上側絶縁層上に電界プレートを設け、この電界プレートをゲート電極と短絡させ、この電界プレートをドリフト領域の薄肉部分上で延在させるのが好ましい。
【０００８】
ドリフト領域が横方向の線形ドーピング領域を有すると、ドーピング濃度はゲート領域からドレイン領域の方向に増大する。この場合、空乏化はゲート領域の付近でゲート領域の左側に向けて一層著しいものとなる。その理由は、ゲート領域の左側に向けてドーピング濃度が少なくなる為である。この場合、ドリフト領域の薄肉部分はドレイン領域に隣接して設けられる。
【０００９】
本発明の装置によれば、逆電圧特性を実質的に既知の装置におけるのと同様に保つことができるとともに、既知の装置における順方向電流が負の基板電圧に対し著しく減少するのに対し、ブリッジ回路で遭遇するソース高電位形態での順方向電圧特性が順方向電流の飽和をほんのわずかしか生ぜしめないＳＯＩ回路を提供する。
【００１０】
【実施例】
図１及び２においては同じ部分に同じ符号を付してある。
【００１１】
本発明の装置は欧州特許出願第５４９０４２号の既知の装置を改善したものである。本発明の新規な装置は、欧州特許出願第５４９０４２号や、この欧州特許出願で従来技術として用いられている欧州特許出願第４９７４２７号で記載されている既知の装置の製造に類似する方法で製造した。この既知の装置の更なる詳細及びその製造処理に関しては、これらの欧州特許出願明細書を参照しうる。
【００１２】
本発明の装置は、ブリッジ回路の場合に生じるようなソース高電位動作中の順方向電流飽和を阻止する。このことは、本発明によれば、図２の珪素層２４，２５を、ＳＯＩ装置の横方向線形ドーピング領域を構成するドリフト領域の全長の約１／３〜２／３の部分２４においてのみ薄肉とすることにより達成する。この珪素層の左側部分２５は約１〜２ミクロンのように厚肉とし、右側部分２４は約０．１〜０．４ミクロンまで薄肉にする。
【００１３】
多結晶珪素ゲート電極２０は多結晶珪素電界プレート２７から分離させる。アルミニウムのような金属より成る相互接続金属２２を用いてゲート電極２０と電界プレート２７とを短絡し、この相互接続金属を珪素層の厚肉左側部分２５の上方の金属電界プレートとして作用させる。右側部分２４と電界プレート２７との間の中間の上側酸化物層６は埋込酸化物層２と同じ厚さで相互接続金属２２と珪素層の左側部分２５との間にも延在させる。
【００１４】
図３ａ及び３ｂは図１に示す装置のような既知の装置及び図２に示す本発明の新規な装置の逆電圧特性をそれぞれ示す。これら双方の装置では約６２０ボルトの同一の降服電圧が達成された。
【００１５】
一方、図４ａ及び４ｂは既知のＳＯＩ装置及び本発明のＳＯＩ装置の順方向電圧特性をそれぞれ示す。これらの双方では、基板を−１ボルトのステップで０ボルトから−２００ボルトまでバイアスした。この検査はブリッジ回路で用いられているソース高電位形態を表わす。従来の装置の順方向電流は負の基板電圧で著しく減少し、その結果順方向電流の飽和が大きくなる。本発明の改善した構造によれば、順方向電流の飽和をほんのわずかしか呈さない装置が得られる。
【００１６】
本発明の装置の変形例としては、ｎ+ ドレイン領域１０の代わりに薄肉のｐ+ドレイン領域を用いてＬＩＧＢＴ回路装置を形成することができる。しかしこの場合、ｐ+ ドレインをｎ型バッファ層上に配置する。
【図面の簡単な説明】
【図１】 既知のＳＯＩ装置を示す断面図である。
【図２】 本発明のＳＯＩ装置の一実施例を示す断面図である。
【図３】 図１の装置の逆方向電圧特性（ａ）と図２の装置の逆方向電圧特性（ｂ）との比較を示す線図である。
【図４】 図１の装置の順方向電圧特性（ａ）と図２の装置の順方向電圧特性（ｂ）との比較を示す線図である。
【符号の説明】
１ 珪素層（ゲート領域）
２ 埋込酸化物層
３ 基板
４ ドリフト領域（珪素層）
６ 上側酸化物層
７ 電界プレート
８ ゲート酸化物
９ ｐ型本体
１０ ソース及びドレイン領域
１１ ソース層
１２ 電気接点
１３ 多結晶ゲート電極
２０ 多結晶ゲート電極
２２ 相互接続金属
２４ 珪素層の右側部分
２５ 珪素層の左側部分
２７ 電界プレート

Claims (5)

  1. 埋込絶縁層と、この埋込絶縁層上の珪素層と、この珪素層上の上側絶縁層とを具える薄膜ＳＯＩ装置であって、前記の珪素層が、横方向に延在するドリフト領域と、このドリフト領域の一端部のゲート領域であってこのゲート領域の上のゲート誘電体の上にゲート電極を有する当該ゲート領域と、前記の一端部とは反対側のドリフト領域の端部のドレイン領域と、前記のゲート領域から横方向で分離されたソース領域とを具えている当該薄膜ＳＯＩ装置において、
    前記のドリフト領域が厚肉部分と薄肉部分との双方を有しており、前記のドリフト領域のドーピング濃度はゲート領域からドレイン領域の方向へ増大するように分布されており、前記のドリフト領域の薄肉部分は厚肉部分よりもドレイン領域に隣接して設けられていることを特徴とする薄膜ＳＯＩ装置。
  2. 請求項１に記載の薄膜ＳＯＩ装置において、前記のドリフト領域の薄肉部分がドリフト領域の全長の１／３〜２／３の長さに亘って延在し、前記の上側絶縁層上に電界プレートが設けられ、この電界プレートはゲート電極に短絡し且つドリフト領域の薄肉部分の上方で延在していることを特徴とする薄膜ＳＯＩ装置。
  3. 請求項１に記載の薄膜ＳＯＩ装置において、ドリフト領域の薄肉部分の厚さは０．１〜０．４μm にしたことを特徴とする薄膜ＳＯＩ装置。
  4. 請求項１に記載の薄膜ＳＯＩ装置において、前記の珪素層の厚さは前記の薄肉部分に隣接するドリフト領域において約１〜２μm としたことを特徴とする薄膜ＳＯＩ装置。
  5. 基板上の埋込酸化物層上に珪素層を形成する工程と、この珪素層の一部分を薄肉にする工程と、この珪素層のこの薄肉にした部分上に酸化物層を形成する工程と、この薄肉にした部分にかからないようにこの珪素層上にゲート誘電体及びゲート電極を設ける工程と、前記の珪素層の前記の薄肉にした部分の上方で前記の酸化物層上に電界プレートを延在させる工程と、この電界プレートと前記のゲート電極との間に短絡回路を設ける工程とを有することを特徴とする薄膜ＳＯＩ装置の製造方法。
JP18816194A 1993-08-10 1994-08-10 薄膜ｓｏｉ装置及びその製造方法 Expired - Fee Related JP3871352B2 (ja)

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