JP3696132B2 - アクティブマトリクス基板及びその製造方法 - Google Patents

アクティブマトリクス基板及びその製造方法 Download PDF

Info

Publication number
JP3696132B2
JP3696132B2 JP2001208724A JP2001208724A JP3696132B2 JP 3696132 B2 JP3696132 B2 JP 3696132B2 JP 2001208724 A JP2001208724 A JP 2001208724A JP 2001208724 A JP2001208724 A JP 2001208724A JP 3696132 B2 JP3696132 B2 JP 3696132B2
Authority
JP
Japan
Prior art keywords
substrate
control member
position control
active element
active
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001208724A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003022034A (ja
JP2003022034A5 (enExample
Inventor
雄二郎 原
政彦 秋山
豊 小野塚
毅 日置
充雄 中島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2001208724A priority Critical patent/JP3696132B2/ja
Priority to KR10-2002-0039600A priority patent/KR100521818B1/ko
Priority to US10/190,663 priority patent/US6828657B2/en
Publication of JP2003022034A publication Critical patent/JP2003022034A/ja
Publication of JP2003022034A5 publication Critical patent/JP2003022034A5/ja
Application granted granted Critical
Publication of JP3696132B2 publication Critical patent/JP3696132B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13613—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit the semiconductor element being formed on a first substrate and thereafter transferred to the final cell substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01055—Cesium [Cs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Landscapes

  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Engineering & Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Thin Film Transistor (AREA)
JP2001208724A 2001-07-10 2001-07-10 アクティブマトリクス基板及びその製造方法 Expired - Fee Related JP3696132B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2001208724A JP3696132B2 (ja) 2001-07-10 2001-07-10 アクティブマトリクス基板及びその製造方法
KR10-2002-0039600A KR100521818B1 (ko) 2001-07-10 2002-07-09 액티브 매트릭스 기판 및 그 제조 방법
US10/190,663 US6828657B2 (en) 2001-07-10 2002-07-09 Active matrix substrate and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001208724A JP3696132B2 (ja) 2001-07-10 2001-07-10 アクティブマトリクス基板及びその製造方法

Publications (3)

Publication Number Publication Date
JP2003022034A JP2003022034A (ja) 2003-01-24
JP2003022034A5 JP2003022034A5 (enExample) 2004-12-02
JP3696132B2 true JP3696132B2 (ja) 2005-09-14

Family

ID=19044490

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001208724A Expired - Fee Related JP3696132B2 (ja) 2001-07-10 2001-07-10 アクティブマトリクス基板及びその製造方法

Country Status (3)

Country Link
US (1) US6828657B2 (enExample)
JP (1) JP3696132B2 (enExample)
KR (1) KR100521818B1 (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3447619B2 (ja) * 1999-06-25 2003-09-16 株式会社東芝 アクティブマトリクス基板の製造方法、中間転写基板
JP3696131B2 (ja) * 2001-07-10 2005-09-14 株式会社東芝 アクティブマトリクス基板及びその製造方法
JP3946683B2 (ja) * 2003-09-25 2007-07-18 株式会社東芝 アクティブマトリクス基板の製造方法
JP4351012B2 (ja) * 2003-09-25 2009-10-28 浜松ホトニクス株式会社 半導体装置
JP4494746B2 (ja) * 2003-09-25 2010-06-30 浜松ホトニクス株式会社 半導体装置
JP4494745B2 (ja) * 2003-09-25 2010-06-30 浜松ホトニクス株式会社 半導体装置
KR100709255B1 (ko) * 2005-08-11 2007-04-19 삼성에스디아이 주식회사 평판 표시 장치 및 그 제조 방법
DE102005043657B4 (de) * 2005-09-13 2011-12-15 Infineon Technologies Ag Chipmodul, Verfahren zur Verkapselung eines Chips und Verwendung eines Verkapselungsmaterials
US20080122119A1 (en) * 2006-08-31 2008-05-29 Avery Dennison Corporation Method and apparatus for creating rfid devices using masking techniques
KR101446226B1 (ko) 2006-11-27 2014-10-01 엘지디스플레이 주식회사 플렉서블 표시장치 및 그 제조 방법
US8630326B2 (en) 2009-10-13 2014-01-14 Skorpios Technologies, Inc. Method and system of heterogeneous substrate bonding for photonic integration
US9922967B2 (en) 2010-12-08 2018-03-20 Skorpios Technologies, Inc. Multilevel template assisted wafer bonding
US8735191B2 (en) 2012-01-04 2014-05-27 Skorpios Technologies, Inc. Method and system for template assisted wafer bonding using pedestals
US9209142B1 (en) 2014-09-05 2015-12-08 Skorpios Technologies, Inc. Semiconductor bonding with compliant resin and utilizing hydrogen implantation for transfer-wafer removal
KR102402999B1 (ko) * 2015-08-31 2022-05-30 삼성디스플레이 주식회사 디스플레이 장치 및 이의 제조 방법
US9887119B1 (en) * 2016-09-30 2018-02-06 International Business Machines Corporation Multi-chip package assembly
CN108598089B (zh) * 2018-04-27 2020-09-29 武汉华星光电技术有限公司 Tft基板的制作方法及tft基板
CN112490174A (zh) * 2020-11-26 2021-03-12 深圳麦沄显示技术有限公司 一种芯片器件的转移方法
CN118511267A (zh) 2022-12-16 2024-08-16 厦门市芯颖显示科技有限公司 转移载板、转移组件及微器件转移方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5764776A (en) * 1980-10-09 1982-04-20 Nippon Denshi Kogyo Shinko Liquid crystal display unit
FR2679057B1 (fr) * 1991-07-11 1995-10-20 Morin Francois Structure d'ecran a cristal liquide, a matrice active et a haute definition.
JPH06230426A (ja) * 1993-02-04 1994-08-19 Fuji Xerox Co Ltd 液晶表示装置
US5545291A (en) 1993-12-17 1996-08-13 The Regents Of The University Of California Method for fabricating self-assembling microstructures
US5904545A (en) 1993-12-17 1999-05-18 The Regents Of The University Of California Apparatus for fabricating self-assembling microstructures
JP3447619B2 (ja) 1999-06-25 2003-09-16 株式会社東芝 アクティブマトリクス基板の製造方法、中間転写基板
TW543206B (en) * 1999-06-28 2003-07-21 Semiconductor Energy Lab EL display device and electronic device

Also Published As

Publication number Publication date
KR20030007065A (ko) 2003-01-23
US20030010970A1 (en) 2003-01-16
KR100521818B1 (ko) 2005-10-17
JP2003022034A (ja) 2003-01-24
US6828657B2 (en) 2004-12-07

Similar Documents

Publication Publication Date Title
JP3696132B2 (ja) アクティブマトリクス基板及びその製造方法
US7407839B2 (en) Method of manufacturing active matrix substrate with height control member
JP3875130B2 (ja) 表示装置及びその製造方法
US7081642B2 (en) Active matrix substrate display device
US6362866B1 (en) Liquid crystal electrooptical device
EP1751789B1 (en) Flexible electro-optical apparatus and method for manufacturing the same
US20040218133A1 (en) Flexible electro-optical apparatus and method for manufacturing the same
JP2009188317A (ja) 半導体装置、電気光学装置、電子機器、半導体装置の製造方法、電気光学装置の製造方法および電子機器の製造方法
US20100059753A1 (en) Matrix electronic devices using opaque substrates and fabrication method therefor
US20060172470A1 (en) Method of manufacturing thin film element
KR20060061169A (ko) 박막 트랜지스터 기판 및 제조 방법
KR100569202B1 (ko) 가요성 전기 광학 장치 및 그 제조 방법
JP3850324B2 (ja) アクティブマトリクス型表示装置およびその製造方法
JP5142546B2 (ja) 半導体装置及びその作製方法
US20070057256A1 (en) Element forming substrate, active matrix substrate, and method of manufacturing the same
JP4476991B2 (ja) 電気光学装置
JP5440996B2 (ja) 半導体装置、電気光学装置および電子機器
KR20070040017A (ko) 박막 트랜지스터 및 이의 제조방법
JP2006156455A (ja) 素子形成基板、中間転写基板、アクティブマトリクス基板およびその製造方法

Legal Events

Date Code Title Description
RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20050414

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20050606

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050617

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20050624

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20050628

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090708

Year of fee payment: 4

LAPS Cancellation because of no payment of annual fees