KR100521818B1 - 액티브 매트릭스 기판 및 그 제조 방법 - Google Patents

액티브 매트릭스 기판 및 그 제조 방법 Download PDF

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Publication number
KR100521818B1
KR100521818B1 KR10-2002-0039600A KR20020039600A KR100521818B1 KR 100521818 B1 KR100521818 B1 KR 100521818B1 KR 20020039600 A KR20020039600 A KR 20020039600A KR 100521818 B1 KR100521818 B1 KR 100521818B1
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KR
South Korea
Prior art keywords
position control
control member
substrate
active element
adhesive
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Expired - Fee Related
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KR10-2002-0039600A
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English (en)
Korean (ko)
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KR20030007065A (ko
Inventor
하라유지로
아끼야마마사히꼬
오노즈까유따까
히오끼쯔요시
나까지마미쯔오
Original Assignee
가부시끼가이샤 도시바
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Publication of KR20030007065A publication Critical patent/KR20030007065A/ko
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Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13613—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit the semiconductor element being formed on a first substrate and thereafter transferred to the final cell substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01055—Cesium [Cs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Landscapes

  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Engineering & Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Thin Film Transistor (AREA)
KR10-2002-0039600A 2001-07-10 2002-07-09 액티브 매트릭스 기판 및 그 제조 방법 Expired - Fee Related KR100521818B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2001-00208724 2001-07-10
JP2001208724A JP3696132B2 (ja) 2001-07-10 2001-07-10 アクティブマトリクス基板及びその製造方法

Publications (2)

Publication Number Publication Date
KR20030007065A KR20030007065A (ko) 2003-01-23
KR100521818B1 true KR100521818B1 (ko) 2005-10-17

Family

ID=19044490

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2002-0039600A Expired - Fee Related KR100521818B1 (ko) 2001-07-10 2002-07-09 액티브 매트릭스 기판 및 그 제조 방법

Country Status (3)

Country Link
US (1) US6828657B2 (enExample)
JP (1) JP3696132B2 (enExample)
KR (1) KR100521818B1 (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3447619B2 (ja) * 1999-06-25 2003-09-16 株式会社東芝 アクティブマトリクス基板の製造方法、中間転写基板
JP3696131B2 (ja) * 2001-07-10 2005-09-14 株式会社東芝 アクティブマトリクス基板及びその製造方法
JP3946683B2 (ja) * 2003-09-25 2007-07-18 株式会社東芝 アクティブマトリクス基板の製造方法
JP4494746B2 (ja) * 2003-09-25 2010-06-30 浜松ホトニクス株式会社 半導体装置
JP4494745B2 (ja) * 2003-09-25 2010-06-30 浜松ホトニクス株式会社 半導体装置
JP4351012B2 (ja) * 2003-09-25 2009-10-28 浜松ホトニクス株式会社 半導体装置
KR100709255B1 (ko) * 2005-08-11 2007-04-19 삼성에스디아이 주식회사 평판 표시 장치 및 그 제조 방법
DE102005043657B4 (de) * 2005-09-13 2011-12-15 Infineon Technologies Ag Chipmodul, Verfahren zur Verkapselung eines Chips und Verwendung eines Verkapselungsmaterials
US20080122119A1 (en) * 2006-08-31 2008-05-29 Avery Dennison Corporation Method and apparatus for creating rfid devices using masking techniques
KR101446226B1 (ko) 2006-11-27 2014-10-01 엘지디스플레이 주식회사 플렉서블 표시장치 및 그 제조 방법
US8630326B2 (en) 2009-10-13 2014-01-14 Skorpios Technologies, Inc. Method and system of heterogeneous substrate bonding for photonic integration
US9922967B2 (en) 2010-12-08 2018-03-20 Skorpios Technologies, Inc. Multilevel template assisted wafer bonding
US8735191B2 (en) 2012-01-04 2014-05-27 Skorpios Technologies, Inc. Method and system for template assisted wafer bonding using pedestals
US9209142B1 (en) * 2014-09-05 2015-12-08 Skorpios Technologies, Inc. Semiconductor bonding with compliant resin and utilizing hydrogen implantation for transfer-wafer removal
KR102402999B1 (ko) 2015-08-31 2022-05-30 삼성디스플레이 주식회사 디스플레이 장치 및 이의 제조 방법
US9887119B1 (en) * 2016-09-30 2018-02-06 International Business Machines Corporation Multi-chip package assembly
CN108598089B (zh) * 2018-04-27 2020-09-29 武汉华星光电技术有限公司 Tft基板的制作方法及tft基板
CN112490174A (zh) * 2020-11-26 2021-03-12 深圳麦沄显示技术有限公司 一种芯片器件的转移方法
WO2024124535A1 (zh) 2022-12-16 2024-06-20 厦门市芯颖显示科技有限公司 转移载板、转移组件及微器件转移方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5764776A (en) * 1980-10-09 1982-04-20 Nippon Denshi Kogyo Shinko Liquid crystal display unit
FR2679057B1 (fr) * 1991-07-11 1995-10-20 Morin Francois Structure d'ecran a cristal liquide, a matrice active et a haute definition.
JPH06230426A (ja) * 1993-02-04 1994-08-19 Fuji Xerox Co Ltd 液晶表示装置
US5904545A (en) 1993-12-17 1999-05-18 The Regents Of The University Of California Apparatus for fabricating self-assembling microstructures
US5545291A (en) 1993-12-17 1996-08-13 The Regents Of The University Of California Method for fabricating self-assembling microstructures
JP3447619B2 (ja) 1999-06-25 2003-09-16 株式会社東芝 アクティブマトリクス基板の製造方法、中間転写基板
TW543206B (en) * 1999-06-28 2003-07-21 Semiconductor Energy Lab EL display device and electronic device

Also Published As

Publication number Publication date
KR20030007065A (ko) 2003-01-23
US20030010970A1 (en) 2003-01-16
US6828657B2 (en) 2004-12-07
JP2003022034A (ja) 2003-01-24
JP3696132B2 (ja) 2005-09-14

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