JP3629050B2 - 同期式２進カウンタ - Google Patents

同期式２進カウンタ Download PDF

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Publication number
JP3629050B2
JP3629050B2 JP27350694A JP27350694A JP3629050B2 JP 3629050 B2 JP3629050 B2 JP 3629050B2 JP 27350694 A JP27350694 A JP 27350694A JP 27350694 A JP27350694 A JP 27350694A JP 3629050 B2 JP3629050 B2 JP 3629050B2
Authority
JP
Japan
Prior art keywords
stage
carry signal
counting
signal
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP27350694A
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English (en)
Japanese (ja)
Other versions
JPH07193492A (ja
Inventor
始烈 李
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JPH07193492A publication Critical patent/JPH07193492A/ja
Application granted granted Critical
Publication of JP3629050B2 publication Critical patent/JP3629050B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/40—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using contact-making devices, e.g. electromagnetic relay
    • G06F7/42—Adding; Subtracting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Electromagnetism (AREA)
  • Dram (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Manipulation Of Pulses (AREA)
  • Inverter Devices (AREA)
JP27350694A 1993-11-08 1994-11-08 同期式２進カウンタ Expired - Fee Related JP3629050B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1993P23598 1993-11-08
KR1019930023598A KR950015184B1 (ko) 1993-11-08 1993-11-08 동기식 이진카운터

Publications (2)

Publication Number Publication Date
JPH07193492A JPH07193492A (ja) 1995-07-28
JP3629050B2 true JP3629050B2 (ja) 2005-03-16

Family

ID=19367538

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27350694A Expired - Fee Related JP3629050B2 (ja) 1993-11-08 1994-11-08 同期式２進カウンタ

Country Status (7)

Country Link
US (1) US5559844A (enExample)
JP (1) JP3629050B2 (enExample)
KR (1) KR950015184B1 (enExample)
CN (1) CN1088941C (enExample)
DE (1) DE4439929C2 (enExample)
GB (1) GB2284082B (enExample)
TW (1) TW287332B (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5692026A (en) * 1996-05-31 1997-11-25 Hewlett-Packard Company Apparatus for reducing capacitive loading of clock and shift signals by shifting register-based devices
US6031887A (en) * 1997-07-30 2000-02-29 Lucent Technolgies Inc. High-speed binary synchronous counter
US5946369A (en) * 1997-07-30 1999-08-31 Lucent Technologies Inc. High-speed binary synchronous counter with precomputation of carry-independent terms
US6642758B1 (en) * 1998-11-03 2003-11-04 Altera Corporation Voltage, temperature, and process independent programmable phase shift for PLL
US7109765B1 (en) 1998-11-03 2006-09-19 Altera Corporation Programmable phase shift circuitry
US6470064B2 (en) * 2000-01-11 2002-10-22 Raytheon Company Extended length counter chains in FPGA logic
US6707874B2 (en) 2002-04-15 2004-03-16 Charles Douglas Murphy Multiple-output counters for analog-to-digital and digital-to-analog conversion
US20040024803A1 (en) * 2002-07-31 2004-02-05 Allen Montijo Cascaded modified PRBS counters form easily programmed and efficient large counter
US7149275B1 (en) * 2004-01-29 2006-12-12 Xilinx, Inc. Integrated circuit and method of implementing a counter in an integrated circuit
CN1321500C (zh) * 2004-04-14 2007-06-13 武汉大学 一种高速同步计数器
CN102609317B (zh) * 2012-01-13 2014-05-14 从兴技术有限公司 一种信号量的处理方法及系统
US12040797B2 (en) * 2022-05-23 2024-07-16 Changxin Memory Technologies, Inc. Counter circuit

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960003526B1 (ko) * 1992-10-02 1996-03-14 삼성전자주식회사 반도체 메모리장치
US4513432A (en) * 1982-06-30 1985-04-23 At&T Bell Laboratories Multiple self-contained logic gate counter circuit
US4621370A (en) * 1984-05-29 1986-11-04 Gte Communication Systems Corporation Binary synchronous count and clear bit-slice module
US4741006A (en) * 1984-07-12 1988-04-26 Kabushiki Kaisha Toshiba Up/down counter device with reduced number of discrete circuit elements
JPS6240824A (ja) * 1985-08-19 1987-02-21 Toshiba Corp 同期型バイナリカウンタ
JPS62165433A (ja) * 1986-01-17 1987-07-22 Matsushita Electric Ind Co Ltd 同期型カウンタ回路
US4780894A (en) * 1987-04-17 1988-10-25 Lsi Logic Corporation N-bit gray code counter
US4856035A (en) * 1988-05-26 1989-08-08 Raytheon Company CMOS binary up/down counter
JP2733251B2 (ja) * 1988-06-30 1998-03-30 シャープ株式会社 同期式プログラマブルカウンタ
US4924484A (en) * 1988-10-27 1990-05-08 International Business Machines Corp. High speed digital counter
JPH04239819A (ja) * 1991-01-24 1992-08-27 Oki Electric Ind Co Ltd 同期式カウンタ
DE4201776C1 (en) * 1992-01-23 1993-09-16 Hurth Maschinen Und Werkzeuge Gmbh, 8000 Muenchen, De Synchronous dual counter stage using flip=flops - has AND=gate receiving all flip=flop outputs controlling memory flip=flop coupled to transfer output of dual counter stage
US5237597A (en) * 1992-03-20 1993-08-17 Vlsi Technology, Inc. Binary counter compiler with balanced carry propagation

Also Published As

Publication number Publication date
KR950015184B1 (ko) 1995-12-23
DE4439929C2 (de) 2000-07-06
CN1088941C (zh) 2002-08-07
KR950015061A (ko) 1995-06-16
US5559844A (en) 1996-09-24
TW287332B (enExample) 1996-10-01
CN1109660A (zh) 1995-10-04
GB9422528D0 (en) 1995-01-04
DE4439929A1 (de) 1995-05-11
GB2284082B (en) 1998-02-11
GB2284082A (en) 1995-05-24
JPH07193492A (ja) 1995-07-28

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