JP3353534B2 - Electronic circuit device and electronic circuit components - Google Patents
Electronic circuit device and electronic circuit componentsInfo
- Publication number
- JP3353534B2 JP3353534B2 JP10342495A JP10342495A JP3353534B2 JP 3353534 B2 JP3353534 B2 JP 3353534B2 JP 10342495 A JP10342495 A JP 10342495A JP 10342495 A JP10342495 A JP 10342495A JP 3353534 B2 JP3353534 B2 JP 3353534B2
- Authority
- JP
- Japan
- Prior art keywords
- electronic circuit
- electrodes
- electrode
- circuit board
- circuit component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電子回路部品の下面電
極と回路基板の上面電極をはんだバンプで接続してなる
電子回路装置に係り、特に、電子回路部品もしくは回路
基板の反りによって、電子回路部品の下面と回路基板の
上面とのすき間が電子回路部品の領域において異なる電
子回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit device in which a lower electrode of an electronic circuit component and an upper electrode of a circuit board are connected by solder bumps. The present invention relates to an electronic circuit device in which a gap between a lower surface of a circuit component and an upper surface of a circuit board is different in a region of the electronic circuit component.
【０００２】[0002]
【従来の技術】電子回路部品の下面電極と回路基板の上
面電極をはんだバンプで接続してなる電子回路装置で
は、従来、電極間隔が等間隔で、電極面積が全て等し
く、はんだバンプの大きさが全て等しい構造となってい
る。2. Description of the Related Art In an electronic circuit device in which the lower electrode of an electronic circuit component and the upper electrode of a circuit board are connected by solder bumps, conventionally, the electrode intervals are equal, the electrode areas are all equal, and the size of the solder bumps is large. Have the same structure.
【０００３】[0003]
【発明が解決しようとする課題】しかし上記従来技術で
は、電子回路部品もしくは回路基板の反りによって、電
子回路部品の下面と回路基板の上面とのすき間が電子回
路部品の領域において異なる場合に、図４に示すように
すき間が狭い部位でははんだバンプのつぶれ量が多くな
り、隣接のはんだバンプと接触するショート不良６を生
じ、逆にすき間が広い部位でははんだバンプに所定のつ
ぶれ量が得られず電子回路部品の下面電極と回路基板の
上面電極の確実な接続が得られないオープン不良７を生
じるという問題がある。However, according to the above-mentioned prior art, when the gap between the lower surface of the electronic circuit component and the upper surface of the circuit board is different in the area of the electronic circuit component due to the warpage of the electronic circuit component or the circuit board, it is difficult to achieve the above-mentioned problem. As shown in FIG. 4, in a portion where the gap is narrow, the amount of crushing of the solder bump increases, and short-circuit failure 6 in contact with an adjacent solder bump occurs. Conversely, in a portion where the gap is wide, a predetermined amount of crushing of the solder bump is not obtained. There is a problem that an open defect 7 occurs in which a reliable connection between the lower electrode of the electronic circuit component and the upper electrode of the circuit board cannot be obtained.
【０００４】本発明の目的は、電子回路部品もしくは回
路基板の反りによって、電子回路部品の下面と回路基板
の上面とのすき間が電子回路部品の領域において異なる
電子回路装置において、ショート不良もしくはオープン
不良を生じない電子回路装置を提供することにある。An object of the present invention is to provide a short circuit or open circuit in an electronic circuit device in which the gap between the lower surface of the electronic circuit component and the upper surface of the circuit substrate differs in the area of the electronic circuit component due to the warpage of the electronic circuit component or the circuit board. It is an object of the present invention to provide an electronic circuit device which does not cause the problem.
【０００５】[0005]
【課題を解決するための手段】上記目的を解決する電子
回路装置の一つの態様として、電子回路部品と回路基板
のすき間が狭い部位の電極間隔が、すき間が広い部位の
電極間隔よりも大きくなっているものがある。 また、本
発明の電子回路装置の他の態様として、凹状に反る電子
回路部品の電極と凸状に反る回路基板の電極をはんだバ
ンプで接続されている電子回路装置において、電子回路
部品の回路基板との接続に用いる電極の配置が、中央の
電極間隔の方が周辺の電極間隔よりも大きくなっている
ものがある。。 また、上記目的を解決するのに、好まし
い電子回路部品の態様として、凹状に反る電子回路部品
において、回路基板との接続に用いる電極の配置が、中
央の電極間隔の方が周辺の電極間隔よりも大きくなって
いるものがある。 In one embodiment of the you achieve the object electronic circuit device Means for Solving the Problems], the electronic circuit component and the circuit board
The gap between the electrodes in the area with a narrow gap is
Some are larger than the electrode spacing. Also book
As another aspect of the electronic circuit device of the invention, a concavely warped electron
Connect the electrodes of the circuit components and the electrodes of the circuit board
Electronic circuit device connected by a
The arrangement of the electrodes used to connect the components to the circuit board
The electrode spacing is larger than the surrounding electrode spacing
There is something. . Also, it is preferable to solve the above purpose.
Electronic circuit components that are concavely warped
In, the arrangement of the electrodes used for connection with the circuit board is
The center electrode spacing is larger than the surrounding electrode spacing
There is something.
【０００６】[0006]
【作用】本発明は、すき間が狭い部位の電極間隔を広く
したことにより、すき間が狭い部位でのショート不良を
無くすことができ、そのためにはんだバンプのつぶれ量
を多くすることができるためすき間が広い部位でのオー
プン不良をも無くすことができる。According to the present invention, by increasing the electrode spacing in a portion where the gap is small, it is possible to eliminate short-circuit defects in a portion where the gap is small, and to increase the amount of crushing of the solder bumps. An open defect in a wide area can be eliminated.
【０００７】また、すき間が狭い部位の電極面積を大き
くしたことにより、すき間が狭い部位でのはんだバンプ
の電極からはみ出しが少なくなってショート不良を無く
すことができ、また全体としてはんだバンプの高さが低
くなり、したがってすき間が広い部位のはんだバンプの
つぶれ量不足が無く、オープン不良を無くすことができ
る。In addition, by increasing the electrode area at the portion where the gap is narrow, the protrusion of the solder bump at the portion where the gap is narrow is reduced so that short-circuit failure can be eliminated, and the height of the solder bump as a whole can be reduced. Therefore, there is no shortage of the amount of crushing of the solder bump in a portion having a wide gap, and an open defect can be eliminated.
【０００８】またすき間が狭い部位ほどはんだバンプの
大きさを小さくすることにより、すき間が狭い部位にお
ける隣接はんだバンプ同士の接触すなわちショート不良
を無くすことができる。Further, by making the size of the solder bump smaller in a portion having a smaller gap, it is possible to eliminate contact between adjacent solder bumps in a portion having a smaller gap, that is, a short circuit failure.
【０００９】[0009]
【実施例】本発明の第１の実施例を図１により説明す
る。図１は第１の実施例の構造を示す側面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a side view showing the structure of the first embodiment.
【００１０】電子回路部品１は凹状に反っており、ま
た、回路基板２は凸状に反っており、電子回路部品１の
下面と回路基板２の上面のすき間は中央程狭くなってい
る。これに対応して電子回路部品１の下面電極３（３a
〜３k）及び回路基板２の上面電極４（４a〜４k）の大
きさは全て等しいが、その間隔は中央程広くなってい
る。すなわち、３eと３f及び４eと４fの間隔は、３aと
３b及び４aと４cあるいは３jと３k及び４jと４kの間隔
よりも広い。The electronic circuit component 1 is warped in a concave shape, and the circuit board 2 is warped in a convex shape. The gap between the lower surface of the electronic circuit component 1 and the upper surface of the circuit board 2 becomes narrower toward the center. Correspondingly, the lower electrode 3 (3a
3k) and the upper surface electrodes 4 (4a to 4k) of the circuit board 2 are all equal in size, but the distance between them is wider toward the center. That is, the intervals between 3e and 3f and between 4e and 4f are wider than the intervals between 3a and 3b, 4a and 4c, or 3j and 3k and 4j and 4k.
【００１１】はんだバンプ５は全てについて体積が等し
いため中央のもの程つぶれ量が大きい。すなわち、はん
だバンプ５e及び５fが、５a、５b及び５j、５kに比べて
高さが低く、その分だけ電極からはみ出している部分の
横幅が大きい。ところが電極の間隔が大きいために中央
部におけるはんだバンプ５eと５fの接触によるショート
不良を無くすことができる。Since all the solder bumps 5 have the same volume, the crush amount is larger at the center. That is, the heights of the solder bumps 5e and 5f are lower than those of the solder bumps 5a, 5b, 5j, and 5k, and the width of the portion protruding from the electrode is correspondingly large. However, since the distance between the electrodes is large, it is possible to eliminate short-circuit failure due to the contact between the solder bumps 5e and 5f at the center.
【００１２】本発明の第２の実施例を図２により説明す
る。図２は第２の実施例の構造を示す側面図である。A second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a side view showing the structure of the second embodiment.
【００１３】電子回路部品１は凹状に反っており、ま
た、回路基板２は凸状に反っており、電子回路部品１の
下面と回路基板２の上面のすき間は中央程狭くなってい
る。これに対応して電子回路部品１の下面電極３及び回
路基板２の上面電極４の面積、すなわち、電極径は、中
央程大きくなっている。すなわち、３e、３f及び４e、
４fの電極径は３a、３b及び４a、４c３j、３k及び４j、
４kの電極径より大きい。The electronic circuit component 1 is warped in a concave shape, and the circuit board 2 is warped in a convex shape. The gap between the lower surface of the electronic circuit component 1 and the upper surface of the circuit board 2 becomes narrower toward the center. Correspondingly, the area of the lower surface electrode 3 of the electronic circuit component 1 and the upper surface electrode 4 of the circuit board 2, that is, the electrode diameter increases toward the center. That is, 3e, 3f and 4e,
The electrode diameter of 4f is 3a, 3b and 4a, 4c3j, 3k and 4j,
It is larger than the electrode diameter of 4k.
【００１４】はんだバンプ５は全てについて体積が等し
く、また電子回路装置の製造過程における溶融工程にお
いて、下面電極３及び上面電極４の表面にぬれ広がるた
めに、中央のもの程溶融後の高さが低くなる。すなわ
ち、はんだバンプ５e及び５fは、５a、５b及び５j、５k
に比べて高さが低い。しかし電極の面積が大きいため電
極からはみ出している部分は少なく、隣接はんだバンプ
との接触は無い。また電極からのはみ出しが少ないため
溶融時において電子回路部品１を上に押し上げる浮力が
小さく、したがって全体としてはんだバンプの高さが低
くなり周辺部分、すなわち、はんだバンプ５a、５b及び
５e、５kにおけるオープン不良も無い。The solder bumps 5 all have the same volume, and in the melting step in the manufacturing process of the electronic circuit device, the solder bumps 5 are wetted and spread on the surfaces of the lower electrode 3 and the upper electrode 4. Lower. That is, the solder bumps 5e and 5f are 5a, 5b and 5j, 5k
The height is lower than. However, since the area of the electrode is large, the portion protruding from the electrode is small, and there is no contact with the adjacent solder bump. In addition, since there is little protrusion from the electrodes, the buoyancy for pushing up the electronic circuit component 1 during melting is small, and therefore the height of the solder bumps is reduced as a whole, so that the open portions in the peripheral portions, that is, the solder bumps 5a, 5b and 5e, 5k are opened. There is no defect.
【００１５】本発明の第３の実施例を図３により説明す
る。図３は第３の実施例の構造を示す側面図である。A third embodiment of the present invention will be described with reference to FIG. FIG. 3 is a side view showing the structure of the third embodiment.
【００１６】電子回路部品１は凹状に反っており、ま
た、回路基板２は凸状に反っており、電子回路部品１の
下面と回路基板２の上面のすき間は中央程狭くなってい
る。これに対応してはんだバンプ５は中央程小さくなっ
ている。すなわち、はんだバンプ５e、５fは５a、５b及
び５j、５kに比べて体積が小さい。したがってはんだバ
ンプ５e、５fは電極からのはみ出し部分が少なく、隣接
バンプとの接触が無い。また中央のはんだバンプ５e、
５fの高さは低く、逆に周辺のはんだバンプ５a、５b及
び５j、５kの高さは高くなるため、周辺部におけるオー
プン不良も無い。The electronic circuit component 1 is warped in a concave shape, and the circuit board 2 is warped in a convex shape. The gap between the lower surface of the electronic circuit component 1 and the upper surface of the circuit board 2 becomes narrower toward the center. Correspondingly, the solder bump 5 becomes smaller toward the center. That is, the solder bumps 5e and 5f are smaller in volume than 5a, 5b and 5j and 5k. Therefore, the solder bumps 5e and 5f have few protruding portions from the electrodes, and there is no contact with adjacent bumps. Also, the central solder bump 5e,
Since the height of 5f is low and the height of the peripheral solder bumps 5a, 5b, 5j, and 5k is high, there is no open defect in the peripheral portion.
【００１７】以上の実施例では電子回路部品１の反りを
凹状、回路基板２の反りを凸状としたが、反りがその逆
方向であってもよい。この場合には周辺部程すき間が狭
くなる。In the above embodiment, the warpage of the electronic circuit component 1 is concave and the warpage of the circuit board 2 is convex, but the warp may be in the opposite direction. In this case, the clearance becomes narrower in the peripheral portion.
【００１８】また実施例１、２、３はそれぞれ単独では
なく、組み合わせて実施してもよい。The first, second, and third embodiments may not be used alone, but may be implemented in combination.
【００１９】[0019]
【本発明の効果】本発明によれば、ショート不良及びオ
ープン不良の少ない電子回路装置を得ることができる。According to the present invention the effect of the present invention, it is possible to obtain a sheet Yoto defects and open defects with less electronic circuit device.
【図１】本発明の第１の実施例の構造を示す側面図。FIG. 1 is a side view showing the structure of a first embodiment of the present invention.
【図２】本発明の第２の実施例の構造を示す側面図。FIG. 2 is a side view showing the structure of a second embodiment of the present invention.
【図３】本発明の第３の実施例の構造を示す側面図。FIG. 3 is a side view showing the structure of a third embodiment of the present invention.
【図４】従来技術における不良を説明する側面図。FIG. 4 is a side view illustrating a defect in the related art.
１…電子回路部品、 ２…回路基板、 ３…下面電極、 ４…上面電極、 ５…はんだバンプ。 DESCRIPTION OF SYMBOLS 1 ... Electronic circuit component, 2 ... Circuit board, 3 ... Lower surface electrode, 4 ... Upper surface electrode, 5 ... Solder bump.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 鈴木 高道 神奈川県横浜市戸塚区吉田町292番地株 式会社日立製作所生産技術研究所内 (72)発明者 村瀬 友彦 神奈川県横浜市戸塚区吉田町292番地株 式会社日立製作所生産技術研究所内 (56)参考文献 特開 昭58−124260（ＪＰ，Ａ) 特開 平３−190238（ＪＰ，Ａ) 特開 平７−22538（ＪＰ，Ａ) 特開 平７−193162（ＪＰ，Ａ) 特開 平８−97322（ＪＰ，Ａ) 特開 平８−125062（ＪＰ，Ａ) 特開 平８−162560（ＪＰ，Ａ) 特開 平８−274102（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 H01L 21/60 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Takamichi Suzuki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Research Institute of Production Technology, Hitachi, Ltd. (72) Tomohiko Murase 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa (56) References JP-A-58-124260 (JP, A) JP-A-3-190238 (JP, A) JP-A-7-22538 (JP, A) JP-A-7-193162 (JP, A) JP-A-8-97322 (JP, A) JP-A-8-125062 (JP, A) JP-A-8-162560 (JP, A) JP-A-8-274102 (JP) , A) (58) Field surveyed (Int. Cl. 7 , DB name) H01L 23/12 H01L 21/60
Claims (3)
んだバンプが接続されている電子回路装置において、 前記電子回路部品と前記回路基板のすき間が狭い部位の
電極間隔が、該すき間が広い部位の電極間隔よりも大き
いことを特徴とする電子回路装置。1. A electronic circuit device electronics of electrodes and the circuit solder bump electrodes of the substrate are connected, said electronic circuit component and the circuit electrode spacing gap is narrow portion of the substrate is, the gap is wide An electronic circuit device, wherein the distance is larger than a distance between electrodes of a part.
る回路基板の電極がはんだバンプで接続されている電子
回路装置において、電子回路部品の回路基板との接続に用いる電極の配置
は、中央の方が周辺よりも大きくなるようになされてい
る ことを特徴とする電子回路装置。2. An electrode for an electronic circuit component which is warped in a concave shape and which has a convex shape.
In the electronic circuit device electrodes of the circuit board are connected by solder bumps that the arrangement of the electrodes used for connection between the circuit board of the electronic circuit component
Is designed so that the center is larger than the periphery
Electronic circuit device, characterized in that that.
隔の方が周辺の電極間隔よりも大きくなるようになされ
ていることを特徴とする電子回路部品。 3. An electronic circuit component which is concavely warped, wherein an arrangement of electrodes used for connection with a circuit board is determined by a distance between central electrodes.
The distance between the electrodes is larger than the distance between the surrounding electrodes.
An electronic circuit component comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10342495A JP3353534B2 (en) | 1995-04-27 | 1995-04-27 | Electronic circuit device and electronic circuit components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10342495A JP3353534B2 (en) | 1995-04-27 | 1995-04-27 | Electronic circuit device and electronic circuit components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08298264A JPH08298264A (en) | 1996-11-12 |
| JP3353534B2 true JP3353534B2 (en) | 2002-12-03 |
Family
ID=14353663
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10342495A Expired - Lifetime JP3353534B2 (en) | 1995-04-27 | 1995-04-27 | Electronic circuit device and electronic circuit components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3353534B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6477011A (en) * | 1988-04-18 | 1989-03-23 | Minolta Camera Kk | Automatic focusing interchangeable lens camera |
| JPH098081A (en) * | 1995-06-20 | 1997-01-10 | Fujitsu General Ltd | Mounting structure of bga package |
| JPH09283562A (en) * | 1996-04-18 | 1997-10-31 | Nec Corp | Integrated circuit device and method of connecting it to substrate |
| WO1998040912A1 (en) * | 1997-03-10 | 1998-09-17 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Chip arrangement and method for the production of the same |
| JP4719009B2 (en) * | 2006-01-13 | 2011-07-06 | ルネサスエレクトロニクス株式会社 | Substrate and semiconductor device |
| JP2010093109A (en) * | 2008-10-09 | 2010-04-22 | Renesas Technology Corp | Semiconductor device, method of manufacturing the same, and method of manufacturing semiconductor module |
| JP5923725B2 (en) * | 2012-05-15 | 2016-05-25 | パナソニックＩｐマネジメント株式会社 | Electronic component mounting structure |
| CN104377181B (en) * | 2013-08-15 | 2018-06-15 | 日月光半导体制造股份有限公司 | Semiconductor package assembly and a manufacturing method thereof |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6059743B2 (en) * | 1978-09-22 | 1985-12-26 | 株式会社日立製作所 | Semiconductor integrated circuit device |
| JPS6041728Y2 (en) * | 1979-12-24 | 1985-12-19 | 超エル・エス・アイ技術研究組合 | semiconductor equipment |
| JPS58124260A (en) * | 1982-01-20 | 1983-07-23 | Nec Corp | Circuit board |
| JPS6384050A (en) * | 1986-09-26 | 1988-04-14 | Nec Corp | Integrated circuit |
| JPH02105420A (en) * | 1988-10-13 | 1990-04-18 | Nec Corp | Flip-flop element |
| JPH0316327U (en) * | 1989-06-29 | 1991-02-19 | ||
| JP2788656B2 (en) * | 1989-10-19 | 1998-08-20 | 日本特殊陶業株式会社 | Manufacturing method of package for integrated circuit |
| JPH03190238A (en) * | 1989-12-20 | 1991-08-20 | Matsushita Electric Ind Co Ltd | Semiconductor chip and mounting structure using same chip |
| JP3285919B2 (en) * | 1992-02-05 | 2002-05-27 | 株式会社東芝 | Semiconductor device |
| JP3291368B2 (en) * | 1993-07-06 | 2002-06-10 | シチズン時計株式会社 | Structure of ball grid array type semiconductor package |
| JP3632930B2 (en) * | 1993-12-27 | 2005-03-30 | 株式会社ルネサステクノロジ | Ball grid array semiconductor device |
| JPH07254631A (en) * | 1994-03-15 | 1995-10-03 | Hitachi Ltd | Electronic circuit device and manufacture thereof |
| JPH0897322A (en) * | 1994-09-22 | 1996-04-12 | Oki Electric Ind Co Ltd | Semiconductor package |
| JPH08125062A (en) * | 1994-10-28 | 1996-05-17 | Seiko Epson Corp | Semiconductor device and its manufacture |
| JPH08162560A (en) * | 1994-12-01 | 1996-06-21 | Matsushita Electric Ind Co Ltd | Electronic part |
| JPH08274102A (en) * | 1995-03-31 | 1996-10-18 | Nec Corp | Method for forming in bump |
-
1995
- 1995-04-27 JP JP10342495A patent/JP3353534B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08298264A (en) | 1996-11-12 |
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