JP2004014778A - Semiconductor device and method of manufacturing same - Google Patents

Semiconductor device and method of manufacturing same Download PDF

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Publication number
JP2004014778A
JP2004014778A JP2002165632A JP2002165632A JP2004014778A JP 2004014778 A JP2004014778 A JP 2004014778A JP 2002165632 A JP2002165632 A JP 2002165632A JP 2002165632 A JP2002165632 A JP 2002165632A JP 2004014778 A JP2004014778 A JP 2004014778A
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Japan
Prior art keywords
electrode
bump
semiconductor device
wiring
bump electrode
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JP2002165632A
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Japanese (ja)
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JP2004014778A5 (en
JP3970694B2 (en
Inventor
Kazuhiro Ban
伴 和弘
Shigeru Shimizu
清水 茂
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Renesas Technology Corp
Hitachi Solutions Technology Ltd
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Renesas Technology Corp
Hitachi ULSI Systems Co Ltd
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Priority to JP2002165632A priority Critical patent/JP3970694B2/en
Publication of JP2004014778A publication Critical patent/JP2004014778A/en
Publication of JP2004014778A5 publication Critical patent/JP2004014778A5/ja
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    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13018Shape in side view comprising protrusions or indentations
    • H01L2224/13019Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8134Bonding interfaces of the bump connector
    • H01L2224/81345Shape, e.g. interlocking features
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    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
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    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
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    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8336Bonding interfaces of the semiconductor or solid state body
    • H01L2224/83365Shape, e.g. interlocking features
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    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
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    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To improve conductivity between a bump electrode and an electrode located on a board in a face-down mounting manner wherein a mounting operation is carried out through an anisotropic conductive film. <P>SOLUTION: Two or more conical or trapezoidal protrusions 12a formed of passivation films 12 are previously formed on a wiring electrode 11 when the bump electrode 14 is formed. In this state, a bump underlying metal layer 13 is deposited, and furthermore a gold electrode is formed thereon through a deposition growth method so as to serve as the bump electrode 14. Irregularities are formed on the electrode surface of the bump electrode 14 corresponding to the irregularities provided on the wiring electrode 11, so that the plane of the electrode can be improved in flatness as a whole. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は、半導体装置およびその製造技術に関し、特に、バンプ電極を用いたフリップチップ方式で実装される半導体装置に適用して有効な技術である。
【0002】
【従来の技術】
以下に説明する技術は、本発明を研究、完成するに際し、本発明者によって検討されたものであり、その概要は次のとおりである。
【0003】
半導体チップ等の半導体装置では、その小型化、高密度実装化等が強く求められている。かかる技術的要請に対して、バンプ電極を設けた半導体チップを、フェイスダウンの状態で実装基板側に位置合わせし、バンプ電極と実装基板側電極とを接続する、いわゆるフリップチップ方式による実装技術が広く採用されている。
【0004】
かかるフリップチップ方式による実装としては、例えば、チップ・オン・ガラス(COG)方式、チップ・オン・フィルム(COF)方式、チップ・オン・ボード(COB)方式等の実装方式が知られている。
【0005】
近年、高精細化、画素数の増大化が求められている液晶技術の分野でも、例えば、液晶表示に係る電圧切替えを制御するLCDドライバの実装方式として、上記方法が積極的に採用されている。
【0006】
【発明が解決しようとする課題】
ところが、上記技術においては、以下の課題があることを本発明者は見出した。
【0007】
上記フリップチップ方式の実装は、一般的には、半導体装置側のバンプ電極と、実装基板側電極との間に、異方性導電樹脂等で構成される異方性導電膜を介在させて、バンプ電極を実装基板側電極に加熱圧着することにより行われている。
【0008】
かかる実装に際してのバンプ電極と実装基板側電極との電気的接続は、異方性導電膜に含まれる導電性粒子が、バンプ電極と実装基板側電極との間に介在させられることにより確保されることとなる。
【0009】
すなわち、加熱圧着により、異方性導電性膜内に含まれていた導電性粒子が、バンプ電極と実装基板側電極との間に挟まれて、両電極間を電気的に接続できるように介在させられることにより、バンプ電極−導電粒子−実装基板側電極なるルートで電気的接続が確保されるのである。
【0010】
かかる介在させた導電性粒子を仲立ちとして両電極間の電気的接続を確保するためには、両電極間における導電性粒子の高密度化が求められる。
【0011】
しかし、実装に際して、バンプ電極の実装基板側電極への圧着に不均一が発生すると、その加圧不足部分では、両電極間に介在する導電粒子の密度は正常加圧部分に比べて相対的に粗に成りがちである。
【0012】
かかる加圧不足部分では、両電極間に介在する導電性粒子が、正常加圧部分に比べて、両電極間で圧縮される割合が少なく、導電性粒子同士、あるいは電極と導電性粒子との接触度合いが比較的に弱かったり、あるいは非接触状態となる場合もある。かかる場合には、その部分における電気抵抗が高くなり、両電極間の良好な十分な導通性が確保されないこととなる。
【0013】
例えば、両電極間に電位差をかければ確かに電流は流れるものの、十分な電流は当初から流れず、十分に電圧が上がるまでに時間がかかる等の異常が発生する。電圧の切替えを円滑に行うことで、液晶状態を変化させてその表示を行う液晶表示のLCDドライバにおいては、液晶表示の鮮明性が確保できなくなる重大な障害となる。
【0014】
また、かかる異常は、完成したLCDドライバ等の半導体装置の完成品検査においても、所定位置に検査用のプローブを当てて、その導通を検査するに際して、反応が遅かったり、あるいは全く導通が示されず、プローブを多少動かして接触位置を変えると導通が俄に確認される等の検査時の問題現象の原因の一つともなる。
【0015】
かかる導通異常が発生する大きな原因の一つは、バンプ電極の表面形状によるものである。バンプ電極は、半導体装置に設けられた配線電極上のパッシベーション膜をエッチング等で除去し、その上にメッキ等の手段で電極形成を行って作成される。
【0016】
そのため、このようにして形成されたバンプ電極では、電極表面に、パッシベーション膜をエッチングして配線電極を露出させた際のパッシベーション膜面と配線電極面との段差を反映した窪みが形成されこととなる。
【0017】
かかる構成のバンプ電極を有する半導体装置をフリップチップ方式でフェイスダウン実装すると、窪みを有した電極表面が、実装基板側電極対面されることとなり、両電極間に介在させる異方性導電膜中の導電性粒子への押圧力が、窪み部と、窪んでいないその周辺部とでは微妙に異なることとなる。すなわち、実装時に加圧不均一が発生するのである。
【0018】
そこで、かかる対策として、パッシベーション膜を薄膜化することで、パッシベーション膜面と配線電極面との段差を小さく抑える手段が提案されている。しかし、パッシベーション膜を薄くすることは、逆に、その絶縁性を低下させることにも繋がり、かかるパッシベーション膜の薄膜化を行わずにバンプ電極と実装基板側の電極との導通性を確保する技術の開発が望まれている。
【0019】
本発明の目的は、LCDドライバなどの半導体装置側のバンプ電極と、バンプ電極と相対して接続される実装基板側電極等の相手側電極との導通性を十分に確保できるようにすることにある。
【0020】
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。
【0021】
【課題を解決するための手段】
本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。
【0022】
本発明は、半導体装置のバンプ電極の電極表面に、半導体装置の表面に設けた配線電極に導通可能な複数の凹部を設け、バンプ電極の電極表面側の凹部開口側面積を凹部底面側面積より大きく構成することにより、導電性粒子を含む異方性導電膜を介してのバンプ電極と実装基板側電極との導通性の確保を良好に行えるようにするものである。
【0023】
【発明の実施の形態】
以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明を省略する。
【0024】
図1(a)は本発明の一実施の形態の半導体装置のバンプ電極構造を模式的に示す断面図であり、(b)は(a)に示す構成のバンプ電極を使用して実装基板側に実装した状態を模式的に示す断面図である。
【0025】
図1(a)に示すように、半導体装置10の表面には、Al等により形成された配線電極11が設けられている。配線電極11上には、パッシベーション膜12が設けられている。
【0026】
配線電極11上には、バンプ電極14の形成部分に対応して、パッシベーション膜12が凸状に断続的に設けられ、凹凸部が形成されている。凸部12aは断面錐状に形成され、凹部12bはかかる凸部12aの錐状に対応して断面が逆錐状に形成されている。このように複数の凸部12a、凹部12bが構成された凹凸部上に、バンプ下地金属層13を介して、Au等で形成されたバンプ電極14が設けられている。
【0027】
このように形成されたバンプ電極14の電極表面には、配線電極11上に設けられたパッシベーション膜12からなる上記凹凸部に対応して、凸部14a(14)、凹部14b(14)がそれぞれ複数形成されている。
【0028】
また、凸部12a、凹部12bは、図1に示すようにそれぞれ断面が錐状、逆錐状に形成されているため、これに対応して形成されるバンプ電極14の凸部14a、凹部14bも、それぞれ錐状、逆錐状に形成されることとなる。図1では、分かりやすいように、バンプ電極14の電極表面側の凸部14a、凹部14bの錐状、逆錐状の凹凸形状を、凸部12a、凹部12bより誇張して示している。
【0029】
尚、上記錐状とは、例えば、円錐、あるいは三角錐、四角錐、五角錐などの角錐形状を意味している。
【0030】
バンプ電極14をメッキ成長により形成する場合には、凸部14a、凹部14bの凹凸形状は、凸部12a、凹部12bの場合よりも小さくなり、マクロ的には凹凸部は平坦と見做せる状態になっている。
【0031】
このようにして形成された凹部14bでは、図1(a)に示すように、電極表面側の凹部開口側面積S1は、凹部底面側面積S2(図中では、凹部14bの谷の底の面積)より大きく形成されることとなる。
【0032】
凹部14bの電極表面側の差し渡し寸法は、図1(b)に示すように、異方性導電膜15を介在させて実装基板16側の電極16aに実装する際に、異方性導電膜15に含有される導電性粒子17が、凹部14b内に完全に入り込むことがないように設定しておけばよい。すなわち、凹部14bの差し渡し寸法を、例えば、導電性粒子17の平均粒径以下となるように設定しておけばよい。
【0033】
このように設定しておけば、図1(b)に示すように、図1(a)に示す構成の半導体装置10のバンプ電極14側を、実装基板16の電極16a側に加熱圧着してフェイスダウン実装する場合に、導電性粒子17が凹部14b内に完全に入り込むことはなく、バンプ電極14と実装基板16の電極16aとの間に導電性粒子17を確実に介在させて、バンプ電極14と導電性粒子17、導電性粒子17と電極16aとの接触性を確保することができる。そのため、バンプ電極14と実装基板16側の電極16aとの導通性は十分に確保されることとなる。
【0034】
前記説明では、図1(a)に示すように、バンプ電極14の電極表面に形成される凹凸部の形状を決める配線電極11上に設けるパッシベーション膜12の凸部12aの形状を錐状に形成した場合について説明したが、凹部14bが、電極表面側の凹部開口側面積S1が凹部底面側面積S2より大きくすることができれば、凸部12aの形状はどのようなものであっても構わない。例えば、凸部12aを断面台形状に形成することもできる。
【0035】
一方、図2(a)に示すように、半導体装置10の配線電極11上に、バンプ電極14を設けるに際して、配線電極11上に、図1(a)に示す場合とは異なり、パッシベーション膜12の凸部12a、凹部12bから構成される凹凸部を設けない場合には、電極表面側に、パッシベーション膜12と配線電極11との間に形成される段差部18が反映された大きな凹部19が形成されることとなる。
【0036】
図2(a)に示す凹部19は、図1(a)に示す凹部14bより格段に大きい。すなわち、図1(a)に示す構成は、大きな凹部19に相当する大きな窪み内に、小さな凸部14a、凹部14bからなる凹凸部を多数形成して、全体として、一つの大きな窪みを設けることなく、電極表面を擬似的に面一に平坦化させる構成と言える。
【0037】
図2(b)には、かかる構成のバンプ電極14を使用して、実装基板16側の電極16aとの間に、異方性導電膜15を介在させてフェイスダウン実装した場合を示す。凹部19に対応する部分では、図1(a)と同様にして加熱圧着しても、凹部19が元々大きな窪みに形成されているため、実装基板16の電極16aとの間に介在される異方性導電膜15内の導電性粒子17を高密度に介在させることができない場合が生ずる。図中、楕円で囲んだ部分に示すように、導電性粒子17との接触部分が少なくなる。
【0038】
図2(b)には、例示として、凹部19と導電性粒子17とが離間している状況を示した。すなわち、例えば、図2(b)に図示するように、バンプ電極14の電極表面の大きな範囲を占める凹部19と、実装基板16側の電極16aとの導通性を介在する導電性粒子17の凹部19、電極16aとの接触性が悪くなる。凹部19と電極16aとの間では、凹部19の段差部18に対応する高い周辺部19aと電極16aとの間とは異なり、導電性粒子17の押さえ込み力が弱く成りがちである。
【0039】
そのため、バンプ電極14と実装基板16側の電極16aとの間の導通性が十分に確保されない場合が発生する。また、導通性は確保されていても、前述の如く、例えば、両電極間に電位差をかければ確かに電流は流れるものの、十分な電流は当初からは流れず、十分に電圧が上がるまでに時間がかかる等の異常が発生する。
【0040】
かかる障害は、例えば、電圧の切替えを円滑に行うことで、液晶状態を変化させてその表示を行う液晶表示のLCDドライバにおいては、極めて致命的な障害であり、液晶表示の画面切替えなどの鮮明性等の確保が果たせなくなる。
【0041】
しかし、図1(a)に示す構成のバンプ電極14を有する本発明に係る半導体装置10であれば、図2(a)の構成のバンプ電極14を有する場合とは異なり、バンプ電極14の電極表面側が平坦化されているため、実装基板16側の電極16aとの間に平均して導電性粒子17を挟み込むことができ、平均した導通性を十分に確保することができる。
【0042】
また、図1(a)に示す構成では、バンプ電極14の表面側に導電性粒子の平均粒径より小さい間隔で断続的に設けられた多数の凸部14aの頂点により、マクロ的には頂点が実質的に連続した状態と見做されて擬似的に平坦化が成されているため、上記問題点の解決策として提案されている段差部18を解消するためのパッシベーション膜12の薄膜化を行わなくても済む。パッシベーション膜12の無理な薄膜化は、パッシベーション膜12に基づく絶縁性を脆弱化する虞れがあるが、かかる危険を未然に回避することができる。
【0043】
次に、上記説明の構造のバンプ電極14を有する半導体装置10の製造方法について、半導体装置10を、図3に示すように、例えば、液晶表示装置の電圧切替え制御として使用するLCDドライバ10a(10)に形成した場合を例に挙げて説明する。
【0044】
図3では、液晶表示機構の互いに交差する方向に設けられるゲート線群と、ドレイン線群との電圧切替え制御を行う細長矩形形状に形成されたLCDドライバ10aのバンプ電極14の配置状況を平面図で示す。LCDドライバ10aには、図3に示すように、液晶表示画面の画素数に対応したゲート線群、ドレイン線群を構成する多数の線数に対応したバンプ電極14が多数設けられている。バンプ電極14は、LCDドライバ10aの矩形面の長辺側、短辺側の周縁に沿って多数設けられている。
【0045】
上記構成のLCDドライバ10aに構成される半導体装置10は、図4〜7に示す各ステップを経ることにより、前記説明の構造を有するバンプ電極14が設けられる。
【0046】
図4(a)には、ウエハ31上に既存の方法で液晶表示装置用の駆動回路素子と、バンプ電極14の形成位置にAlからなる配線電極11が形成され、その上にパッシベーション膜12が形成されている状況を、要部断面図として示す。
【0047】
図4(a)に示す構成において、そのパッシベーション膜12上に、レジスト32を塗布する。塗布したレジスト32の配線電極11に対応する範囲に、ステッパ露光によりマスクパターンを露光させ、露光後の現像によりマスクパターンをレジスト32上にパターニングする。図4(b)には、レジスト32上にパターニングされた状態を断面図として示す。
【0048】
レジスト32上に形成するパターンは、種々の構成が考えられるが、例えば、図5(a)に示すように、中央の開口した凹部41を中心として、その周囲に同心状に、枠状に凹部42、43、44を設ける構成とすることができる。
【0049】
あるいは、図5(b)に示すように、略角形に形成した凹部45をマトリックス状に配置しても構わない。さらに、図5(c)に示すように、矩形に形成した凹部46を列状に設けるようにしても構わない。さらには、図5(d)に示すように、凹部47を円環状に、形成しても一向に構わない。かかる円環状に形成した凹部47を、同心円状に複数設けても構わない。
【0050】
図4(c)に示すように、所定のパターニングが施されたレジスト32をマスクとして、等方性を強めたエッチングで、パッシベーション膜12のパターニングを行う。
【0051】
かかるエッチングとしては、例えば、等方性のドライエッチングを使用することができる。通常、等方性のドライエッチングでは、圧力を0.1〜1.0 Torr(1.33322×10〜1.33322×102 Pa)に設定し、ガス種としてCFに、8%のOを加えたものを使用して行うのが一般的であるが、本実施の形態では、かかる通常の等方性のエッチング条件とは異なり、さらに等方性を強めたエッチング条件を採用した。
【0052】
すなわち、上記圧力下、CFに、Oを20%加えることで等方性を強めた。ガス種としては、SFを使用してもよい。
【0053】
このようにして、等方性を強めたドライエッチングによりパッシベーション膜12をパターニングし、その後マスクとして使用したレジスト32を除去する。このようにして、レジスト32を除去した状態を、図4(d)に断面図として示す。
【0054】
図4(d)に示すように、配線電極11上には、パッシベーション膜12からなる断面錐状に形成された凸部12aが断続的に複数残され、併せて凹部12bが形成されている。すなわち、凹凸部が配線電極11上に設けられることとなる。
【0055】
このようにして凹凸部を配線電極11上に設けた状態で、図6(a)に示すように、バンプ下地金属層13を所定厚さに堆積する。例えば、Cr層、Cu層、Au層を下層から順次スパッタリングにより堆積させて積層させればよい。
【0056】
このようにしてバンプ下地金属層13を所定層厚に堆積させた後、所定層厚にレジスト33の塗布を行う。レジスト塗布後、配線電極11に対応して、ステッパ露光によりマスクパターンを露光させ、露光後の現像によりバンプ電極形成用のマスクパターンをレジスト33上にパターニングする。図6(b)には、かかる状態を断面図で示した。
【0057】
その後、パターニングされたレジスト33を利用して、図6(c)に示すように、電解メッキによりAuのバンプ電極14を形成する。バンプ電極14の形成後は、図7(a)に示すように、バンプ電極形成用のレジスト33を除去する。さらに、不要部分のバンプ下地金属層13を除去して、図7(b)に示すように、本発明に係る構成のバンプ電極14を有する半導体装置10としてのLCDドライバ10aを製造する。
【0058】
上記一連のステップにより形成されたバンプ電極14は、図7(b)に示すように、配線電極11上にパッシベーション膜12の凸部12aを複数断続的に残すことにより凹凸部が形成され、形成されたこの凹凸部を反映した状態がバンプ電極14の電極表面の凸部14a、凹部14bからなる凹凸部として形成されることとなる。
【0059】
バンプ電極14の電極表面に形成される凹凸部は、図6(b)の状態から縦方向に金メッキを成長させて形成されるが、金メッキの成長は、縦方向ばかりではなく横方向にも成長するため、縦方向と横方向とのメッキ成長が相まって、電極表面の凹凸部は配線電極11上のパッシベーション膜12により形成される凹凸部に比べて凹凸の高さが低い緩やかな凹凸形状となっている。
【0060】
特に、かかるバンプ電極14の形成に際しては、図4(d)に示すように、配線電極11上に形成する凹凸部では、パッシベーション膜12の凸部12aに合わせて形成される凹部12bは、パッシベーション膜12の表面側の開口面積S3が、配線電極11側の開口面積S4より大きくなる孔部に形成されている。
【0061】
そのため、かかる孔部を、例えば、凸部の側面が垂直に切り立った直状形状、すなわち柱状に形成する場合に比べて、凸部12aの側面はテーパに形成されているため、スパッタリングによるバンプ下地金属層13の堆積を凹部12b内に平均的に行うことができる。
【0062】
また、上記の如く側面が直状に伸びた凸部により矩形波形のような凹凸形状に形成する凹凸部の場合には、パッシベーション膜12の表面側の開口面積S3と、配線電極11側の開口面積S4とは略同じ大きさの柱状の孔部が形成されることとなる。この状態で、バンプ下地金属層13を堆積した場合には、開口面積S3が小さくなり、その後のバンプ電極14形成用の金メッキにおいて、十分にメッキ液が孔部の底まで侵入しにくく、孔部底面側にボイドが閉じ込められた状態が生起される可能性が高い。
【0063】
しかし、本発明では、開口面積S3は開口面積S4より大きく形成されているためメッキ液の流れ込みを円滑に行うことができ、導通に際しての抵抗となるボイドの発生を未然に防止することができる。そのため、形成されたバンプ電極14の導通性に関しての信頼性を高めることができる。
【0064】
また、凹部12bは、図4(d)に示すように、断面略逆台形状に形成されており、さらに、その後のステップでバンプ下地金属層13が堆積されで、凸部13a、凹部13bからなる凹凸部が形成されることとなる。バンプ下地金属層13堆積後の凹部13bは、メッキにより凹部12bよりも凹部空間が埋められた状態になっている。
【0065】
かかる凹部空間に関しては、前記の如く、側面が直上に伸びた凸部により矩形波形のような凹凸形状に形成する場合には、パッシベーション膜12の表面側の開口面積S3と、配線電極11側の開口面積S4とは略同じ大きさの柱状の孔部に形成されることとなるため、例えば、開口面積S3が同一と仮定した場合には、図6(a)に示す場合の凹部空間の方が小さく、その後の金メッキによる凹部空間の埋め込みが起き易いと言える。
【0066】
すなわち、凹部13bのメッキ成長による埋め込みが起き易い本発明に係る構成の方が、側面が直上に伸びた凸部により矩形波形のような凹凸形状に形成する場合に比べて、バンプ電極14の電極表面をより平坦化し易いと言える。
【0067】
このように、本発明は、敢えて、バンプ電極14を形成するに際して、配線電極11上のパッシベーション膜12に、パッシベーション膜12の表面側の開口面積S3が配線電極側の開口面積S4より大きくなるように、前記配線電極11上に通じる孔部を複数形成しておくことにより、その後のメッキ成長によるバンプ電極の表面をより平坦化するようにしているのである。
【0068】
かかる平坦化が促進されているバンプ電極14を有するLCDドライバ10a(10)を使用すれば、図8に示すように、LCDドライバ10aのバンプ電極14と、実装基板16の電極16aに相当する液晶基板51の液晶側配線層51aとの間に、異方性導電膜15を介在させたフリップチップ方式の実装における導通性を十分に確保することができる。
【0069】
図8に模式的に示すように、バンプ電極14の電極表面に形成された凹凸部の凹部14bの差し渡し寸法は導電性粒子17の平均粒径より小さく形成され、前記の如く、平坦度が高く設定されている。そのため、図2(b)に示す構成のバンプ電極構造とは異なり、図8に示す構成のバンプ電極構造の方が、電極表面の表面全体に亙って、液晶側配線層51aとの間に介在させる異方性導電膜15に含まれる導電性粒子17を、平均して高密度に介在させて押しつぶすようにして挟持することとができる。
【0070】
そのため、バンプ電極14−導電性粒子17−液晶側配線層51aからなる導通ルートを確実にして、その導通性を十分に確保することができる。
【0071】
図9(a)、(b)には、図4(c)、(d)に相当するステップで、配線電極11上に残すパッシベーション膜12の凸部12aの形状を断面台形状に設定した場合におけるバンプ電極14の平面形状を例示した。断面台形状の凸部12aの上底部分に対応して形成された部分を、図中の凸部14aで示した。図9(a)、(b)は、共に同心状に凹部14bが形成されている場合である。
【0072】
図9(a)は、矩形のバンプ電極14形状に合わせて同心状に、(b)は正方形のバンプ電極14の形状に合わせて同心状にそれぞれ形成した場合を示す。同心状に形成することにより、凹部14bの配線電極11上に通じる導通面積を列状に構成する場合よりも多くすることができる。
【0073】
勿論、凹部14bの配置は、同心状以外にも、図5に示すように、マトリックス状、あるいは列状に形成しても構わない。また、上記説明では、凹部を平面直線状に形成した場合を示しているが、波形に蛇行させるように形成して、導通面積を多くするようにしても構わない。
【0074】
以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。
【0075】
例えば、上記説明では、LCDドライバを例に挙げて説明したが、本発明は、LCDドライバ以外でも、異方性導電膜を介在させてフェイスダウン実装によりバンプ電極を実装基板側電極等の相手側電極と電気的に接続させる構成の半導体装置に適用することができることは言うまでもない。
【0076】
【発明の効果】
本願によって開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば、以下の通りである。
【0077】
すなわち、バンプ電極の表面の平坦度を高めて、バンプ電極と相手側電極との導通性を良好にすることができる。
【図面の簡単な説明】
【図1】(a)は本発明の一実施の形態の半導体装置のバンプ電極構造を模式的に示す断面図であり、(b)は(a)に示す構成のバンプ電極を使用して実装基板側に実装した状態を模式的に示す断面図である。
【図2】(a)は、図1に示す構成とは異なり、配線電極上に凹凸部を設けないで形成したバンプ電極構造を模式的に示す断面図であり、(b)は(a)に示す構成のバンプ電極を使用して実装基板側に実装した状態を示す断面図である。
【図3】LCDドライバに構成した半導体装置におけるバンプ電極の配置状況を示す平面図である。
【図4】(a)〜(d)は、本発明の一実施の形態の半導体装置の製造方法の一連のステップ例を示す断面説明図である。
【図5】(a)〜(d)は、パッシベーション膜のパターニング例を示す平面図である。
【図6】(a)〜(c)は、本発明の一実施の形態の半導体装置の製造方法の一連のステップ例を示す断面説明図である。
【図7】(a)、(b)は、本発明の半導体装置の製造方法の一連のステップによりバンプ電極が形成される状況を示す断面説明図である。
【図8】本発明に係る構成のバンプ電極を設けた半導体装置のLCDドライバを、液晶基板側に実装した状態の一例を示す要部断面説明図である。
【図9】(a)、(b)は、バンプ電極表面の凹部を同心状に形成した場合を例示する平面図である。
【符号の説明】
10  半導体装置
10a LCDドライバ
11  配線電極
12  パッシベーション膜
12a 凸部
12b 凹部
13  バンプ下地金属層
13a 凸部
13b 凹部
14  バンプ電極
14a 凹部
14b 凸部
15  異方性導電膜
16  実装基板
16a 電極
17  導電性粒子
18  段差
19  凹部
19a 周辺部
31  ウエハ
32  レジスト
33  レジスト
41  凹部
42  凹部
43  凹部
44  凹部
45  凹部
46  凹部
51  液晶基板
51a 液晶側配線層
S1  凹部開口側面積
S2  凹部底面側面積
S3  開口面積
S4  開口面積
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing technology thereof, and is particularly effective when applied to a semiconductor device mounted by a flip chip method using bump electrodes.
[0002]
[Prior art]
The technology described below has been studied by the inventor when researching and completing the present invention, and the outline thereof is as follows.
[0003]
2. Description of the Related Art In semiconductor devices such as semiconductor chips, there is a strong demand for miniaturization, high-density mounting, and the like. In response to such technical demands, a so-called flip-chip mounting technique of aligning a semiconductor chip provided with bump electrodes on a mounting board side face down and connecting the bump electrodes and the mounting board side electrodes has been developed. Widely adopted.
[0004]
As the mounting using the flip-chip method, for example, mounting methods such as a chip-on-glass (COG) method, a chip-on-film (COF) method, and a chip-on-board (COB) method are known.
[0005]
In recent years, even in the field of liquid crystal technology in which higher definition and an increase in the number of pixels are required, for example, the above method is actively adopted as a mounting method of an LCD driver for controlling voltage switching related to liquid crystal display. .
[0006]
[Problems to be solved by the invention]
However, the present inventor has found that the above-described technology has the following problems.
[0007]
The flip-chip mounting is generally performed by interposing an anisotropic conductive film made of an anisotropic conductive resin or the like between a bump electrode on the semiconductor device side and an electrode on the mounting substrate. This is performed by heat-pressing the bump electrode to the mounting substrate side electrode.
[0008]
The electrical connection between the bump electrode and the mounting substrate-side electrode during such mounting is ensured by the conductive particles contained in the anisotropic conductive film being interposed between the bump electrode and the mounting substrate-side electrode. It will be.
[0009]
In other words, the conductive particles contained in the anisotropic conductive film are interposed between the bump electrode and the mounting substrate side electrode by the heat compression bonding so that the two electrodes can be electrically connected to each other. As a result, electrical connection is ensured along the route of the bump electrode, the conductive particles, and the mounting substrate side electrode.
[0010]
In order to secure electrical connection between the two electrodes by using the interposed conductive particles as intermediates, it is required to increase the density of the conductive particles between the two electrodes.
[0011]
However, during the mounting, if unevenness occurs in the pressure bonding of the bump electrode to the mounting board side electrode, the density of the conductive particles interposed between the two electrodes is relatively lower in the insufficiently pressed portion than in the normally pressed portion. It tends to be coarse.
[0012]
In such an underpressurized portion, the conductive particles interposed between the two electrodes are less compressed between the two electrodes as compared to the normal pressurized portion, and the conductive particles between the conductive particles, or between the electrode and the conductive particles, In some cases, the degree of contact is relatively weak, or a non-contact state occurs. In such a case, the electrical resistance at that portion increases, and good and sufficient conductivity between the two electrodes cannot be secured.
[0013]
For example, if a potential difference is applied between the two electrodes, a current certainly flows, but a sufficient current does not flow from the beginning, and an abnormality such as a long time is required until the voltage is sufficiently increased. Smooth switching of the voltage causes a serious obstacle to the clarity of the liquid crystal display in a liquid crystal display LCD driver that changes the liquid crystal state and performs the display.
[0014]
In addition, such an abnormality is caused in a completed product inspection of a semiconductor device such as a completed LCD driver or the like, when a test probe is applied to a predetermined position and its conduction is inspected, the reaction is slow or no conduction is shown. If the contact position is changed by slightly moving the probe, this may be one of the causes of a problem at the time of inspection such that conduction is suddenly confirmed.
[0015]
One of the major causes of such conduction abnormality is due to the surface shape of the bump electrode. A bump electrode is formed by removing a passivation film on a wiring electrode provided in a semiconductor device by etching or the like, and forming an electrode thereon by plating or the like.
[0016]
Therefore, in the bump electrode formed in this way, a depression is formed on the electrode surface that reflects the step between the passivation film surface and the wiring electrode surface when the passivation film is etched to expose the wiring electrode. Become.
[0017]
When a semiconductor device having a bump electrode having such a configuration is mounted face-down by a flip-chip method, the electrode surface having a dent faces the mounting substrate-side electrode, and the anisotropic conductive film interposed between the two electrodes. The pressing force on the conductive particles is slightly different between the concave portion and the peripheral portion that is not concave. That is, pressure unevenness occurs during mounting.
[0018]
Therefore, as a countermeasure, a means has been proposed to reduce the step between the passivation film surface and the wiring electrode surface by reducing the thickness of the passivation film. However, making the passivation film thinner, on the contrary, also lowers its insulating property, and a technique for securing the conductivity between the bump electrode and the electrode on the mounting board side without making the passivation film thinner. The development of is desired.
[0019]
An object of the present invention is to ensure sufficient conductivity between a bump electrode on a semiconductor device such as an LCD driver and a counter electrode such as a mounting board electrode connected to the bump electrode. is there.
[0020]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0021]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0022]
The present invention provides a plurality of recesses on the electrode surface of a bump electrode of a semiconductor device, the recesses being capable of conducting to a wiring electrode provided on the surface of the semiconductor device. By making the structure large, the conductivity between the bump electrode and the mounting substrate-side electrode can be satisfactorily ensured via the anisotropic conductive film containing the conductive particles.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.
[0024]
FIG. 1A is a cross-sectional view schematically showing a bump electrode structure of a semiconductor device according to an embodiment of the present invention, and FIG. 1B is a sectional view showing a mounting substrate side using a bump electrode having the configuration shown in FIG. FIG. 4 is a cross-sectional view schematically showing a state where the device is mounted on the helmet.
[0025]
As shown in FIG. 1A, a wiring electrode 11 made of Al or the like is provided on the surface of the semiconductor device 10. A passivation film 12 is provided on the wiring electrode 11.
[0026]
On the wiring electrode 11, a passivation film 12 is provided intermittently in a convex shape corresponding to a portion where the bump electrode 14 is formed, and an uneven portion is formed. The convex portion 12a is formed in a conical section, and the concave portion 12b is formed in an inverted conical shape corresponding to the conical shape of the convex portion 12a. The bump electrode 14 made of Au or the like is provided on the uneven portion having the plurality of convex portions 12a and concave portions 12b with the bump base metal layer 13 interposed therebetween.
[0027]
On the electrode surface of the bump electrode 14 thus formed, a convex portion 14 a (14) and a concave portion 14 b (14) are respectively formed corresponding to the above-mentioned concave and convex portions formed of the passivation film 12 provided on the wiring electrode 11. A plurality is formed.
[0028]
Also, as shown in FIG. 1, the convex portion 12a and the concave portion 12b are formed in a conical or inverted conical shape, respectively, so that the convex portion 14a and the concave portion 14b of the bump electrode 14 are formed correspondingly. Are also formed in a conical shape and an inverted conical shape, respectively. In FIG. 1, for the sake of simplicity, the convex and concave portions 14 a and the concave portions 14 b on the electrode surface side of the bump electrode 14 are exaggerated from the convex portions 12 a and the concave portions 12 b.
[0029]
The pyramid means, for example, a cone or a pyramid such as a triangular pyramid, a quadrangular pyramid, or a pentagonal pyramid.
[0030]
When the bump electrode 14 is formed by plating growth, the convex and concave portions 14a and the concave portions 14b have smaller irregularities than those of the convex portions 12a and the concave portions 12b, and the concave and convex portions can be regarded as flat macroscopically. It has become.
[0031]
In the thus formed recess 14b, as shown in FIG. 1A, the recess opening side area S1 on the electrode surface side is the recess bottom surface area S2 (in the figure, the area of the bottom of the valley of the recess 14b is shown). ) Is formed larger.
[0032]
As shown in FIG. 1B, when the concave portion 14b is mounted on the electrode 16a on the mounting substrate 16 with the anisotropic conductive film 15 interposed therebetween, as shown in FIG. The conductive particles 17 may be set so as not to completely enter the recess 14b. That is, the width of the recess 14b may be set to be equal to or smaller than the average particle diameter of the conductive particles 17, for example.
[0033]
With this setting, as shown in FIG. 1B, the bump electrode 14 side of the semiconductor device 10 having the configuration shown in FIG. In the case of face-down mounting, the conductive particles 17 do not completely enter the recesses 14b, and the conductive particles 17 are reliably interposed between the bump electrodes 14 and the electrodes 16a of the mounting substrate 16, so that the bump electrodes 14 and the conductive particles 17, and the contact between the conductive particles 17 and the electrode 16 a can be ensured. Therefore, the conductivity between the bump electrode 14 and the electrode 16a on the mounting substrate 16 side is sufficiently ensured.
[0034]
In the above description, as shown in FIG. 1A, the shape of the convex portion 12a of the passivation film 12 provided on the wiring electrode 11 which determines the shape of the uneven portion formed on the electrode surface of the bump electrode 14 is formed in a conical shape. As described above, the concave portion 14b may have any shape as long as the concave portion opening side area S1 on the electrode surface side can be made larger than the concave portion bottom surface side area S2. For example, the convex portion 12a may be formed in a trapezoidal cross section.
[0035]
On the other hand, as shown in FIG. 2A, when the bump electrode 14 is provided on the wiring electrode 11 of the semiconductor device 10, unlike the case shown in FIG. In the case where the uneven portion composed of the convex portion 12a and the concave portion 12b is not provided, a large concave portion 19 reflecting the step portion 18 formed between the passivation film 12 and the wiring electrode 11 is provided on the electrode surface side. Will be formed.
[0036]
The recess 19 shown in FIG. 2A is much larger than the recess 14b shown in FIG. That is, in the configuration shown in FIG. 1A, a large depression corresponding to the large depression 19 is provided with a large number of depressions and projections composed of the small projections 14a and the depressions 14b, and one large depression is provided as a whole. In other words, it can be said that the electrode surface is quasi-planarly flattened.
[0037]
FIG. 2B shows a case where the bump electrodes 14 having such a configuration are mounted face-down with an anisotropic conductive film 15 interposed between the bump electrodes 14 and the electrodes 16a on the mounting substrate 16 side. In the portion corresponding to the concave portion 19, the concave portion 19 is originally formed in a large concave portion even when the pressure bonding is performed in the same manner as in FIG. In some cases, the conductive particles 17 in the anisotropic conductive film 15 cannot be interposed at high density. In the figure, as shown by the portion surrounded by the ellipse, the contact portion with the conductive particles 17 is reduced.
[0038]
FIG. 2B shows, as an example, a situation in which the concave portion 19 and the conductive particles 17 are separated from each other. That is, for example, as shown in FIG. 2B, the concave portion 19 occupying a large area of the electrode surface of the bump electrode 14 and the concave portion of the conductive particle 17 interposed between the concave portion 19 and the electrode 16a on the mounting substrate 16 side. 19. The contact with the electrode 16a is deteriorated. The pressing force of the conductive particles 17 tends to be weaker between the concave portion 19 and the electrode 16a than between the high peripheral portion 19a corresponding to the step 18 of the concave portion 19 and the electrode 16a.
[0039]
For this reason, there may be a case where the conductivity between the bump electrode 14 and the electrode 16a on the mounting board 16 side is not sufficiently ensured. Also, even if conductivity is ensured, as described above, for example, if a potential difference is applied between the two electrodes, a current certainly flows, but a sufficient current does not flow from the beginning, and it takes time until the voltage is sufficiently increased. And abnormalities such as
[0040]
Such a failure is an extremely fatal failure in an LCD driver of a liquid crystal display that changes the liquid crystal state and performs the display by smoothly switching the voltage, for example. It will not be possible to ensure sex and the like.
[0041]
However, the semiconductor device 10 according to the present invention having the bump electrodes 14 having the configuration shown in FIG. 1A is different from the semiconductor device 10 having the bump electrodes 14 having the configuration shown in FIG. Since the surface side is flattened, the conductive particles 17 can be interposed between the electrode 16a on the mounting substrate 16 side on average and the average conductivity can be sufficiently ensured.
[0042]
In addition, in the configuration shown in FIG. 1A, the apex of a large number of protrusions 14a intermittently provided on the surface side of the bump electrode 14 at intervals smaller than the average particle size of the conductive particles causes the apex macroscopically. Is regarded as a substantially continuous state and is pseudo-flattened. Therefore, it is necessary to reduce the thickness of the passivation film 12 to eliminate the step 18 proposed as a solution to the above problem. You don't have to do it. Forcibly reducing the thickness of the passivation film 12 may weaken the insulation based on the passivation film 12, but such danger can be avoided.
[0043]
Next, in the method of manufacturing the semiconductor device 10 having the bump electrode 14 having the above-described structure, as shown in FIG. 3, for example, an LCD driver 10a (10 ) Will be described as an example.
[0044]
FIG. 3 is a plan view showing an arrangement state of bump electrodes 14 of an LCD driver 10a formed in a slender rectangular shape for controlling voltage switching between a gate line group provided in a direction intersecting with the liquid crystal display mechanism and a drain line group. Indicated by As shown in FIG. 3, the LCD driver 10a is provided with a large number of bump electrodes 14 corresponding to a large number of gate lines and drain lines corresponding to the number of pixels of the liquid crystal display screen. A large number of bump electrodes 14 are provided along the long sides and short sides of the rectangular surface of the LCD driver 10a.
[0045]
The semiconductor device 10 included in the LCD driver 10a having the above configuration is provided with the bump electrodes 14 having the above-described structure by performing the steps shown in FIGS.
[0046]
In FIG. 4A, a drive circuit element for a liquid crystal display device and a wiring electrode 11 made of Al are formed on a wafer 31 at a position where a bump electrode 14 is formed by an existing method, and a passivation film 12 is formed thereon. The formed state is shown as a cross-sectional view of a main part.
[0047]
In the configuration shown in FIG. 4A, a resist 32 is applied on the passivation film 12. A mask pattern is exposed by stepper exposure in a range corresponding to the wiring electrode 11 of the applied resist 32, and the mask pattern is patterned on the resist 32 by development after exposure. FIG. 4B is a sectional view showing a state where the resist 32 is patterned.
[0048]
Various patterns can be considered for the pattern formed on the resist 32. For example, as shown in FIG. 42, 43, and 44 may be provided.
[0049]
Alternatively, as shown in FIG. 5B, the recesses 45 formed in a substantially rectangular shape may be arranged in a matrix. Further, as shown in FIG. 5C, the concave portions 46 formed in a rectangular shape may be provided in a row. Further, as shown in FIG. 5D, the recess 47 may be formed in an annular shape. A plurality of such concave portions 47 formed in an annular shape may be provided concentrically.
[0050]
As shown in FIG. 4C, the passivation film 12 is patterned by etching with an enhanced isotropic property using the resist 32 that has been subjected to predetermined patterning as a mask.
[0051]
As such etching, for example, isotropic dry etching can be used. Usually, in the isotropic dry etching, the pressure is set to 0.1 to 1.0 Torr (1.3332 × 10 to 1.333322 × 10 3 Torr). 2 Pa) and the gas type is CF 4 And 8% O 2 In general, the etching is performed by using an etching condition in which isotropic etching is performed. However, in the present embodiment, an etching condition in which the isotropic property is further strengthened is adopted unlike the ordinary isotropic etching condition.
[0052]
That is, under the above pressure, CF 4 And O 2 Was added to increase the isotropy. As the gas type, SF 6 May be used.
[0053]
In this way, the passivation film 12 is patterned by dry etching with enhanced isotropy, and then the resist 32 used as a mask is removed. FIG. 4D is a sectional view showing a state in which the resist 32 has been removed in this manner.
[0054]
As shown in FIG. 4D, on the wiring electrode 11, a plurality of convex portions 12a formed of a passivation film 12 and having a conical cross section are intermittently left, and a concave portion 12b is also formed. That is, the uneven portion is provided on the wiring electrode 11.
[0055]
With the uneven portions provided on the wiring electrodes 11 in this way, as shown in FIG. 6A, a bump underlayer metal layer 13 is deposited to a predetermined thickness. For example, a Cr layer, a Cu layer, and an Au layer may be sequentially deposited and stacked from the lower layer by sputtering.
[0056]
After the bump base metal layer 13 is deposited to a predetermined thickness in this way, a resist 33 is applied to the predetermined thickness. After the application of the resist, the mask pattern is exposed by stepper exposure corresponding to the wiring electrode 11, and a mask pattern for forming a bump electrode is patterned on the resist 33 by development after the exposure. FIG. 6B is a sectional view showing such a state.
[0057]
Thereafter, using the patterned resist 33, as shown in FIG. 6C, the Au bump electrode 14 is formed by electrolytic plating. After the formation of the bump electrode 14, as shown in FIG. 7A, the resist 33 for forming the bump electrode is removed. Further, an unnecessary portion of the bump base metal layer 13 is removed, and as shown in FIG. 7B, an LCD driver 10a as the semiconductor device 10 having the bump electrodes 14 of the configuration according to the present invention is manufactured.
[0058]
As shown in FIG. 7B, the bump electrode 14 formed by the above-described series of steps is formed by forming a plurality of protrusions 12a of the passivation film 12 on the wiring electrode 11 intermittently, thereby forming an uneven portion. The state reflecting the irregularities thus formed is formed as the irregularities composed of the projections 14a and the depressions 14b on the electrode surface of the bump electrode 14.
[0059]
The uneven portion formed on the electrode surface of the bump electrode 14 is formed by growing gold plating in the vertical direction from the state of FIG. 6B, and the growth of the gold plating grows not only in the vertical direction but also in the horizontal direction. Therefore, the plating growth in the vertical direction and the horizontal direction is combined, and the uneven portion on the electrode surface has a gentle uneven shape in which the height of the unevenness is lower than the uneven portion formed by the passivation film 12 on the wiring electrode 11. ing.
[0060]
In particular, when the bump electrode 14 is formed, as shown in FIG. 4D, in the uneven portion formed on the wiring electrode 11, the concave portion 12b formed in accordance with the convex portion 12a of the passivation film 12 has a passivation. The opening area S3 on the front surface side of the film 12 is formed in a hole portion larger than the opening area S4 on the wiring electrode 11 side.
[0061]
For this reason, since the side surface of the convex portion 12a is formed in a tapered shape as compared with a case where such a hole portion is formed, for example, in a straight shape in which the side surface of the convex portion is stood vertically, that is, in a columnar shape, the bump base by sputtering is formed. The deposition of the metal layer 13 can be performed evenly in the recess 12b.
[0062]
Further, as described above, in the case of the uneven portion formed by the convex portion having the side surface extending straight, the opening area S3 on the front surface side of the passivation film 12 and the opening area on the wiring electrode 11 side are formed. A columnar hole having substantially the same size as the area S4 is formed. When the under bump metal layer 13 is deposited in this state, the opening area S3 becomes small, and in the subsequent gold plating for forming the bump electrode 14, the plating solution hardly penetrates to the bottom of the hole. There is a high possibility that a state in which the void is confined on the bottom side will occur.
[0063]
However, in the present invention, since the opening area S3 is formed to be larger than the opening area S4, the plating solution can flow smoothly, and the generation of a void which becomes a resistance at the time of conduction can be prevented. Therefore, the reliability of the formed bump electrode 14 in terms of conductivity can be improved.
[0064]
Further, as shown in FIG. 4D, the concave portion 12b is formed in a substantially inverted trapezoidal cross section, and further, a bump base metal layer 13 is deposited in a subsequent step, so that the convex portion 13a and the concave portion 13b As a result, an uneven portion is formed. The recess 13b after the deposition of the bump base metal layer 13 is in a state in which the recess space is more filled than the recess 12b by plating.
[0065]
As described above, when the concave space is formed in a concave and convex shape such as a rectangular waveform by the convex portion having the side surface extending directly upward, as described above, the opening area S3 on the front surface side of the passivation film 12 and the wiring area 11 side Since the opening area S4 is formed in a columnar hole having substantially the same size as the opening area S4, for example, when the opening area S3 is assumed to be the same, the recessed space shown in FIG. It can be said that the recess is easily buried by the subsequent gold plating.
[0066]
That is, in the configuration according to the present invention, in which the recess 13b is easily embedded by plating growth, the electrode of the bump electrode 14 is formed in an uneven shape such as a rectangular waveform by the convex portion having the side surface extending upward. It can be said that the surface is easier to flatten.
[0067]
As described above, according to the present invention, when the bump electrode 14 is formed, the opening area S3 on the surface side of the passivation film 12 on the passivation film 12 on the wiring electrode 11 is larger than the opening area S4 on the wiring electrode side. In addition, by forming a plurality of holes communicating with the wiring electrode 11, the surface of the bump electrode formed by the subsequent plating growth is further flattened.
[0068]
If the LCD driver 10a (10) having the bump electrode 14 whose flattening is promoted is used, as shown in FIG. 8, a liquid crystal corresponding to the bump electrode 14 of the LCD driver 10a and the electrode 16a of the mounting board 16 is used. Conductivity in flip-chip mounting in which the anisotropic conductive film 15 is interposed between the substrate 51 and the liquid crystal side wiring layer 51a can be sufficiently ensured.
[0069]
As schematically shown in FIG. 8, the width of the concave portion 14 b of the uneven portion formed on the electrode surface of the bump electrode 14 is formed smaller than the average particle size of the conductive particles 17, and as described above, the flatness is high. Is set. Therefore, unlike the bump electrode structure having the structure shown in FIG. 2B, the bump electrode structure having the structure shown in FIG. 8 has a larger distance between the bump electrode structure and the liquid crystal side wiring layer 51a over the entire surface of the electrode surface. The conductive particles 17 included in the anisotropic conductive film 15 to be interposed can be sandwiched so as to be crushed by being interposed at high density on average.
[0070]
Therefore, a conduction route including the bump electrode 14, the conductive particles 17, and the liquid crystal side wiring layer 51 a can be reliably established, and the conduction can be sufficiently ensured.
[0071]
FIGS. 9A and 9B show a case where the shape of the projection 12a of the passivation film 12 to be left on the wiring electrode 11 is set to a trapezoidal cross section in steps corresponding to FIGS. 4C and 4D. Of the bump electrode 14 in FIG. A portion formed corresponding to the upper bottom portion of the convex portion 12a having a trapezoidal cross section is indicated by a convex portion 14a in the figure. FIGS. 9A and 9B show a case where the concave portion 14b is formed concentrically.
[0072]
FIG. 9A shows the case where the bump electrode 14 is formed concentrically according to the shape of the rectangular bump electrode 14, and FIG. 9B shows the case where it is formed concentrically according to the shape of the square bump electrode 14. By forming the concentric shape, the conductive area of the concave portion 14b on the wiring electrode 11 can be made larger than in the case where the conductive area is formed in a row.
[0073]
Of course, the arrangement of the concave portions 14b may be formed in a matrix or a row as shown in FIG. Further, in the above description, the case where the concave portion is formed in a plane linear shape is shown, but the concave portion may be formed so as to meander in a waveform to increase the conductive area.
[0074]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.
[0075]
For example, in the above description, the LCD driver is described as an example. However, the present invention is not limited to the LCD driver, and the bump electrode may be mounted face-down by face-down mounting with an anisotropic conductive film interposed therebetween. It is needless to say that the present invention can be applied to a semiconductor device having a structure of being electrically connected to an electrode.
[0076]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0077]
That is, the flatness of the surface of the bump electrode can be increased, and the conductivity between the bump electrode and the partner electrode can be improved.
[Brief description of the drawings]
FIG. 1A is a cross-sectional view schematically showing a bump electrode structure of a semiconductor device according to an embodiment of the present invention, and FIG. 1B is mounted using a bump electrode having the configuration shown in FIG. It is sectional drawing which shows the state mounted on the board side typically.
FIG. 2A is a cross-sectional view schematically showing a bump electrode structure formed without providing an uneven portion on a wiring electrode, unlike the configuration shown in FIG. 1, and FIG. FIG. 4 is a cross-sectional view showing a state where the bump electrode having the configuration shown in FIG.
FIG. 3 is a plan view showing the arrangement of bump electrodes in a semiconductor device configured as an LCD driver.
FIGS. 4A to 4D are cross-sectional views illustrating a series of example steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIGS. 5A to 5D are plan views showing examples of patterning a passivation film.
FIGS. 6A to 6C are cross-sectional views illustrating a series of example steps of a method of manufacturing a semiconductor device according to an embodiment of the present invention.
FIGS. 7A and 7B are cross-sectional views showing a state in which a bump electrode is formed by a series of steps of a method of manufacturing a semiconductor device according to the present invention.
FIG. 8 is a cross-sectional view of an essential part showing an example of a state in which an LCD driver of a semiconductor device provided with bump electrodes having a configuration according to the present invention is mounted on a liquid crystal substrate side.
FIGS. 9A and 9B are plan views illustrating a case where concave portions on the surface of a bump electrode are formed concentrically.
[Explanation of symbols]
10 Semiconductor device
10a LCD driver
11 Wiring electrode
12 Passivation film
12a convex part
12b recess
13 Under bump metal layer
13a convex
13b recess
14 Bump electrode
14a recess
14b convex part
15 Anisotropic conductive film
16 Mounting board
16a electrode
17 conductive particles
18 steps
19 recess
19a Peripheral part
31 wafer
32 resist
33 Resist
41 recess
42 recess
43 recess
44 recess
45 recess
46 recess
51 LCD substrate
51a Liquid crystal side wiring layer
S1 recess opening side area
S2 Concave bottom surface area
S3 opening area
S4 opening area

Claims (5)

バンプ電極を有する半導体装置であって、
前記バンプ電極の電極表面には、前記半導体装置に設けた配線電極と導通する複数の凹部が設けられ、
前記凹部は、電極表面側の凹部開口側面積が凹部底面側面積より大きいことを特徴とする半導体装置。
A semiconductor device having a bump electrode,
On the electrode surface of the bump electrode, a plurality of recesses that are electrically connected to a wiring electrode provided on the semiconductor device are provided,
The semiconductor device is characterized in that the recess has an area on the electrode opening side on the electrode surface side larger than the area on the recess bottom side.
バンプ電極を有する半導体装置であって、
前記バンプ電極の電極表面には、前記半導体装置に設けた配線電極と導通する複数の凹部が、同心状に設けられ、
前記凹部は、電極表面側の凹部開口側面積が凹部底面側面積より大きいことを特徴とする半導体装置。
A semiconductor device having a bump electrode,
On the electrode surface of the bump electrode, a plurality of recesses that are electrically connected to wiring electrodes provided on the semiconductor device are provided concentrically,
The semiconductor device is characterized in that the recess has an area on the electrode opening side on the electrode surface side larger than the area on the recess bottom side.
実装基板側の電極に導電性粒子を含む異方性導電膜を介して導通可能に接続させるバンプ電極を有する半導体装置であって、
前記バンプ電極の電極表面には、凹凸部が設けられ、
前記凹凸部の凹部は、前記半導体装置に設けた配線電極に導通され、前記凹部の電極表面側の凹部開口側面積が、凹部底面側面積より大きく形成され、
前記電極表面側の凹部の差し渡し寸法が、前記導電性粒子の平均粒径より小さく設定されていることを特徴とする半導体装置。
A semiconductor device having a bump electrode that is conductively connected to an electrode on a mounting substrate side via an anisotropic conductive film containing conductive particles,
An uneven portion is provided on the electrode surface of the bump electrode,
The concave portion of the concave and convex portion is electrically connected to a wiring electrode provided on the semiconductor device, and the concave portion opening side area on the electrode surface side of the concave portion is formed to be larger than the concave portion bottom surface side area,
The semiconductor device according to claim 1, wherein a dimension of the concave portion on the electrode surface side is set smaller than an average particle size of the conductive particles.
バンプ電極を有する半導体装置の製造方法であって、
前記半導体装置の配線電極上に設けたパッシベーション膜に、パッシベーション膜表面側の開口面積が、配線電極側の開口面積より大きくなるように、前記配線電極上に通じる孔部を設ける工程と、
前記配線電極上に、前記孔部を介して前記配線電極側に導通可能にバンプ電極を形成する工程とを有することを特徴とする半導体装置の製造方法。
A method of manufacturing a semiconductor device having a bump electrode,
A step of providing a hole communicating with the wiring electrode so that an opening area on the surface of the passivation film is larger than an opening area on the wiring electrode side in the passivation film provided on the wiring electrode of the semiconductor device;
Forming a bump electrode on the wiring electrode so as to be conductive to the wiring electrode through the hole.
バンプ電極を有する半導体装置の製造方法であって、
前記半導体装置の配線電極上に設けたパッシベーション膜に、等方性エッチング処理を施して、前記配線電極上に、断面錐状または断面台形状のパッシベーション膜を断続的に残す工程と、
前記配線電極上に、断面錐状あるいは断面台形状のパッシベーション膜を断続的に残した状態で、前記配線電極上にバンプ下地金属層を設ける工程と、
前記バンプ下地金属層上に、メッキによりバンプ電極を形成する工程とを有することを特徴とする半導体装置の製造方法。
A method of manufacturing a semiconductor device having a bump electrode,
A step of subjecting the passivation film provided on the wiring electrode of the semiconductor device to an isotropic etching treatment so as to intermittently leave a passivation film having a conical or trapezoidal cross section on the wiring electrode;
A step of providing a bump base metal layer on the wiring electrode while the passivation film having a conical or trapezoidal cross section is intermittently left on the wiring electrode;
Forming a bump electrode by plating on the bump base metal layer.
JP2002165632A 2002-06-06 2002-06-06 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3970694B2 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007096315A (en) * 2005-09-27 2007-04-12 Agere Systems Inc Solder bump structure for flip chip semiconductor device and its manufacturing method
JP2009054833A (en) * 2007-08-28 2009-03-12 Seiko Epson Corp Ectronic device and its manufacturing emthod, electrooptical device, and electronic device
WO2013013204A3 (en) * 2011-07-21 2013-03-14 Qualcomm Incorporated Compliant interconnect pillars with orientation or geometry dependent on the position on a die or formed with a patterned structure between the pillar and a die pad for reduction of thermal stress
CN104112682A (en) * 2014-07-03 2014-10-22 上海交通大学 Solid-state ultrasonic bonding method based on nickel microneedle cones of the same structure

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007096315A (en) * 2005-09-27 2007-04-12 Agere Systems Inc Solder bump structure for flip chip semiconductor device and its manufacturing method
JP2009054833A (en) * 2007-08-28 2009-03-12 Seiko Epson Corp Ectronic device and its manufacturing emthod, electrooptical device, and electronic device
WO2013013204A3 (en) * 2011-07-21 2013-03-14 Qualcomm Incorporated Compliant interconnect pillars with orientation or geometry dependent on the position on a die or formed with a patterned structure between the pillar and a die pad for reduction of thermal stress
US9184144B2 (en) 2011-07-21 2015-11-10 Qualcomm Incorporated Interconnect pillars with directed compliance geometry
CN104112682A (en) * 2014-07-03 2014-10-22 上海交通大学 Solid-state ultrasonic bonding method based on nickel microneedle cones of the same structure

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