JPS6384050A - Integrated circuit - Google Patents

Abstract

PURPOSE:To attain supermulti-electrode constitution, and to inhibit a potential drop and noises, etc., by forming an external electrode for soldered joint at the central section of the main surface of an integrated circuit chip and an external electrode for connecting a TAB lead to a peripheral section. CONSTITUTION:External electrodes 4 for soldered joint are shaped at the central section of the main surface of an integrated circuit 1 and external electrodes 2, 3 for connecting TAB leads to a peripheral section. The electrical test of a wafer level is executed by bringing a testing probe into contact with the electrodes 2, 3 for the circuit 1 in the circuit 1. The electrodes disposed at the central section of the main surface of the circuit 1 can also be employed under the state of actual usage, thus inhibiting a potential drop and noises, etc. Accordingly, supermulti-electrode structure is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit, and more particularly to an integrated circuit having a large number of external electrodes.

[Conventional technology]

In conventional integrated circuits, multiple external electrodes are TAB (tap
e automated bondiB) system.

[Problem that the invention seeks to solve]

Since the TAB method is a method in which external electrodes are provided only at the peripheral edge of the main surface of the integrated circuit chip, in order to achieve a large number of electrodes without increasing the size of the integrated circuit, it is necessary to use TAB bumps and T A B.
It is necessary to make the lead finer. However, TAB
Since the bumps are formed by plating, it is difficult to miniaturize them. Furthermore, since the TAB lead is formed by etching a copper lead, it is not easy to miniaturize it.

[Means for solving problems]

The integrated circuit of the present invention includes an external electrode for solder connection provided at the center of the main surface of the integrated circuit chip, and an external electrode for TAB lead connection provided at the peripheral end of the main surface.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing a first embodiment of the present invention. On the main surface (upper part) of the integrated circuit (chip) 1, there is a T on the peripheral edge.
A power pin electrode 4 is provided as an external electrode for AB lead connection. The integrated circuit 1 fabricated in this way is TAB
FIG. 3 shows the device mounted on a tape, and FIG. 4 shows the device mounted on a chip carrier. The number of external electrodes of this integrated circuit 1 is the sum of the TAB lead connection external electrodes arranged in high density and the solder connection external electrode arranged in the center.

In this embodiment, the integrated circuit 1 is connected to the TAB of the integrated circuit 1 during wafer level electrical testing.
T
This can be carried out by placing a stylus on the electrode 7 placed on the polyimide film 6 of the AB tape (see FIG. 3). Furthermore, in actual use, the solder connection power pin electrode 4 disposed at the center of the main surface of the integrated circuit 1 can also be used, so potential drops, noise, etc. can be suppressed.

In addition, in FIG. 3 and FIG. 4, reference numeral 5 is TAB.
Lead, 8 is alumina substrate, 9 is cap with heat sink,
10 is an external terminal, and 11 is a solder.

FIG. 2 is a plan view showing a second embodiment of the present invention. On the main surface of the integrated circuit 1, a signal pin electrode 2 is arranged at the peripheral edge as an external electrode for connecting the TAB lead. A power pin electrode 4 is arranged in the center as an external electrode for solder connection. Mounting on the TAB tape and mounting on the chip carrier are the same as in the first embodiment described above.

The integrated circuit 1 in this embodiment can be electrically tested at a wafer level by touching the electrodes 2 and 4 disposed at the peripheral edges and the center of the integrated circuit 1 with test probes. Although it is not possible to sort the chips while they are mounted on the TAB tape, it is possible to sort them after they are mounted on the chip carrier.

〔Effect of the invention〕

As explained above, according to the present invention, a super multi-electrode configuration can be achieved by providing an external electrode for solder connection at the center of the main surface of an integrated circuit chip and an external electrode for TAB lead connection at the peripheral edge. .

[Brief explanation of the drawing]

Fig. 1 is a plan view showing a first embodiment of the present invention, Fig. 2 is a plan view showing a second embodiment of the invention, and Fig. 3 shows a state in which the integrated circuit of Fig. 1 is TAB mounted. The plan view shown in FIG. 4 is a vertical sectional view showing the state where the device is mounted on a chip carrier. DESCRIPTION OF SYMBOLS 1... Integrated circuit, 2... Signal bin electrode for TAB lead connection, 3... Power supply bin electrode for TAB lead connection, 4
...Power pin electrode for solder connection. (・Fig. 4

Claims (1)

[Claims] An integrated circuit comprising an external electrode for solder connection provided at the center of the main surface of the integrated circuit chip, and an external electrode for TAB lead connection provided at the peripheral edge of the main surface.