JPS6027139A - Method for inspecting connection between package and printed board - Google Patents

Abstract

PURPOSE:To execute the inspection smoothly and easily by overcoming difficulties due to the high density arrangement of connecting terminals by a method wherein resistance values including those of contact parts are discretely measured while probes are brought into contact with pads. CONSTITUTION:The structure is made as simple as possible by short-circuiting the inspection pads 12 in close contact on a chip substrate in a mass via resistors. On the other hand, the positions of connection inspection pads 14 on the back of the printed board 10 are arranged by diffusion by means of the inner layer wiring in the board, thus giving the special margin whereby the discrete probes 20 can be provided. Thereby, the short-circuit among bumps 8 is detected on the basis of the value of a current flowing through each of the probes 20.

Description

Detailed Description of the Invention fal Technical Field of the Invention The present invention relates to a method for inspecting the connection state between a package mounted with a semiconductor element and a printed circuit board. This invention relates to a connection inspection method when a chip carrier is mounted on a printed circuit board.

(b) Conventional technology and problems With the rapid development of electronic devices such as computers.

There has been an increasing demand for higher density and smaller packaging of electronic components in electronic devices. In particular, as the degree of integration of semiconductor integrated circuits increases, thousand-knob carriers using ceramic substrates have been put into practical use, and the number of terminals has increased, making the pinch smaller.

In order to mount the chip carrier as described above on a printed circuit board, the connection surface (i) of the ceramic substrate of the chip carrier is
ffl Connecting pads and bumps formed on the surface opposite to the surface on which the semiconductor integrated circuit is mounted (hereinafter referred to as the back surface of the chip substrate) are placed at a predetermined position on the printed circuit board and their temperature is raised. The so-called reflow method of soldering is often used.

FIG. 1 is a perspective view showing the structure of a standardized tissop carrier that is widely available on the market. As is clear from the figure, the chip carrier is a small, so-called leadless package having a gold-plated cavity 2 on a square or rectangular ceramic chip substrate 1.

The IC chip 3 is fixedly mounted on the chip substrate 1,
It is connected to a connection pad 4 disposed on the bottom surface of the cavity 2 by gold bonding or soldering. The connection pad 4 is connected to an external terminal 5 formed on the surface of the chip substrate 1 by a metallization method, and its tip reaches the back surface of the chip substrate 1.

The connection portion 6 is subjected to surface treatment such as gold plating to facilitate connection when soldering by the reflow method.

The plan view of FIG. 2(a) and the cross-sectional view of FIG. 2fbl show a leadless chip carrier as a type of ceramic package to enable higher density packaging.

While the external terminals 5 of the leadless chip carrier shown in FIG. 1 are formed along the surface of the chip substrate l, in the example shown in FIG. Conductive terminals formed by mixing and sintering metal powder and ceramic powder pass through the ceramic of the chip substrate 1 and are provided at the lower ends of the mounted IC chips 3 and vias 7. The bumps 8 are electrically connected to each other. The leadless chip carrier is mounted on a printed circuit board via bumps 8. Hump 8 is usually pb-3n
This is a protrusion made of a type of brazing material. 9 is a ceramic lid for internal protection of the IC chip 3 and the like.

FIG. 3 is a side view including a partial cross-sectional view showing a method of using a probe for performing a connection test with the beam rest knob carrier mounted on a printed circuit board. After the leadless chip carrier is mounted, the solder connection between the via 7 and the connection pad 11 on the printed circuit board 10 is hidden under the chip board l. is via 7 on the top surface of chip substrate 1.
A test pad 12 connected to the upper end of the test pad 12 is formed.

The pad 11 is connected to a test pad 14 provided on the opposite surface of the printed circuit board 10 through a through hole 13 passing through the printed circuit board IO.

To inspect the connection between the leadless chip carrier and the printed circuit board 10, as shown in the figure, on the one hand, probes 15. A probe base 16 is implanted in a substrate 17 and is brought into contact with a pad 12 on the top surface of the chip substrate 1 of the leadless chip carrier with a contact terminal 19 connected to a tester (not shown) through a conductor 18, and a similar probe 20 is placed on the other side. A method is adopted in which an electrical continuity test is performed by contacting the pad 14 on the back surface of the printed circuit board 10. Here, the probe 15 is fitted onto the probe base 16 and slides smoothly, and is biased downward by a small helical spring not visible in the figure, so the tip of the probe 15 comes into close contact with the pad 12. The structure is such that it can be done.

Now, in the current situation where there is no end to the demand for higher-density packaging of semiconductor chips, the pinch of vias 7 on the substrate of leadless chip carriers is becoming smaller and smaller.
Conventionally, the standard pitch was 2.5 mm, but the pitch is about half that, and higher density is being promoted. In the structure of the contact terminal 19 as shown in FIG. 3, the probe 15 does not have enough room to accommodate the bulge in the portion that contacts the probe base 16 and the conductive wire 18. In addition, since the pinch of the bump 8 is small, the solder around the hump 8 tends to stick to each other and cause a short circuit. The emergence of an inspection method that can solve these problems has been long awaited.

tc) Purpose of the Invention The present invention has been made in view of the above-mentioned points, and the present invention has been made in view of the above-mentioned points. The purpose of this invention is to provide a test method that can effectively perform a connection test.

(d) Structure of the Invention The object of the above invention is to provide a method for inspecting the connection status of the connection portion after a pancage containing a semiconductor integrated circuit element is connected and mounted on a printed circuit board via a connection means. The connection test band formed on the surface of the pan cage is made of a high-resistance metal material and embedded in the base body corresponding to each pad, and the end opposite to the contact end is electrically conductive. A contact terminal comprising a plurality of short-circuited probes is brought into contact with a contact end thereof, and a probe is connected to a pad conductive to the connection portion and disposed on a surface of the printed circuit board opposite to the pancage mounting surface. This can be easily achieved by individually measuring the resistance value including the contact portion while making contact with each other.

Embodiments of the Invention Examples of the present invention will be described below with reference to the drawings. A side view of FIG. Give an example.

To summarize the present invention, by collectively short-circuiting the closely spaced test pads 12 on the chip substrate 1 via a resistor,
On the other hand, by simplifying the sentence structure that can be created, and by distributing the positions of the pads 14 for connection inspection on the back side of the printed circuit board 10 by using the inner layer wiring in the printed circuit board 10, there is enough space to accommodate three individual probes 20. In addition, a short circuit between the humps 8 is detected from the current value flowing through each probe 200.

FIG. 4 is a side view including a partial cross-sectional view showing an embodiment of a method for inspecting a connection portion between a leadless chip carrier and a printed circuit board/substrate according to the present invention.

Probe 2 made of high resistance metal wire such as nickel chrome iron instead of the conventional probe 15 shown in FIG.
1 are arranged corresponding to the test pads 12 of the leadless chip carrier to be tested, and each is implanted so that it can slide into a small hole formed in a contact terminal board 22 made of an insulating plate, and A contact terminal 24 is used which has a structure in which the curved portion 21a at the top of each probe 21 is held down by a cover 23 to elastically bias the probe 21 in the direction of the arrow in the figure. Since the cover 23 is made of metal, the probe 21 is electrically short-circuited at its upper end (curved portion 21a).

The connection test pad 14 on the back side of the printed circuit board 10 is connected to the inner layer wiring 25 of the printed circuit board 10. Alternatively, since the probes 20 are arranged with increased distance from each other by surface wiring, it is possible to use the conventional probes 20, and therefore each probe 20 can be tested by a continuity tester (not shown). test current, i.e. the resistance of the connection in question.

Of course, if the connection between the bump 8 and the connection pad 11 on the printed circuit board 10 is broken, it can be detected immediately.

For example, if the solders of two adjacent connections are short-circuited together, the probe 21 has a predetermined resistance value, and when the short-circuit occurs, the resistance value is halved, so this also applies. It is also easy to discover.

In the embodiments described above, an example of a leadless chip carrier having a hump 8 was dealt with.

It goes without saying that the same connection inspection method according to the present invention can be applied even when a pin is provided instead of the hump 8.

(f) Effects of the invention As is clear from the above explanation, the density has been increased to a high degree recently. If the inspection method based on the present invention is applied to the inspection of the connection portion between a leadless chip carrier, etc., which has a row of bumps with a small pitch, and a printed circuit board on which it is mounted, difficulties associated with a high-density arrangement of connection terminals such as bumps 8 can be avoided. This has the effect of overcoming the above problems, allowing the inspection to be carried out smoothly and easily, and greatly contributing to cost reduction and quality improvement.

[Brief explanation of the drawing]

Figure 1 is a perspective view showing the structure of a standardized chip carrier that is widely commercially available, Figure 2 is a plan view and cross-sectional view of a chip carrier with vias that enable higher density mounting, and Figure 3 is a lead FIG. 3 is a side view including a partial cross-sectional view showing a conventional inspection method for a connecting portion between a non-chip carrier and a mounted printed circuit board. FIG. 4 is a side view including a partial sectional view showing the same inspection method according to the present invention. In the figure, l is a chip substrate and 3 is an IC chip. 5 is an external terminal of the chip carrier, 7 is a via, 8 is a bump, 10 is a printed circuit board, and 1L12.14 is a band.

Claims (1)

[Claims] When a package housing a semiconductor integrated circuit element is connected and mounted on a printed circuit board via a connecting means and the connection status of the connection part is inspected, on the one hand, a connection inspection band formed on the surface of the package is used. A contact terminal comprising a plurality of probes made of a high-resistance metal material and whose ends opposite to the contact ends are electrically short-circuited with a conductive member, implanted in a base body corresponding to each of the bands. A resistance value including the contact portion while individually contacting with a probe a band that is in contact with the contact end and is conductive to the connection portion and arranged on the surface of the printed circuit board opposite to the package mounting surface on the other hand. A connection inspection method between a package and a printed circuit board, which is characterized by individually measuring .