JPH05267393A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH05267393A JPH05267393A JP4062902A JP6290292A JPH05267393A JP H05267393 A JPH05267393 A JP H05267393A JP 4062902 A JP4062902 A JP 4062902A JP 6290292 A JP6290292 A JP 6290292A JP H05267393 A JPH05267393 A JP H05267393A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- relay plate
- semiconductor device
- holes
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置及びその製造
方法に関し、特に半導体チップがフリップチップ方式で
基板に取付けられる半導体装置及びその製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which a semiconductor chip is mounted on a substrate by a flip chip method and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】半導体集積回路（以下ＩＣと記す）の製
造技術における微小化と、これに伴なう高集積化，高機
能化，多端子化という傾向により、これらの半導体チッ
プの接触端子と回路基板の接続端子間の接続についても
微小化，多端子化が要求されている。半導体チップと回
路基板の接続方法には、ワイヤーボンド方式，ＴＡＢ方
式，フリップチップ方式などが知られているが、多端子
を有する半導体チップの高密度実装方式としてはフリッ
プチップ方式が適している。これはフリップチップ方式
では半導体チップの表面上の全面に接続端子（バンプ）
を設けることができ、周辺部のみに接続端子を設けるワ
イヤーボンド方式やＴＡＢ方式に比べ、多端子化が容易
であるからである。2. Description of the Related Art Due to the miniaturization in the manufacturing technology of semiconductor integrated circuits (hereinafter referred to as IC) and the accompanying tendency toward higher integration, higher functionality and multiple terminals, contact terminals of these semiconductor chips There is also a demand for miniaturization and multi-terminal connection between the connection terminals on the circuit board. A wire bond method, a TAB method, a flip chip method, etc. are known as a method for connecting a semiconductor chip and a circuit board, but a flip chip method is suitable as a high-density mounting method for a semiconductor chip having multiple terminals. In the flip chip method, this is a connection terminal (bump) on the entire surface of the semiconductor chip.
This is because the number of terminals can be increased and the number of terminals can be easily increased as compared with the wire bond method or the TAB method in which the connection terminals are provided only in the peripheral portion.
【０００３】またこのフリップチップ方式は、接続に必
要な配線長が短いため、電気的特性も優れている。これ
らの理由により１０数年前から実装方式のひとつとし
て、特に大型コンピューター用ＩＣの実装方式としてフ
リップチップ方式が実用化されており、最近では液晶表
示電子部品への実装方式としても検討されている。従来
のフリップチップ方式を用いる半導体チップは、その表
面に形成されたパッド部に、例えば半田バンプをメッキ
法や半田ボール供給法で形成する方式であったが、最近
では半田バンプに代り、金バンプか銅バンプあるいはワ
イヤーボンド方式により金のボールのバンプが用いられ
ている。また半田バンプの形状については球状から鼓状
への変更等各種の研究や実験が行なわれている。Further, the flip chip method has excellent electrical characteristics because the wiring length required for connection is short. For these reasons, a flip-chip method has been put into practical use as one of the mounting methods for several decades, particularly as a mounting method for ICs for large-scale computers, and is recently being considered as a mounting method for liquid crystal display electronic components. .. In the conventional semiconductor chip using the flip chip method, for example, a solder bump is formed on a pad portion formed on the surface of the semiconductor chip by a plating method or a solder ball supply method, but recently, a gold bump is used instead of the solder bump. Copper ball bumps or wire ball bumps of gold balls are used. In addition, various researches and experiments such as changing the shape of the solder bump from a spherical shape to a drum shape have been conducted.
【０００４】また従来からフリップチップ方式の半導体
素子は、チップに切断する前のウェハー状態でＤＣ特性
等の電気的評価を行っている。しかし、ＡＣ特性等の電
気的評価は、チップが搭載されているパッケージあるい
は回路基板にフリップチップボンディングを行い、最終
製品の形態に仕上げてから行われている。従ってフリッ
プチップボンディングを行った後に特性評価を行って、
もし異状があった場合、このチップの取り外し（リペ
ア）は非常に困難である。Conventionally, flip-chip type semiconductor elements are electrically evaluated in terms of DC characteristics and the like in a wafer state before being cut into chips. However, electrical evaluation of AC characteristics and the like is performed after flip chip bonding is performed on a package or a circuit board on which a chip is mounted to finish the product into a final product form. Therefore, after performing flip chip bonding, characteristic evaluation is performed,
If something goes wrong, the removal (repair) of this chip is very difficult.
【０００５】[0005]
【発明が解決しようとする課題】フリップチップ方式で
製造される従来の半導体装置においては、上述したよう
に、フリップチップボンディングを実施したあとで最終
的な電気的特性評価が行なわれていた。従ってチップに
異状があった時、製造工程における損失が大きいという
問題があった。これらの原因はフリップチップボンディ
ングを実施する前に、チップ状態で最終的な電気的特性
の評価を十分に実施することが困難であったからであ
る。これは図３に示すように、ウェハー状態でメッキ法
等により半田バンプ２を形成するプロセスでは、ウェハ
ー内またはチップ内においても、半田バンプ２の高さに
ばらつきが生じてしまい、チップ状態で特性検査を行う
時、加圧のみでは検査用基板２０の電極２１と半田バン
プ２との電気的導通が十分に得られないからである。As described above, in the conventional semiconductor device manufactured by the flip chip method, the final electrical characteristic evaluation is performed after the flip chip bonding is performed. Therefore, there is a problem that the loss in the manufacturing process is large when the chip is abnormal. These causes are because it was difficult to sufficiently evaluate the final electrical characteristics in a chip state before performing flip chip bonding. As shown in FIG. 3, in the process of forming the solder bumps 2 by the plating method or the like in the wafer state, the height of the solder bumps 2 varies within the wafer or in the chip, and the characteristics in the chip state are increased. This is because when conducting the inspection, sufficient electrical connection between the electrodes 21 of the inspection substrate 20 and the solder bumps 2 cannot be obtained only by applying pressure.
【０００６】また他の方法として図４に示すように、半
導体チップ１と検査用基板２０の間に例えば金属細線に
より厚さ方向のみに導電性を有する導電性弾性シート８
等を介在させ、半導体チップ１の半田バンプ２と検査用
基板２０の電極２１とを加圧のみにより電気的導通を得
る方法がある。この方法においては半導体チップ上の半
田バンプの僅かな高さの差を導電性弾性シートにより吸
収でき、半田バンプ２と検査用基板の電極２１の接触が
完全に得られる。しかしながら、導電性弾性シート８の
導電抵抗は例えば、数百ｍΩから数Ω程度と大きい。従
ってＩＣがパワーＩＣ等の場合、検査時の大電流により
導電性弾性シートが発熱し、その物性値が劣化してしま
うという点や、半田バンプに高さの差が有るために各半
田バンプと導電性弾性シートとの接触抵抗に差が生じ
る。特に多端子のＩＣの場合、完全な接続を得るには大
きな圧力、例えば３００ピンのＩＣでは４．５ｋｇ〜６
ｋｇ程の圧力が必要となり、半導体チップ及び検査用基
板が破損する恐れが有る等の問題点があった。As another method, as shown in FIG. 4, a conductive elastic sheet 8 having conductivity only in the thickness direction is formed between the semiconductor chip 1 and the inspection substrate 20 by, for example, a thin metal wire.
There is a method of electrically connecting the solder bumps 2 of the semiconductor chip 1 and the electrodes 21 of the inspection substrate 20 only by applying pressure by interposing the above. In this method, the slight difference in height of the solder bump on the semiconductor chip can be absorbed by the conductive elastic sheet, and the contact between the solder bump 2 and the electrode 21 of the inspection substrate can be completely obtained. However, the conductive resistance of the conductive elastic sheet 8 is as large as several hundred mΩ to several Ω. Therefore, when the IC is a power IC or the like, the conductive elastic sheet generates heat due to a large current at the time of inspection, and the physical property values thereof are deteriorated. A difference occurs in contact resistance with the conductive elastic sheet. Especially in the case of a multi-terminal IC, a large pressure is required to obtain a complete connection, for example, in a 300-pin IC, 4.5 kg to 6 kg.
Since a pressure of about kg is required, there is a problem that the semiconductor chip and the inspection substrate may be damaged.
【０００７】これらの問題点のため従来は、図５に示す
ように、検査用基板２０又は回路基板と半導体チップ１
は、不活性ガスを使用したリフロー炉で熱処理を行うこ
とにより半田バンプ２を溶融させてフリップチップボン
ディングを実施し、最終的な電気的特性評価が行なわれ
ていた。Due to these problems, conventionally, as shown in FIG. 5, the inspection substrate 20 or the circuit substrate and the semiconductor chip 1 are used.
, The solder bumps 2 are melted by performing heat treatment in a reflow furnace using an inert gas, flip chip bonding is performed, and final electrical characteristic evaluation is performed.
【０００８】[0008]
【課題を解決するための手段】第１の発明の半導体装置
は、複数のスルーホールが形成された耐熱性の絶縁シー
トとこのスルーホールをふさぐように絶縁シートの裏面
に設けられたパッドとからなるシート状の中継板と、前
記スルーホールを介し前記パッドに先端部が接続された
半田バンプを有する半導体チップとを含むものである。The semiconductor device according to the first invention comprises a heat-resistant insulating sheet having a plurality of through holes and a pad provided on the back surface of the insulating sheet so as to close the through holes. And a semiconductor chip having a solder bump whose tip portion is connected to the pad via the through hole.
【０００９】第２の発明の半導体装置の製造方法は、ス
ルーホールが形成された耐熱性の絶縁シートとこのスル
ーホールをふさぐように絶縁シートの裏面に設けられた
パッドからなる中継板と、半田バンプを有する半導体チ
ップとを用意する工程と、前記中継板のスルーホール内
に前記半導体チップの半田バンプを入れ、熱処理して半
田バンプと前記パッドとを接続する工程とを含むもので
ある。According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a heat-resistant insulating sheet having through holes is formed, a relay plate made of a pad provided on the back surface of the insulating sheet so as to cover the through holes, and a solder. The method includes a step of preparing a semiconductor chip having bumps, and a step of inserting solder bumps of the semiconductor chip into the through holes of the relay board and heat-treating the solder bumps to connect the pads.
【００１０】第３の発明の半導体装置の製造方法は、ス
ルーホールが形成された耐熱性の絶縁シートとこのスル
ーホールをふさぐように絶縁シートの裏面に設けられた
パッドからなる中継板と、半田バンプを有する半導体チ
ップとを用意する工程と、前記中継板のスルーホール内
に前記半導体チップの半田バンプを入れ、熱処理して半
田バンプと前記パッドとを接続する工程と、前記中継板
のパッドに直接または導電性弾性シートを介して検査用
基板の電極を接触させ電気的特性を評価する工程とを含
むものである。According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a heat-resistant insulating sheet having through holes is formed, a relay plate made of a pad provided on the back surface of the insulating sheet so as to cover the through holes, and a solder. A step of preparing a semiconductor chip having bumps; a step of inserting the solder bumps of the semiconductor chip into the through holes of the relay plate and heat-treating the solder bumps to connect the pads to the pads of the relay plate; And directly contacting the electrodes of the inspection substrate with the conductive elastic sheet to evaluate the electrical characteristics.
【００１１】[0011]
【実施例】次に本発明について図面を参照して説明す
る。図１（ａ）〜（ｄ）は本発明の第１の実施例を説明
するための断面図である。The present invention will be described below with reference to the drawings. 1 (a) to 1 (d) are cross-sectional views for explaining a first embodiment of the present invention.
【００１２】まず図１（ａ）に示すように、複数の半田
バンプ２が形成された半導体チップ１と、スルーホール
４を有する耐熱性の絶縁フィルム３とこのスルーホール
４をふさぐように設けられたパッド５とＣｕ層６とから
なるシート状の中継板１０とを用意する。半田バンプ２
はウェハー状態でメッキ法等により形成されるが、その
高さは例えば平均値が１００μｍに対し±１０〜３０μ
ｍのばらつきが生じている。First, as shown in FIG. 1A, a semiconductor chip 1 on which a plurality of solder bumps 2 are formed, a heat-resistant insulating film 3 having a through hole 4 and a through hole 4 are provided so as to cover the through hole 4. A sheet-shaped relay plate 10 including the pad 5 and the Cu layer 6 is prepared. Solder bump 2
Is formed in a wafer state by a plating method or the like, and its height is, for example, ± 10 to 30 μ with respect to an average value of 100 μm.
There is a variation in m.
【００１３】そこで図１（ｂ）に示すように、半田バン
プ２の先端部にスルーホール４が形成されたシート状の
中継板１０を配置し、この状態で不活性ガスを使用した
リフロー炉で熱処理を行なうことによって、半田バンプ
２を中継板１０のパッド５に接続し、半導体装置を完成
させる。Therefore, as shown in FIG. 1B, a sheet-like relay plate 10 having through-holes 4 formed at the tips of the solder bumps 2 is arranged, and a reflow furnace using an inert gas in this state is used. By performing heat treatment, the solder bumps 2 are connected to the pads 5 of the relay plate 10 to complete the semiconductor device.
【００１４】シート状の中継板１０は、２層ＴＡＢテー
プの製法等を用いて製造する。すなわち、ポリイミド等
の絶縁フィルム３上に無電解メッキ等により給電用のＣ
ｕ膜を形成し、このＣｕ膜上にフォトレジストからなる
マスクを設け、電解メッキ法によりＣｕからなるパッド
５を形成する。次で、このパッド５に対応する絶縁フィ
ルム３にウェットエッチング法によりスルーホール４を
形成する。この時スルーホール４の開口部はテーパー状
になる。次で、必要に応じてスルーホール４内に電解メ
ッキ法によりＣｕ層６を、そしてパッド５の表面にＮｉ
またはＡｕメッキを施したのち、パッド５以外のＣｕ膜
を除去して中継板１０を完成させる。The sheet-shaped relay plate 10 is manufactured by a method such as a method for manufacturing a two-layer TAB tape. That is, C for power supply is provided on the insulating film 3 such as polyimide by electroless plating or the like.
A u film is formed, a mask made of photoresist is provided on the Cu film, and pads 5 made of Cu are formed by electrolytic plating. Next, through holes 4 are formed in the insulating film 3 corresponding to the pads 5 by a wet etching method. At this time, the opening of the through hole 4 is tapered. Next, if necessary, a Cu layer 6 is formed in the through hole 4 by an electrolytic plating method, and a Ni layer is formed on the surface of the pad 5.
Alternatively, after the Au plating is applied, the Cu film other than the pad 5 is removed to complete the relay plate 10.
【００１５】このスルーホール４の開口部がテーパー状
であるため、半田バンプ２の先端部はこのテーパーによ
りガイドされてスムーズにスルーホール４内に入り込
み、半導体チップ１と中継板１０の位置決めが容易かつ
正確に行なわれる。さらに、半田バンプ２の半田量の差
を吸収する事が可能となる。この状態で熱を加えて半田
バンプを溶融するが、チップサイズ，半田バンプの数、
半田バンプの高さのばらつき状態を考慮して、半導体チ
ップ１の上に重り等を載置することにより、半導体チッ
プ１を確実に中継板１０に接続できる。またリフロー炉
での処理時には必要に応じてフラックスを半田バンプ部
に塗布してもよい。このようにして取り付けられた中継
板１０のパッド５が形成された面は、平面度が十分に保
たれ、例えばポリイミドフィルムを用いた場合±１μｍ
以下の平面度が確保できる。次に、このようにして作ら
れた半導体装置を図１（ｃ）に示すように、検査用基板
２０上に配置された電極２１に中継板１０のパッド５を
位置合わせして加圧した状態で電気的導通が十分に得ら
れるようにし、電気的特性を検査する。検査用基板２０
上の電極２１も高さのばらつきは小さい方が良いので、
検査用基板２０の材質が例えばアルミナセラミックの場
合、電極２１の形成前に研磨処理を行ない、その後でス
クリーン印刷法，蒸着法，メッキ法等により電極２１を
形成する。またパワーＩＣ等以外の大電流を検査時に必
要としないＩＣでは、従来と同様に導電性弾性シートを
中継板１０と検査用基板３の間に介在させた形態で電気
特性の検査を行ってもよい。Since the opening of the through hole 4 is tapered, the tip of the solder bump 2 is guided by the taper and smoothly enters the through hole 4, and the semiconductor chip 1 and the relay plate 10 can be easily positioned. And it is done accurately. Further, it becomes possible to absorb the difference in the amount of solder of the solder bump 2. In this state, heat is applied to melt the solder bumps, but the chip size, the number of solder bumps,
By placing a weight or the like on the semiconductor chip 1 in consideration of the variation in the height of the solder bumps, the semiconductor chip 1 can be reliably connected to the relay board 10. Further, at the time of processing in the reflow furnace, flux may be applied to the solder bump portion as necessary. The surface of the relay plate 10 thus mounted, on which the pads 5 are formed, has sufficient flatness. For example, when a polyimide film is used, it is ± 1 μm.
The following flatness can be secured. Next, as shown in FIG. 1C, the semiconductor device manufactured in this manner is in a state in which the pad 5 of the relay plate 10 is aligned with the electrode 21 arranged on the inspection substrate 20 and pressed. To ensure sufficient electrical continuity and to inspect electrical characteristics. Inspection board 20
Since it is better that the upper electrode 21 also has a small variation in height,
When the inspection substrate 20 is made of alumina ceramic, for example, a polishing process is performed before the electrode 21 is formed, and then the electrode 21 is formed by a screen printing method, a vapor deposition method, a plating method, or the like. In the case of an IC that does not require a large current at the time of inspection, such as a power IC, even if an electrically conductive elastic sheet is interposed between the relay board 10 and the inspection board 3 as in the conventional case, the electrical characteristics are inspected. Good.
【００１６】また図１（ｄ）に示すように、最終的なフ
リップチップボンディングを回路基板３０に行なうと
き、例えば回路基板３０がアルミナセラミックである場
合、中継板１０に用いるポリイミド材は、半導体チップ
がＳｉの時、Ｓｉとアルミナセラミックの熱膨張係数の
中間値のものを選定する。例えば、熱膨張係数が３．０
×１０-6のＳｉと、６．８×１０-6のアルミナセラミッ
ク板を用いる場合は熱膨張係数が４〜５×１０-6のポリ
イミドフィルムを用いる。更に、回路基板３０と中継板
１０の接続部の半田バンプ２Ａは、半田バンプ２よりも
低融点の半田を選定する。これにより中継板のとりはず
し等の工程がなく、回路基板に実装しても熱膨張係数差
による熱応力集中を防止し、信頼性の高いフリップチッ
プボンディングが可能となる。As shown in FIG. 1D, when the final flip chip bonding is performed on the circuit board 30, for example, when the circuit board 30 is an alumina ceramic, the polyimide material used for the relay board 10 is a semiconductor chip. When Si is Si, an intermediate value of the thermal expansion coefficients of Si and alumina ceramic is selected. For example, the coefficient of thermal expansion is 3.0
And Si × 10 -6, the coefficient of thermal expansion in the case of using the alumina ceramic plate of 6.8 × 10 -6 is used a polyimide film of 4 to 5 × 10 -6. Further, for the solder bumps 2A at the connecting portion between the circuit board 30 and the relay board 10, a solder having a melting point lower than that of the solder bumps 2 is selected. As a result, there is no step of removing the relay board, and even if the relay board is mounted on the circuit board, concentration of thermal stress due to the difference in thermal expansion coefficient is prevented, and highly reliable flip chip bonding becomes possible.
【００１７】このように第１の実施例によれば、半導体
チップに中継板を接続し、検査用基板と組合せることに
より、最終的なフリップチップボンディングを実施する
前にＩＣに必要な最終的な電気的特性評価を実施できる
ようになる。従来フリップチップ方式の半導体装置は、
フリップチップボンディングを行ってから電気的評価を
行っていたために欠陥品が生じた時には、リペア等が困
難であるために、生産性を非常に悪くしていたが、本実
施例によればこの問題は解決し、製造効率の向上や信頼
性向上に大きな効果がある。As described above, according to the first embodiment, by connecting the relay plate to the semiconductor chip and combining it with the inspection substrate, the final IC required before the final flip chip bonding is carried out. It becomes possible to perform various electrical characteristic evaluations. Conventional flip-chip type semiconductor devices are
When a defective product was generated because the electrical evaluation was performed after flip chip bonding, the productivity was extremely deteriorated because repair or the like was difficult. Solves the problem, and has a great effect on improvement of manufacturing efficiency and reliability.
【００１８】図２（ａ）〜（ｃ）は本発明の第２の実施
例を説明するための断面図である。まず図２（ａ）に示
すように、半田バンプ２が形成された半導体チップ１
と、階段状のスルーホール４Ａが設けられた絶縁シート
７とスルーホール４Ａをふさぐように設けられたパッド
５Ａとからなるシート状の中継板１０Ａを用意する。FIGS. 2A to 2C are sectional views for explaining the second embodiment of the present invention. First, as shown in FIG. 2A, a semiconductor chip 1 on which solder bumps 2 are formed
Then, a sheet-shaped relay plate 10A including an insulating sheet 7 provided with stepped through holes 4A and a pad 5A provided so as to cover the through holes 4A is prepared.
【００１９】次に図２（ｂ）に示すように、スルーホー
ル４Ａと半田バンプ２とを位置合せした後、不活性ガス
を使用したリフロー炉で熱処理を行うことによって、半
田バンプ２を中継板１０Ａのパッド５Ａに接続する。こ
こでシート状の中継板１０Ａは、例えば耐熱性と電気絶
縁性を有するガラスエポキシ等のシートで構成され、そ
の製法は例えばＣＯＢ（Ｃｈｉｐ ｏｎ ｂｏａｒｄ）
用基板や、Ｐ−ＰＧＡ（プラスチックピングリッドアレ
イ）用基板と同様の製法が適用される。Next, as shown in FIG. 2B, after the through holes 4A and the solder bumps 2 are aligned with each other, heat treatment is performed in a reflow furnace using an inert gas, so that the solder bumps 2 are connected to the relay plate. Connect to 10A pad 5A. Here, the sheet-shaped relay plate 10A is made of, for example, a sheet of glass epoxy or the like having heat resistance and electrical insulation, and its manufacturing method is, for example, COB (Chip on board).
A manufacturing method similar to that for the substrate for P-PGA (plastic pin grid array) and the substrate for P-PGA (plastic pin grid array) is applied.
【００２０】例えば、スルーホール径の異なる２枚のガ
ラスエポキシシートを貼り合わせ、次にスルーホール径
の小さい側へＣｕ箔等を貼り合わせ、次いで所定のパッ
ド等のパターンを形成し、次で仕上メッキとしてＮｉ，
Ａｕ等を施し中継板を完成させる。このスルーホール４
Ａの形状はテーパー状でなく、階段状であるが、半導体
チップ１上の半田バンプ２の先端部は、この階段状のス
ルーホール４Ａによりガイドされてスムーズに入り込む
ため、半導体チップ１とシート状の中継板１０Ａの位置
決めが容易かつ正確に行なわれる。For example, two glass epoxy sheets having different through-hole diameters are stuck together, then a Cu foil or the like is stuck to the side having a smaller through-hole diameter, then a predetermined pad pattern or the like is formed, and then finished. Ni as plating,
Apply Au or the like to complete the relay plate. This through hole 4
The shape of A is not a taper shape but a step shape, but the tip end of the solder bump 2 on the semiconductor chip 1 is guided by the stepped through hole 4A and smoothly enters, so that the semiconductor chip 1 and the sheet shape. The relay plate 10A can be positioned easily and accurately.
【００２１】この状態で熱を加えてバンプを溶融するこ
とにより半導体チップ１と中継板１０Ａは接続される。
このようにして取り付けられた中継板１０Ａのパッド５
Ａが形成された面は平面度が十分に保たれ、例えばガラ
スエポキシシートでは±２μｍ程度が確保できる。また
ガラスエポキシシートそのものはポリイミドフィルムの
１／１０〜１／２０のコストであるため、中継板１０Ａ
は第１の実施例のものより安価に製造できる。In this state, the semiconductor chip 1 and the relay plate 10A are connected by applying heat to melt the bumps.
Pad 5 of relay plate 10A attached in this way
The surface on which A is formed has sufficient flatness, and for example, a glass epoxy sheet can secure about ± 2 μm. In addition, since the glass epoxy sheet itself costs 1/10 to 1/20 of the cost of the polyimide film, the relay board 10A
Is cheaper to manufacture than that of the first embodiment.
【００２２】このようにして作られた半導体装置は、図
１（ｃ）で説明したと同様に、検査用基板を用いるか、
または図２（ｃ）に示すように、真空吸着口２３を有す
る検査用治具２２と検査用のプローバー２４を用いて、
検査用基板を使用しない電気特性の検査を行う。これは
直接半田バンプの先端部に検査用プローバーを接触させ
る方法ではないために、安定した電気的導通が得られ
る。電気的特性評価後に最終実装用回路基板に実施する
場合は、図１（ｄ）に示したようにバンプ２Ａを用い
る。The semiconductor device thus manufactured uses the inspection substrate as described in FIG. 1 (c).
Alternatively, as shown in FIG. 2C, by using an inspection jig 22 having a vacuum suction port 23 and an inspection prober 24,
The electrical characteristics are inspected without using the inspection board. Since this is not a method of directly contacting the tip end of the solder bump with the inspection prober, stable electrical conduction can be obtained. When the final mounting circuit board is implemented after the electrical characteristics evaluation, the bumps 2A are used as shown in FIG.
【００２３】[0023]
【発明の効果】以上説明したように本発明は、スルーホ
ールとパッドとが設けられたシート状の中継板の、この
スルーホールを介して半導体チップの半田バンプをパッ
ドに接続することにより、フリップチップボンディング
前に半導体装置の電気的特性を評価することができる。
このため、従来の最終的なフリップチップボンディング
を行ってから電気的特性評価を行っていたため生じる生
産性の悪化が改善されると共に、信頼性を向上させるこ
とができるという効果がある。As described above, according to the present invention, a sheet-like relay plate provided with through holes and pads is connected to the pads by connecting the solder bumps of the semiconductor chip to the pads. The electrical characteristics of the semiconductor device can be evaluated before chip bonding.
Therefore, there is an effect that the deterioration of productivity caused by the electrical characteristic evaluation performed after the conventional final flip-chip bonding is improved and the reliability can be improved.
【図１】本発明の第１の実施例を説明するための断面
図。FIG. 1 is a sectional view for explaining a first embodiment of the present invention.
【図２】本発明の第２の実施例を説明するための断面
図。FIG. 2 is a sectional view for explaining a second embodiment of the present invention.
【図３】従来の半導体装置の電気的特性評価を説明する
ための断面図。FIG. 3 is a cross-sectional view for explaining electrical characteristic evaluation of a conventional semiconductor device.
【図４】従来の半導体装置の電気的特性評価を説明する
ための断面図。FIG. 4 is a cross-sectional view for explaining electrical characteristic evaluation of a conventional semiconductor device.
【図５】従来の半導体装置の電気的特性評価を説明する
ための断面図。FIG. 5 is a cross-sectional view for explaining electrical characteristic evaluation of a conventional semiconductor device.
１ 半導体チップ ２，２Ａ 半田バンプ ３ 絶縁フィルム ４，４Ａ スルーホール ５，５Ａ パッド ６ Ｃｕ層 ７ 絶縁シート ８ 導電性弾性シート １０，１０Ａ 中継板 ２０ 検査用基板 ２１ 電極 ２２ 検査用治具 ２３ 真空吸着口 ２４ プロバー 1 Semiconductor Chip 2, 2A Solder Bump 3 Insulation Film 4, 4A Through Hole 5, 5A Pad 6 Cu Layer 7 Insulation Sheet 8 Conductive Elastic Sheet 10, 10A Relay Plate 20 Inspection Board 21 Electrode 22 Inspection Jig 23 Vacuum Adsorption Mouth 24 Pro Bar
Claims (7)
の絶縁シートとこのスルーホールをふさぐように絶縁シ
ートの裏面に設けられたパッドとからなるシート状の中
継板と、前記スルーホールを介し前記パッドに先端部が
接続された半田バンプを有する半導体チップとを含むこ
とを特徴とする半導体装置。1. A sheet-like relay plate comprising a heat-resistant insulating sheet having a plurality of through holes and a pad provided on the back surface of the insulating sheet so as to cover the through holes, and the through holes. And a semiconductor chip having a solder bump whose tip is connected to the pad.
にはテーパが形成されている請求項１記載の半導体装
置。2. The semiconductor device according to claim 1, wherein a taper is formed at an opening of the through hole into which the solder bump is inserted.
は階段状に形成されている請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein the opening of the through hole into which the solder bump is inserted is formed in a step shape.
装回路基板との中間値を有する請求項１記載の半導体装
置。4. The semiconductor device according to claim 1, wherein the thermal expansion coefficient of the relay plate has an intermediate value between the semiconductor chip and the mounting circuit board.
シートとこのスルーホールをふさぐように絶縁シートの
裏面に設けられたパッドからなる中継板と、半田バンプ
を有する半導体チップとを用意する工程と、前記中継板
のスルーホール内に前記半導体チップの半田バンプを入
れ、熱処理して半田バンプと前記パッドとを接続する工
程とを含むことを特徴とする半導体装置の製造方法。5. A step of preparing a heat-resistant insulating sheet having a through hole, a relay plate made of a pad provided on the back surface of the insulating sheet so as to cover the through hole, and a semiconductor chip having a solder bump. And a step of inserting solder bumps of the semiconductor chip into the through holes of the relay plate and heat-treating the solder bumps to connect the pads to the pads.
シートとこのスルーホールをふさぐように絶縁シートの
裏面に設けられたパッドからなる中継板と、半田バンプ
を有する半導体チップとを用意する工程と、前記中継板
のスルーホール内に前記半導体チップの半田バンプを入
れ、熱処理して半田バンプと前記パッドとを接続する工
程と、前記中継板のパッドに直接または導電性弾性シー
トを介して検査用基板の電極を接触させ電気的特性を評
価する工程とを含むことを特徴とする半導体装置の製造
方法。6. A step of preparing a heat-resistant insulating sheet having a through hole, a relay plate including a pad provided on the back surface of the insulating sheet so as to cover the through hole, and a semiconductor chip having a solder bump. And a step of inserting the solder bumps of the semiconductor chip into the through holes of the relay plate and heat treating them to connect the solder bumps to the pads, and inspecting the pads of the relay plate directly or via a conductive elastic sheet. A method of manufacturing a semiconductor device, the method comprising: contacting electrodes of a substrate for evaluation of electrical characteristics.
させて電気的特性を評価する請求項６記載の半導体装置
の製造方法。7. The method for manufacturing a semiconductor device according to claim 6, wherein the inspection probe is brought into contact with the pad of the relay plate to evaluate the electrical characteristics.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4062902A JP2715793B2 (en) | 1992-03-19 | 1992-03-19 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4062902A JP2715793B2 (en) | 1992-03-19 | 1992-03-19 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05267393A true JPH05267393A (en) | 1993-10-15 |
| JP2715793B2 JP2715793B2 (en) | 1998-02-18 |
Family
ID=13213651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4062902A Expired - Fee Related JP2715793B2 (en) | 1992-03-19 | 1992-03-19 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2715793B2 (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08153751A (en) * | 1994-08-31 | 1996-06-11 | Nec Corp | Electronic device assembly, and manufacture thereof |
| JPH11160356A (en) * | 1997-11-25 | 1999-06-18 | Matsushita Electric Ind Co Ltd | Probe card for wafer collective measurement and inspection and ceramic multilayer interconnection board as well as their manufacture |
| US6062873A (en) * | 1996-07-16 | 2000-05-16 | Nec Corporation | Socket for chip package test |
| KR20010104147A (en) * | 2000-05-13 | 2001-11-24 | 윤종광 | Multiple line grid and fabrication method thereof and method for mounting semiconductor chip on pcb board by using it |
| JP2006269917A (en) * | 2005-03-25 | 2006-10-05 | Kyocera Corp | Laminated wiring board and mounting method thereof |
| JP2008147317A (en) * | 2006-12-08 | 2008-06-26 | Matsushita Electric Ind Co Ltd | Packaging method of electronic component |
| WO2009158057A1 (en) * | 2008-06-26 | 2009-12-30 | Freescale Semiconductor Inc. | Test interposer having active circuit component and method therefor |
| EP2936558A4 (en) * | 2012-12-20 | 2016-08-31 | Mediatek Inc | Semiconductor package and method for fabricating base for semiconductor package |
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1992
- 1992-03-19 JP JP4062902A patent/JP2715793B2/en not_active Expired - Fee Related
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08153751A (en) * | 1994-08-31 | 1996-06-11 | Nec Corp | Electronic device assembly, and manufacture thereof |
| US6062873A (en) * | 1996-07-16 | 2000-05-16 | Nec Corporation | Socket for chip package test |
| JPH11160356A (en) * | 1997-11-25 | 1999-06-18 | Matsushita Electric Ind Co Ltd | Probe card for wafer collective measurement and inspection and ceramic multilayer interconnection board as well as their manufacture |
| KR20010104147A (en) * | 2000-05-13 | 2001-11-24 | 윤종광 | Multiple line grid and fabrication method thereof and method for mounting semiconductor chip on pcb board by using it |
| JP2006269917A (en) * | 2005-03-25 | 2006-10-05 | Kyocera Corp | Laminated wiring board and mounting method thereof |
| JP2008147317A (en) * | 2006-12-08 | 2008-06-26 | Matsushita Electric Ind Co Ltd | Packaging method of electronic component |
| WO2009158057A1 (en) * | 2008-06-26 | 2009-12-30 | Freescale Semiconductor Inc. | Test interposer having active circuit component and method therefor |
| US7808258B2 (en) | 2008-06-26 | 2010-10-05 | Freescale Semiconductor, Inc. | Test interposer having active circuit component and method therefor |
| TWI447408B (en) * | 2008-06-26 | 2014-08-01 | Freescale Semiconductor Inc | Test interposer having active circuit component and method therefor |
| US10573615B2 (en) | 2012-07-31 | 2020-02-25 | Mediatek Inc. | Semiconductor package and method for fabricating base for semiconductor package |
| US10573616B2 (en) | 2012-07-31 | 2020-02-25 | Mediatek Inc. | Semiconductor package and method for fabricating base for semiconductor package |
| US10580747B2 (en) | 2012-07-31 | 2020-03-03 | Mediatek Inc. | Semiconductor package and method for fabricating base for semiconductor package |
| US10991669B2 (en) | 2012-07-31 | 2021-04-27 | Mediatek Inc. | Semiconductor package using flip-chip technology |
| US11469201B2 (en) | 2012-07-31 | 2022-10-11 | Mediatek Inc. | Semiconductor package and method for fabricating base for semiconductor package |
| EP2936558A4 (en) * | 2012-12-20 | 2016-08-31 | Mediatek Inc | Semiconductor package and method for fabricating base for semiconductor package |
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| Publication number | Publication date |
|---|---|
| JP2715793B2 (en) | 1998-02-18 |
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