JP2008147317A - Packaging method of electronic component - Google Patents

Packaging method of electronic component Download PDF

Info

Publication number
JP2008147317A
JP2008147317A JP2006331245A JP2006331245A JP2008147317A JP 2008147317 A JP2008147317 A JP 2008147317A JP 2006331245 A JP2006331245 A JP 2006331245A JP 2006331245 A JP2006331245 A JP 2006331245A JP 2008147317 A JP2008147317 A JP 2008147317A
Authority
JP
Japan
Prior art keywords
substrate
electrode
electronic component
protrusion
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006331245A
Other languages
Japanese (ja)
Other versions
JP2008147317A5 (en
JP4889464B2 (en
Inventor
Yoshihiro Tomura
善広 戸村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2006331245A priority Critical patent/JP4889464B2/en
Publication of JP2008147317A publication Critical patent/JP2008147317A/en
Publication of JP2008147317A5 publication Critical patent/JP2008147317A5/ja
Application granted granted Critical
Publication of JP4889464B2 publication Critical patent/JP4889464B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81141—Guiding structures both on and outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To automatically correct dislocation when jointing a bump electrode of an electronic component to a corresponding terminal electrode of a substrate. <P>SOLUTION: An alignment projection 12 which is higher than a bump electrode 11 is formed at a semiconductor element. A recess 14 is formed to correspond to the alignment projection 12 on a substrate. The alignment projection 12 is firstly inserted into the recess 14 of the substrate to be deformed. An electronic component is moved sideways such that the bump electrode 11 approaches a wiring electrode 13 of the substrate, for automatic correction. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、狭ピッチの配線電極へ半導体チップなどの電子部品を正確に実装する電子部品の実装方法に関するものである。   The present invention relates to an electronic component mounting method for accurately mounting an electronic component such as a semiconductor chip on a wiring electrode having a narrow pitch.

近年、電子機器は軽薄短小傾向を強め、高機能集積化及び信号処理の高速化が進んできており、これに伴い半導体チップの電極間ピッチも１００〔μｍ〕以下が要求されている。   In recent years, electronic devices have become increasingly light and thin, and high-function integration and high-speed signal processing have progressed. Accordingly, the pitch between electrodes of a semiconductor chip is required to be 100 [μm] or less.

このような電極間ピッチ、幅の狭い電極に対して、半導体チップをバンプを用いて配線基板上に実装することは技術的に極めて困難であり、狭ピッチでも組み立て容易な構造、方法が検討されている。   It is extremely difficult to technically mount a semiconductor chip on a wiring board using bumps for such an electrode pitch and narrow electrode, and a structure and a method that can be easily assembled even at a narrow pitch have been studied. ing.

このような方法において代表的なものとしては、特許文献１がある。
図１５（ｂ）に示すように基板１に電子部品としての半導体チップ２を実装する場合には、図１５（ａ）に示すように、半導体チップ２の電極３上に金の突起電極４を形成する。突起電極４は引きちぎることによって先端が細く形成されている。基板１の上に形成された配線電極５は、その中央に形成されている凹部６の形状が入口よりも奥端が広く形成されている。そして、基板１の凹部６の中央に、突起電極４の先端が来るように基板１に対する半導体チップ２の位置を合わせる。そして、基板１に半導体チップ２を押圧することによって、突起電極４の先端は基板１の凹部６の底部に当接して変形して配線電極５に係合して実装が完了する。
特開平１１−２０４９１３号公報 A typical example of such a method is Patent Document 1.
When the semiconductor chip 2 as an electronic component is mounted on the substrate 1 as shown in FIG. 15B, the gold protruding electrode 4 is formed on the electrode 3 of the semiconductor chip 2 as shown in FIG. Form. The protruding electrode 4 is formed with a thin tip by tearing. The wiring electrode 5 formed on the substrate 1 has a concave portion 6 formed in the center of which the back end is formed wider than the entrance. Then, the position of the semiconductor chip 2 with respect to the substrate 1 is aligned so that the tip of the protruding electrode 4 comes to the center of the recess 6 of the substrate 1. Then, by pressing the semiconductor chip 2 against the substrate 1, the tip of the protruding electrode 4 comes into contact with the bottom of the concave portion 6 of the substrate 1 to deform and engage with the wiring electrode 5 to complete the mounting.
JP-A-11-204913

しかし、特許文献１の場合、各突起電極４とそれぞれ対応する各配線電極５との接合時に、Ｘ、Ｙ、θの位置ずれがある場合、その位置ずれが配線電極５に対し数μｍでもあると、各突起電極４を各対応の配線電極５に正確に実装できない。または、半導体チップ２側から荷重をかけていく途中で、配線電極５の微妙な形状により配線電極５から突起電極４がずり落ちたり、基板１と半導体チップ２との間に熱硬化性樹脂を介装している場合には、配線電極５から突起電極４がずり落ちた状態のまま樹脂硬化してしまう。   However, in the case of Patent Document 1, when there is a positional deviation of X, Y, and θ when each protruding electrode 4 and each corresponding wiring electrode 5 are joined, the positional deviation is several μm with respect to the wiring electrode 5. Thus, each protruding electrode 4 cannot be accurately mounted on each corresponding wiring electrode 5. Alternatively, in the course of applying a load from the semiconductor chip 2 side, the protruding electrode 4 may fall off from the wiring electrode 5 due to the delicate shape of the wiring electrode 5, or a thermosetting resin may be placed between the substrate 1 and the semiconductor chip 2. When it is interposed, the resin is cured while the protruding electrode 4 is slipped off from the wiring electrode 5.

本発明は、配線電極が狭ピッチの基板に対して、半導体チップの突起電極を正確に実装できる半導体素子の実装方法を提供することを目的とする。   An object of the present invention is to provide a semiconductor element mounting method capable of accurately mounting a protruding electrode of a semiconductor chip on a substrate having wiring electrodes with a narrow pitch.

本発明の請求項１記載の電子部品の実装方法は、突起電極が形成された電子部品を、基板の上に形成された配線電極に電気的に接続して前記基板に前記電子部品を実装するに際し、前記電子部品の前記突起電極が設けられている同じ面に、前記突起電極よりも高い少なくとも２個の位置合わせ突起を形成し、前記突起電極に対応する配線電極を有する前記基板の側には、前記位置合わせ突起の位置にそれぞれ対応して配置され内周面が底部に向かって狭くなるように傾いた斜面を有する凹部を形成し、前記突起電極よりも高い前記位置合わせ突起の先端を、前記基板の前記斜面に当接させて、前記位置合わせ突起を前記凹部の底部中央にガイドして前記電子部品の前記突起電極を前記基板の配線電極に位置合わせすることを特徴とする。   The electronic component mounting method according to claim 1 of the present invention is such that the electronic component on which the protruding electrode is formed is electrically connected to the wiring electrode formed on the substrate, and the electronic component is mounted on the substrate. At the time, at least two alignment protrusions higher than the protrusion electrodes are formed on the same surface of the electronic component on which the protrusion electrodes are provided, and the wiring electrode corresponding to the protrusion electrodes is provided on the side of the substrate. Are formed corresponding to the positions of the alignment protrusions, respectively, and formed with recesses having slopes inclined so that the inner circumferential surface becomes narrower toward the bottom, and the tips of the alignment protrusions higher than the protrusion electrodes are formed. The alignment protrusion is guided to the center of the bottom of the concave portion in contact with the inclined surface of the substrate, and the protrusion electrode of the electronic component is aligned with the wiring electrode of the substrate.

本発明の請求項２記載の電子部品の実装方法は、請求項１において、前記基板の側の凹部は、前記基板の表面よりも窪んでいることを特徴とする。
本発明の請求項３記載の電子部品の実装方法は、請求項１において、前記基板の側の凹部は、前記基板の表面に突出したガイド片で構成されていることを特徴とする。 According to a second aspect of the present invention, there is provided the electronic component mounting method according to the first aspect, wherein the concave portion on the substrate side is recessed from the surface of the substrate.
According to a third aspect of the present invention, there is provided the electronic component mounting method according to the first aspect, wherein the concave portion on the substrate side is constituted by a guide piece protruding from the surface of the substrate.

本発明の請求項４記載の電子部品の実装方法は、請求項１において、前記基板と前記電子部品の間に熱硬化性樹脂を介装して結合することを特徴とする。
本発明の請求項５記載の電子部品の実装方法は、請求項２において、前記基板の前記凹部の形状を、前記基板の一方の面から他方の面に貫通させないことを特徴とする。 According to a fourth aspect of the present invention, there is provided the electronic component mounting method according to the first aspect, wherein a thermosetting resin is interposed between the substrate and the electronic component.
The electronic component mounting method according to claim 5 of the present invention is characterized in that, in claim 2, the shape of the concave portion of the substrate is not penetrated from one surface of the substrate to the other surface.

本発明の請求項６記載の電子部品の実装方法は、請求項２において、前記基板の前記凹部の形状を、前記基板の一方の面から他方の面に貫通させたことを特徴とする。
本発明の請求項７記載の電子部品の実装方法は、請求項６において、前記基板の前記凹部の片側の面を配線電極で閉塞したことを特徴とする。 The electronic component mounting method according to claim 6 of the present invention is characterized in that, in claim 2, the shape of the concave portion of the substrate is penetrated from one surface of the substrate to the other surface.
According to a seventh aspect of the present invention, there is provided the electronic component mounting method according to the sixth aspect, wherein one surface of the concave portion of the substrate is closed with a wiring electrode.

本発明の請求項８記載の電子部品の実装方法は、請求項２において、前記基板に前記配線電極の形成時に、前記基板の前記凹部の周辺と前記斜面のうちの少なくとも一方に電極を形成することを特徴とする。   An electronic component mounting method according to an eighth aspect of the present invention is the method for mounting an electronic component according to the second aspect, wherein the electrode is formed on at least one of the periphery of the concave portion and the inclined surface of the substrate when the wiring electrode is formed on the substrate. It is characterized by that.

本発明の請求項９記載の電子部品の実装方法は、請求項３において、前記基板に前記配線電極の形成時に、前記基板の表面に前記ガイド片としての電極を形成することを特徴とする。   The electronic component mounting method according to claim 9 of the present invention is characterized in that, in claim 3, when the wiring electrode is formed on the substrate, the electrode as the guide piece is formed on the surface of the substrate.

本発明の請求項１０記載の電子部品の実装方法は、請求項１において、前記突起電極が前記基板の前記配線電極に当接した状態で、前記位置合わせ突起に当接する検出電極を前記凹部の底部に形成し、前記位置合わせ突起と前記検出電極との導通から実装状態を判定することを特徴とする。   According to a tenth aspect of the present invention, in the electronic component mounting method according to the first aspect, in the state where the protruding electrode is in contact with the wiring electrode of the substrate, the detection electrode that is in contact with the alignment protrusion is provided in the recess. It is formed on the bottom, and a mounting state is determined from conduction between the alignment protrusion and the detection electrode.

本発明の請求項１１記載の電子部品の実装方法は、請求項１において、前記位置合わせ突起を、前記突起電極よりも少なくとも台座高さ分だけ高くすることを特徴とする。
本発明の請求項１２記載の電子部品の実装方法は、請求項１において、前記位置合わせ突起を、前記突起電極よりも高さが１．４倍以上にすることを特徴とする。 An electronic component mounting method according to an eleventh aspect of the present invention is characterized in that, in the first aspect, the alignment protrusion is made higher than the protrusion electrode by at least a pedestal height.
According to a twelfth aspect of the present invention, there is provided the electronic component mounting method according to the first aspect, wherein the alignment protrusion has a height 1.4 times or more higher than the protrusion electrode.

本発明の請求項１３記載の電子部品の実装方法は、請求項１において、前記位置合わせ突起を、電子部品に矩形状に広がって前記突起電極が配置された突起電極群に対してこの突起電極群を横切る対角位置またはその近傍に配置することを特徴とする。   The electronic component mounting method according to a thirteenth aspect of the present invention is the method for mounting an electronic component according to the first aspect, wherein the alignment protrusion is extended in a rectangular shape on the electronic component and the protruding electrode is arranged on the protruding electrode group. It arrange | positions at the diagonal position which crosses a group, or its vicinity.

本発明の請求項１４記載の電子部品の実装方法は、請求項１において、前記凹部の開口の最大幅は、前記位置合わせ突起の先端径に電気的接続用配線幅の５０％〜１００％未満を加えた幅とすることを特徴とする。   The electronic component mounting method according to a fourteenth aspect of the present invention is the electronic component mounting method according to the first aspect, wherein the maximum width of the opening of the recess is less than 50% to less than 100% of the wiring width for electrical connection to the tip diameter of the alignment protrusion. It is characterized by a width that is added.

本発明の請求項１５記載の電子部品の実装方法は、請求項１において、前記位置合わせ突起を前記凹部の底部中央にガイドして前記電子部品の前記突起電極を前記基板の配線電極に位置合わせして、前記位置合わせ突起を変形させることを特徴とする。   The electronic component mounting method according to a fifteenth aspect of the present invention is the method for mounting an electronic component according to the first aspect, wherein the alignment protrusion is guided to the center of the bottom of the recess to align the protrusion electrode of the electronic component with the wiring electrode of the substrate. Then, the alignment protrusion is deformed.

本発明の請求項１６記載の電子部品の実装方法は、請求項１において、加圧して前記電子部品を前記基板に仮実装して前記電子部品の前記突起電極を前記基板の配線電極に位置合わせし、仮実装した前記電子部品を加熱しながら押圧して前記電子部品と前記基板との間に介装された熱硬化性樹脂を前記電子部品の周辺に押し出しながら硬化させ、前記位置合わせ突起を変形させることを特徴とする。   The electronic component mounting method according to a sixteenth aspect of the present invention is the method for mounting an electronic component according to the first aspect, wherein the electronic component is temporarily mounted on the substrate by applying pressure and the protruding electrode of the electronic component is aligned with the wiring electrode of the substrate. Then, the temporarily mounted electronic component is pressed while being heated, and the thermosetting resin interposed between the electronic component and the substrate is cured while being pushed around the electronic component, and the alignment protrusion is It is characterized by being deformed.

本発明の請求項１７記載の半導体装置は、突起電極が形成された電子部品を、基板の上に形成された配線電極に電気的に接続して実装した半導体装置であって、前記電子部品には、前記突起電極が設けられている同じ面に、前記突起電極よりも高い少なくとも２個の位置合わせ突起を設け、前記基板には、前記位置合わせ突起の位置にそれぞれ対応して配置され内周面が底部に向かって狭くなるように傾いた斜面を有する凹部を設け、前記突起電極が基板の上に形成された配線電極に当接するとともに、前記位置合わせ突起が前記凹部に係合していることを特徴とする。   A semiconductor device according to a seventeenth aspect of the present invention is a semiconductor device in which an electronic component on which a protruding electrode is formed is electrically connected to a wiring electrode formed on a substrate and is mounted on the electronic component. Are provided with at least two alignment protrusions higher than the protrusion electrodes on the same surface on which the protrusion electrodes are provided, and are arranged on the substrate corresponding to the positions of the alignment protrusions, respectively. A recess having a slope inclined so that the surface becomes narrower toward the bottom is provided, the protruding electrode abuts on a wiring electrode formed on the substrate, and the alignment protrusion is engaged with the recess. It is characterized by that.

この構成によると、電子部品の突起電極が設けられている同じ面に、突起電極よりも高い少なくとも２個の位置合わせ突起を形成し、前記突起電極が基板の上に形成された配線電極に当接するとともに、前記位置合わせ突起を前記凹部に係合させて押圧して位置合わせ突起が変形するので、突起電極の位置を基板側の正常な電極位置に自動補正して、突起電極が基板の配線電極に接続されることによって、狭ピッチや微細配線基板への位置ずれ実装（接続）による、信頼性の低下を回避できる。   According to this configuration, at least two alignment protrusions higher than the protrusion electrode are formed on the same surface on which the protrusion electrode of the electronic component is provided, and the protrusion electrode contacts the wiring electrode formed on the substrate. Since the alignment protrusion is deformed by engaging and pressing the alignment protrusion with the recess, the position of the protrusion electrode is automatically corrected to the normal electrode position on the substrate side, and the protrusion electrode is connected to the wiring of the substrate. By being connected to the electrodes, it is possible to avoid a decrease in reliability due to narrow pitch or misaligned mounting (connection) to a fine wiring board.

また、従来の半導体チップの実装時の位置合わせ時にプロセス条件のマージンが多くとれるため、タクトを短くすることも可能で、組み立ても容易になるため、低コスト化が可能になる。具体的には、実装の完了状態における突起電極の高さを揃えることができるので、半導体チップを基板に押し付けて突起電極を塑性変形させる時の実装荷重のばらつきを小さくすることができるので、再現性が良好である。   In addition, since a margin for process conditions can be increased during alignment when mounting a conventional semiconductor chip, the tact can be shortened and the assembly is facilitated, so that the cost can be reduced. Specifically, since the height of the protruding electrode in the completed state of mounting can be made uniform, the variation in mounting load when the semiconductor chip is pressed against the substrate to plastically deform the protruding electrode can be reproduced. Good properties.

以下、本発明の電子部品の実装方法を具体的な各実施の形態に基づいて説明する。
（実施の形態１）
図１〜図４は本発明の実施の形態１を示す。 Hereinafter, an electronic component mounting method of the present invention will be described based on specific embodiments.
(Embodiment 1)
1 to 4 show Embodiment 1 of the present invention.

図２は基板１に電子部品としての半導体チップ２をフリップチップ実装した拡大平面図で、厚みが０．２ｍｍの半導体チップ２の下面には電極群７を構成する電極が、半導体チップ２の外周部に沿って２列で配列されている。   FIG. 2 is an enlarged plan view in which a semiconductor chip 2 as an electronic component is flip-chip mounted on a substrate 1. The electrodes constituting the electrode group 7 are arranged on the lower surface of the semiconductor chip 2 having a thickness of 0.2 mm. It is arranged in two rows along the part.

図３は理解しやすいように図２を切断線Ａ−ＡＡで切断して簡略的に図示した断面図で、電極群７を横切る対角位置の近傍に配置する電極８１，８２を除く各電極９には、突起電極１１が図１（ｂ）に示すように構成されている。電極８１，８２には、突起電極１１よりも高さが高い位置合わせ突起１２が形成されている。突起電極１１と位置合わせ突起１２はともに材質が金である。例えば、突起電極１１の台座２１径は６０μｍである。   FIG. 3 is a cross-sectional view schematically showing FIG. 2 cut along a cutting line A-AA for easy understanding. Each electrode excluding the electrodes 81 and 82 arranged in the vicinity of the diagonal position across the electrode group 7 is shown. 9, the protruding electrode 11 is configured as shown in FIG. The electrodes 81 and 82 are formed with alignment protrusions 12 that are higher than the protrusion electrodes 11. Both the protruding electrode 11 and the alignment protrusion 12 are made of gold. For example, the diameter of the base 21 of the protruding electrode 11 is 60 μm.

この位置合わせ突起１２は、電極９，８１，８２に均一に突起電極１１を形成した後に、電極８１，８２の上にだけ同じ突起電極１１をもう一度ずつ打ち付けることによって実現できる。この場合、位置合わせ突起１２は、突起電極１１より少なくとも台座２１の高さ分だけ高くなる。ここでは、電極８１，８２の場所に、台座２１の直径が突起電極１１の台座径の１．５倍以上、高さが突起電極１１の高さの１．４倍以上の突起電極を重ね打ちして位置合わせ突起１２とした。   The alignment projection 12 can be realized by forming the projection electrode 11 uniformly on the electrodes 9, 81, and 82 and then striking the same projection electrode 11 once again only on the electrodes 81 and 82. In this case, the alignment protrusion 12 is higher than the protrusion electrode 11 by at least the height of the base 21. Here, a protruding electrode having a diameter of the pedestal 21 of 1.5 times or more of the pedestal diameter of the protruding electrode 11 and a height of 1.4 or more of the height of the protruding electrode 11 is overlapped at the location of the electrodes 81 and 82. Thus, the alignment protrusion 12 was obtained.

電極８１，８２は、その他の電極９から電気的に孤立していてもよいし、グランドや電源に繋がっていてもよい。
基板１に半導体チップ２をフリップチップ実装する工程は、図１（ａ）〜図１（ｅ）の工程で実行する。 The electrodes 81 and 82 may be electrically isolated from the other electrodes 9, or may be connected to a ground or a power source.
The step of flip-chip mounting the semiconductor chip 2 on the substrate 1 is performed in the steps of FIGS. 1 (a) to 1 (e).

基板１は材質がガラスエポキシで、その厚みが０．３ｍｍ、実装位置には図１（ｂ）に示すように半導体チップ２の突起電極１１に対応して狭ピッチで形成されている配線電極１３が銅（ニッケル＋Ａｕメッキしてもよい）で形成されている。   The substrate 1 is made of glass epoxy, the thickness is 0.3 mm, and the wiring electrodes 13 are formed at a mounting position at a narrow pitch corresponding to the protruding electrodes 11 of the semiconductor chip 2 as shown in FIG. Is made of copper (may be nickel + Au plated).

なお、基板１には、半導体チップ２の位置合わせ突起１２に対応する位置に、それぞれ凹部１４が形成されている。
この実施の形態の凹部１４は、図１（ａ）に示すように基板１の表面よりも窪ませて形成された平面形状が環状の凹部本体１５と、この凹部本体１５の内側と凹部本体１５の周囲にわたって形成された電極１６とで構成されている。凹部本体１５は内周面が底部に向かって狭くなるように傾いた斜面１７を有しており、この上に形成されている電極１６の表面も斜面１７に沿って傾いている。また、電極１６の基板１の表面に形成されている部分の内周側の角１８も凹部本体１５の中心に向かって傾斜している。このような電極１６は、配線電極１３を形成する工程において形成されている。図４は基板１の要部を示しており、半導体チップ２の実装位置を仮想線で示している。 In the substrate 1, recesses 14 are formed at positions corresponding to the alignment protrusions 12 of the semiconductor chip 2.
As shown in FIG. 1A, the recess 14 of this embodiment has a recess main body 15 having a ring shape that is recessed from the surface of the substrate 1, and the inside of the recess main body 15 and the recess main body 15. And an electrode 16 formed over the periphery of the substrate. The concave body 15 has an inclined surface 17 inclined so that the inner peripheral surface becomes narrower toward the bottom, and the surface of the electrode 16 formed thereon is also inclined along the inclined surface 17. Further, the corner 18 on the inner peripheral side of the portion of the electrode 16 formed on the surface of the substrate 1 is also inclined toward the center of the concave body 15. Such an electrode 16 is formed in the step of forming the wiring electrode 13. FIG. 4 shows the main part of the substrate 1, and the mounting position of the semiconductor chip 2 is indicated by a virtual line.

フリップチップ実装に際しては、基板１の実装位置に熱硬化性エポキシ樹脂１９が液状であればディスペンサーを用いて塗布する。熱硬化性エポキシ樹脂１９がフィルム状であれば貼付装置を使って実装位置に貼り付ける。今回、１５０℃で硬化するフィルム状の熱硬化性エポキシ樹脂１９を５０℃程度１００Ｎで貼り付けを行った。   At the time of flip chip mounting, if the thermosetting epoxy resin 19 is liquid at the mounting position of the substrate 1, it is applied using a dispenser. If the thermosetting epoxy resin 19 is in the form of a film, it is affixed to the mounting position using an affixing device. This time, a film-like thermosetting epoxy resin 19 curable at 150 ° C. was attached at about 50 ° C. and 100 N.

熱硬化性エポキシ樹脂１９の上に、半導体チップ２の突起電極１１を基板１の側に向けて配置し、半導体チップ２の上面に加圧ツールを押し当てて加熱しながら基板１の側に押圧した。   The protruding electrode 11 of the semiconductor chip 2 is disposed on the thermosetting epoxy resin 19 so as to face the substrate 1, and a pressure tool is pressed against the upper surface of the semiconductor chip 2 to heat and press the substrate 1 side. did.

図１（ｂ）に示したように実装位置に対して半導体チップ２の位置がずれていても、位置合わせ突起１２の方が突起電極１１よりも高いため、図１（ｃ）に示すように突起電極１１が配線電極１３に接触する前に、凹部本体１５の斜面１７の上に形成された電極１６に位置合わせ突起１２が当接する。   Even if the position of the semiconductor chip 2 is shifted from the mounting position as shown in FIG. 1B, the alignment protrusion 12 is higher than the protrusion electrode 11, so that as shown in FIG. Before the protruding electrode 11 contacts the wiring electrode 13, the alignment protrusion 12 comes into contact with the electrode 16 formed on the inclined surface 17 of the concave body 15.

凹部本体１５の斜面１７の上に形成された電極１６も凹部本体１５の中心に向かって傾斜しているため、半導体チップ２は図１（ｄ）に示すように凹部本体１５の斜面１７に沿って横ずれしながら降下して、位置合わせ突起１２が凹部本体１５の底部の電極１６に当接する。この時点で突起電極１１は配線電極１３に当接していない。ここで、突起電極１１の高さは例えば５５μｍであった。   Since the electrode 16 formed on the inclined surface 17 of the recessed body 15 is also inclined toward the center of the recessed body 15, the semiconductor chip 2 follows the inclined surface 17 of the recessed body 15 as shown in FIG. The alignment protrusion 12 comes into contact with the electrode 16 at the bottom of the concave body 15. At this time, the protruding electrode 11 is not in contact with the wiring electrode 13. Here, the height of the protruding electrode 11 was 55 μm, for example.

この状態からさらに前記加圧ツールで加熱しながら半導体チップ２を押圧すると、凹部本体１５の底部の電極１６に当接している位置合わせ突起１２が、加圧ツールによる押圧が進むにつれて塑性変形し、半導体チップ２は位置合わせ突起１２の中心Ｂ１が凹部本体１５の中心Ｓ１に近づくように更に横ずれする。この過程で突起電極１１が配線電極１３に当接して図１（ｅ）に示すように塑性変形する。ここで、塑性変形した後の突起電極１１の高さは例えば２５μｍであった。   When the semiconductor chip 2 is further pressed from this state while being heated with the pressure tool, the alignment protrusion 12 that is in contact with the electrode 16 at the bottom of the concave body 15 is plastically deformed as the pressure tool is pressed, The semiconductor chip 2 is further laterally shifted so that the center B1 of the alignment protrusion 12 approaches the center S1 of the concave body 15. In this process, the protruding electrode 11 contacts the wiring electrode 13 and plastically deforms as shown in FIG. Here, the height of the protruding electrode 11 after plastic deformation was, for example, 25 μm.

図１（ｅ）に示す状態で熱硬化性エポキシ樹脂１９が硬化して、基板１と半導体チップ２の位置が固定される。
凹部１４の大きさを、更に詳しく説明する。 In the state shown in FIG. 1E, the thermosetting epoxy resin 19 is cured, and the positions of the substrate 1 and the semiconductor chip 2 are fixed.
The size of the recess 14 will be described in more detail.

Ｃ１は突起電極１１の中心位置、Ｓ２は基板１の配線電極１３の（断面）中心、Ｄ１は凹部１４の半径で、この例では凹部本体１５の表面を電極１６によってメタライズして構成しているため、電極１６の内径がこれに相当する。Ｄ２は配線電極１３の半分の幅であって、
Ｄ１ ＜ Ｄ２
に形成することによって、半導体チップの基板実装時の位置ずれを防止することができる。 C1 is the center position of the protruding electrode 11, S2 is the (cross-sectional) center of the wiring electrode 13 of the substrate 1, D1 is the radius of the concave portion 14, and in this example, the surface of the concave body 15 is metalized by the electrode 16. Therefore, the inner diameter of the electrode 16 corresponds to this. D2 is half the width of the wiring electrode 13,
D1 <D2
By forming in this manner, it is possible to prevent the displacement of the semiconductor chip when mounted on the substrate.

また、基板１に対する半導体チップ２の位置ずれが配線電極１３の半分のＤ２だけ発生した場合であってもこれを自動補正するために必要なＤ１は、位置合わせ突起１２の先端径Ｅ１に配線電極１３の幅Ｄ２を加えた幅とすることにより、位置合わせ突起１２が電極１６の内側に当接する。Ｄ２は配線電極１３の幅の５０％を越えて１００％未満で前記自動補正を期待できる。   Further, even when the position shift of the semiconductor chip 2 with respect to the substrate 1 occurs only by D2 which is half of the wiring electrode 13, D1 necessary for automatically correcting this is the wiring electrode at the tip diameter E1 of the alignment protrusion 12. The alignment protrusion 12 abuts on the inner side of the electrode 16 by adding the width 13 of the width 13. The automatic correction can be expected when D2 exceeds 50% of the width of the wiring electrode 13 and less than 100%.

このように、半導体チップ２の各突起電極１１が基板１の配線電極１３上に接続されることによって、狭ピッチや微細配線基板への位置ずれ実装（接続）による、信頼性の低下を回避することが可能となる。位置合わせ突起１２の高さは突起電極１１の高さの１．４倍以上、位置合わせ突起１２の台座２１の径は突起電極の台座径の１．５倍以上にした場合に好適な結果が得られた。   As described above, each protruding electrode 11 of the semiconductor chip 2 is connected to the wiring electrode 13 of the substrate 1, thereby avoiding a decrease in reliability due to a narrow pitch or misaligned mounting (connection) to a fine wiring substrate. It becomes possible. A suitable result is obtained when the height of the alignment protrusion 12 is 1.4 times or more of the height of the protrusion electrode 11 and the diameter of the base 21 of the alignment protrusion 12 is 1.5 times or more of the base diameter of the protrusion electrode. Obtained.

上記の「電極１６が配線電極１３を形成する工程において形成される」とは、例えば、基板銅箔上にレジストを塗布したのち、電極パターンを写真露光したのち、配線以外の部分レジストを除去し、酸で銅箔をエッチングして行う。エッチングされなかったレジスト部を溶解させて、配線電極を形成する。これをサブトラクト法という。他に、先に配線電極１３のレジストパターンを形成しておき、電解もしくは無電解メッキで銅等を析出させてレジスト厚み分に成長させて配線電極を形成する。これをアディティブ法という。   “The electrode 16 is formed in the step of forming the wiring electrode 13” means, for example, that after applying a resist on the substrate copper foil, the electrode pattern is exposed to a photo, and then the partial resist other than the wiring is removed. Etching the copper foil with acid. The resist part that has not been etched is dissolved to form a wiring electrode. This is called the subtract method. In addition, a resist pattern for the wiring electrode 13 is formed in advance, and copper or the like is deposited by electrolysis or electroless plating and grown to the resist thickness to form the wiring electrode. This is called the additive method.

凹部本体１５の表面に電極１６を形成してメタライズしたため、基板１の材質が位置合わせ突起１２に比べて柔らかな材質の場合であってもこれを補強することができる。また、電極１６と電極８１，８２との導通状態を確認することによって、位置の修正が正しく行われたかどうかを確認できる。   Since the electrode 16 is formed on the surface of the concave body 15 and metallized, the substrate 1 can be reinforced even when the material of the substrate 1 is softer than the alignment protrusion 12. Further, by confirming the conduction state between the electrode 16 and the electrodes 81 and 82, it is possible to confirm whether or not the position has been corrected correctly.

基板４としては、セラミックス基板、樹脂基板、樹脂シート（ポリイミドフレキ）、シリコンの基板でもよい。
また、実装の完了状態における突起電極１１の高さを揃えることができるので、半導体チップ２を基板１に押し付けて突起電極１１を塑性変形させる時の実装荷重のばらつきを小さくすることができるので、再現性が良好である。 The substrate 4 may be a ceramic substrate, a resin substrate, a resin sheet (polyimide flexible), or a silicon substrate.
In addition, since the height of the protruding electrode 11 in the completed state of mounting can be made uniform, variation in mounting load when the semiconductor chip 2 is pressed against the substrate 1 to plastically deform the protruding electrode 11 can be reduced. Good reproducibility.

（実施の形態２）
図５は本発明の実施の形態２を示す。
実施の形態１における凹部１４は、凹部本体１５とこの凹部本体１５の内側と凹部本体１５の周囲にわたって形成された電極１６とで構成されていたが、図５では、電極１６が存在していない。また図５では電極９，８１，８２に均一に突起電極１１を形成した後に、電極８１，８２の上にだけ同じ突起電極１１をもう一度ずつ打ち付けて位置合わせ突起１２を形成した場合を示している。その他は実施の形態１と同じである。 (Embodiment 2)
FIG. 5 shows a second embodiment of the present invention.
The concave portion 14 in the first embodiment is composed of the concave body 15 and the electrode 16 formed over the inside of the concave body 15 and the periphery of the concave body 15, but the electrode 16 does not exist in FIG. 5. . Further, FIG. 5 shows a case in which after the protruding electrodes 11 are uniformly formed on the electrodes 9, 81, 82, the same protruding electrodes 11 are again struck once again only on the electrodes 81, 82 to form the alignment protrusions 12. . The rest is the same as in the first embodiment.

基板１が位置合わせ突起１２に比べて丈夫な材質である場合には、メタライズを必要としない。その他は実施の形態１と同じである。凹部本体１５はドリル加工，レーザー加工，化学的エッチングなどで形成することもできる。   When the substrate 1 is made of a material that is stronger than the alignment protrusion 12, metallization is not required. The rest is the same as in the first embodiment. The recess body 15 can also be formed by drilling, laser processing, chemical etching, or the like.

（実施の形態３）
図６は本発明の実施の形態３を示す。
実施の形態１における凹部１４は、凹部本体１５とこの凹部本体１５の内側と凹部本体１５の周囲にわたって形成された電極１６とで構成されていたが、図６では、電極１６ａが凹部本体１５の底部に設けられており、凹部本体１５の斜面１７と凹部本体１５の周囲には電極１６が存在していない。また図６では電極９，８１，８２に均一に突起電極１１を形成した後に、電極８１，８２の上にだけ同じ突起電極１１をもう一度ずつ打ち付けて位置合わせ突起１２を形成した場合を示している。その他は実施の形態１と同じである。 (Embodiment 3)
FIG. 6 shows a third embodiment of the present invention.
The recess 14 in the first embodiment is composed of the recess body 15 and the electrode 16 formed over the inside of the recess body 15 and the periphery of the recess body 15, but in FIG. The electrode 16 is not provided around the inclined surface 17 of the recess body 15 and the periphery of the recess body 15. Further, FIG. 6 shows a case in which after the protruding electrodes 11 are uniformly formed on the electrodes 9, 81, 82, the same protruding electrodes 11 are once again applied only on the electrodes 81, 82 to form the alignment protrusions 12. . The rest is the same as in the first embodiment.

更に詳しくは、図６における電極１６ａは基板１に内装されている電極を使用することによって、凹部１４の深さを電極１６ａにより正確にコントロールすることができる。
この構成によると、位置合わせ突起１２を凹部本体１５の底部に設けられ電極１６ａによって安定に変形させるこができ、半導体チップ２の突起電極１１を基板１の配線電極１３に位置ずれなく接続できる。 More specifically, the electrode 16a shown in FIG. 6 can be accurately controlled by the electrode 16a by using the electrode built in the substrate 1.
According to this configuration, the alignment protrusion 12 can be stably deformed by the electrode 16 a provided on the bottom of the concave body 15, and the protrusion electrode 11 of the semiconductor chip 2 can be connected to the wiring electrode 13 of the substrate 1 without displacement.

（実施の形態４）
図７は本発明の実施の形態４を示す。
実施の形態１における凹部１４は、凹部本体１５と電極１６とで構成されており、凹部本体１５の内側と凹部本体１５の周囲にわたって形成された電極１６は、基板１に配線電極１３を形成する工程で作成したが、図７では、実施の形態３の図６のように内装電極からなる電極１６ａが底部に設けられた凹部本体１５を有する基板１を作成し、基板１の表面に配線電極１３を形成する工程で、凹部本体１５の斜面１７と凹部本体１５の周囲にわたる電極１６ｂを形成して、電極１６ａと電極１６ｂとを導通させて構成している。また図７では電極９，８１，８２に均一に突起電極１１を形成した後に、電極８１，８２の上にだけ同じ突起電極１１をもう一度ずつ打ち付けて位置合わせ突起１２を形成した場合を示している。その他は実施の形態１と同じである。 (Embodiment 4)
FIG. 7 shows a fourth embodiment of the present invention.
The recess 14 in the first embodiment includes a recess body 15 and an electrode 16, and the electrode 16 formed inside the recess body 15 and around the recess body 15 forms the wiring electrode 13 on the substrate 1. In FIG. 7, the substrate 1 having the concave body 15 with the electrode 16 a made of the interior electrode provided at the bottom is prepared as shown in FIG. 6 of the third embodiment, and the wiring electrode is formed on the surface of the substrate 1. In the step of forming 13, the inclined surface 17 of the concave body 15 and the electrode 16b extending around the concave body 15 are formed, and the electrode 16a and the electrode 16b are electrically connected. Further, FIG. 7 shows a case where after the protruding electrodes 11 are uniformly formed on the electrodes 9, 81, 82, the same protruding electrodes 11 are struck once again only on the electrodes 81, 82 to form the alignment protrusion 12. . The rest is the same as in the first embodiment.

この構成によると、さらに位置合わせ突起１２の変形を安定にすることができる。
（実施の形態５）
図８は本発明の実施の形態５を示す。 According to this configuration, the deformation of the alignment protrusion 12 can be further stabilized.
(Embodiment 5)
FIG. 8 shows a fifth embodiment of the present invention.

図５に示す実施の形態２では凹部１４としての凹部本体１５は基板１を貫通していなかったが、この実施の形態５では図８に示すように基板１を貫通して凹部本体１５ａが形成されている点だけが異なっている。   In the second embodiment shown in FIG. 5, the concave body 15 as the concave portion 14 does not penetrate the substrate 1, but in this fifth embodiment, the concave body 15a is formed through the substrate 1 as shown in FIG. Only the differences are different.

この構成によると、突起電極１１の位置合わせが完了したかどうか、基板１の外側に露出した位置合わせ突起１２を使用して電気的な検査を行うことができる。
（実施の形態６）
図９は本発明の実施の形態６を示す。 According to this configuration, whether or not the alignment of the protruding electrode 11 is completed can be electrically inspected using the alignment protrusion 12 exposed to the outside of the substrate 1.
(Embodiment 6)
FIG. 9 shows a sixth embodiment of the present invention.

図８に示す実施の形態５では凹部本体１５ａが基板１を貫通していたが、この実施の形態６では図９に示すように基板１を貫通した凹部本体１５ａがランド電極２２によって閉塞されており、熱硬化性樹脂１９のはみ出しが無い。その他は実施の形態５と同じである。   In the fifth embodiment shown in FIG. 8, the concave body 15a penetrates the substrate 1, but in this sixth embodiment, the concave body 15a that penetrates the substrate 1 is blocked by the land electrode 22 as shown in FIG. The thermosetting resin 19 does not protrude. The rest is the same as in the fifth embodiment.

（実施の形態７）
図１０は本発明の実施の形態７を示す。
図９に示す実施の形態６では凹部本体１５ａの内周面に電極が形成されていなかったが、この実施の形態７では図１０に示すように、貫通した凹部本体１５ａがランド電極２２によって閉塞された基板１を作成し、基板１の表面に配線電極１３を形成する工程で、凹部本体１５の斜面１７と凹部本体１５の周囲にわたる電極１６ｂを形成して、ランド電極２２と電極１６ｂとを導通させて構成している点だけが異なっている。 (Embodiment 7)
FIG. 10 shows a seventh embodiment of the present invention.
In the sixth embodiment shown in FIG. 9, no electrode is formed on the inner peripheral surface of the concave body 15a. However, in this seventh embodiment, as shown in FIG. 10, the penetrating concave body 15a is blocked by the land electrode 22. In the step of forming the substrate 1 and forming the wiring electrode 13 on the surface of the substrate 1, the inclined surface 17 of the concave body 15 and the electrode 16b extending around the concave body 15 are formed, and the land electrode 22 and the electrode 16b are formed. The only difference is that they are made conductive.

（実施の形態８）
図１１は本発明の実施の形態８を示す。
実施の形態５を示す図８では、突起電極１１と同じ大きさのバンプを重ね打ちして位置合わせ突起１２を構成していたが、図１１では突起電極１１よりも台座径の大きなバンプを１度打ちによって形成している。基板１には大きなシングルの位置合わせ突起１２に応じた径の凹部本体１５が凹部１４として形成されている。
その他は実施の形態５と同じである。 (Embodiment 8)
FIG. 11 shows an eighth embodiment of the present invention.
In FIG. 8 showing the fifth embodiment, bumps having the same size as that of the protruding electrode 11 are overlaid to form the alignment protrusion 12, but in FIG. 11, a bump having a base diameter larger than that of the protruding electrode 11 is 1. It is formed by hitting. A concave body 15 having a diameter corresponding to a large single alignment protrusion 12 is formed as a concave portion 14 on the substrate 1.
The rest is the same as in the fifth embodiment.

なお、位置合わせ突起１２をダブルバンプではなく、図１１のようにシングルで構成する点については、その他の実施の形態においても同様に実施できる。
（実施の形態９）
図１２と図１３は本発明の実施の形態９を示す。 The point that the alignment protrusion 12 is not a double bump but a single as shown in FIG. 11 can be similarly implemented in other embodiments.
(Embodiment 9)
12 and 13 show Embodiment 9 of the present invention.

実施の形態１を示す図１では、基板１の側に設けられた凹部１４は、電極１６と基板１の表面よりも窪ませて形成された凹部本体１５とで構成されていたが、図１２では、位置合わせ突起１２に対応して基板１の表面に形成された電極１６だけで凹部１４が形成されている。電極１６の内周側の角１８は凹部１４の中心に向かって傾斜している。   In FIG. 1 showing the first embodiment, the concave portion 14 provided on the substrate 1 side is composed of the electrode 16 and the concave body 15 formed to be recessed from the surface of the substrate 1. Then, the recess 14 is formed only by the electrode 16 formed on the surface of the substrate 1 corresponding to the alignment protrusion 12. A corner 18 on the inner peripheral side of the electrode 16 is inclined toward the center of the recess 14.

図１２（ａ）に示すように、実装位置に対して半導体チップ２の位置がずれていても、位置合わせ突起１２の方が突起電極１１よりも高いため、加圧ツールで半導体チップ２を押圧すると、図１２（ｂ）に示すように突起電極１１が配線電極１３に接触する前に、電極１６の内周側の傾斜した角１８に位置合わせ突起１２が当接する。   As shown in FIG. 12A, even if the position of the semiconductor chip 2 is shifted from the mounting position, the alignment protrusion 12 is higher than the protrusion electrode 11, so that the semiconductor chip 2 is pressed with a pressure tool. Then, as shown in FIG. 12B, the alignment protrusion 12 contacts the inclined corner 18 on the inner peripheral side of the electrode 16 before the protrusion electrode 11 contacts the wiring electrode 13.

これによって、半導体チップ２は電極１６の内周側の傾斜した角１８に沿って横ずれしながら降下して、位置合わせ突起１２が基板１の表面に当接する。この時点で突起電極１１は配線電極１３に当接していない。   As a result, the semiconductor chip 2 descends while laterally shifting along the inclined corner 18 on the inner peripheral side of the electrode 16, and the alignment protrusion 12 contacts the surface of the substrate 1. At this time, the protruding electrode 11 is not in contact with the wiring electrode 13.

この状態からさらに前記加圧ツールで加熱しながら半導体チップ２を押圧すると、基板１の表面に当接している位置合わせ突起１２が、加圧ツールによる押圧が進むにつれて塑性変形し、半導体チップ２は位置合わせ突起１２の中心が電極１６の中心に近づくように更に横ずれする。この過程で突起電極１１が配線電極１３に当接して図１２（ｃ）に示すように塑性変形する。この状態で熱硬化性エポキシ樹脂１９が硬化して、基板１と半導体チップ２の位置が固定される。   When the semiconductor chip 2 is further pressed from this state while being heated by the pressure tool, the alignment protrusion 12 that is in contact with the surface of the substrate 1 is plastically deformed as the pressure tool is pressed, and the semiconductor chip 2 is The alignment protrusion 12 is further laterally shifted so that the center of the alignment protrusion 12 approaches the center of the electrode 16. In this process, the protruding electrode 11 contacts the wiring electrode 13 and is plastically deformed as shown in FIG. In this state, the thermosetting epoxy resin 19 is cured, and the positions of the substrate 1 and the semiconductor chip 2 are fixed.

（実施の形態１０）
図１４は本発明の実施の形態１０を示す。
図１４（ａ）は基板１の要部の平面図、図１４（ｂ）は図１４（ａ）のＢ−ＢＢ線に沿った断面図である。 (Embodiment 10)
FIG. 14 shows a tenth embodiment of the present invention.
14A is a plan view of the main part of the substrate 1, and FIG. 14B is a cross-sectional view taken along the line B-BB in FIG. 14A.

実施の形態９の凹部１４は平面形状が環状で中央に窪みを有した電極１６であったが、この図１４では、基板１の表面に形成された互いに平行なガイド片２３ａ，２３ｂによってガイド片２３ａ，２３ｂの間に窪みを有する凹部１４が構成されている。ガイド片２３ａ，２３ｂによる凹部１４は、前記半導体チップ２の電極８１，８２に形成された位置合わせ突起１２に対応して基板１に形成されている。ガイド片２３ａ，２３ｂの内側は凹部１４の中央にむかって傾いた斜面２４に形成されている。その他は実施の形態９と同じである。   The concave portion 14 of the ninth embodiment is an electrode 16 having a ring shape in the plane and having a depression in the center. In FIG. 14, the guide piece is formed by the parallel guide pieces 23a and 23b formed on the surface of the substrate 1. A recess 14 having a recess between 23a and 23b is formed. The recesses 14 formed by the guide pieces 23 a and 23 b are formed on the substrate 1 corresponding to the alignment protrusions 12 formed on the electrodes 81 and 82 of the semiconductor chip 2. The inner sides of the guide pieces 23 a and 23 b are formed on an inclined surface 24 inclined toward the center of the recess 14. The rest is the same as in the ninth embodiment.

上記の各実施の形態において、基板４は、セラミックス基板、樹脂基板、樹脂シート（ポリイミドフレキ）、シリコンの基板でもよい。シリコン基板（シリコンインターポーザでもよい）の場合は、貫通孔を専用設備で作製する。貫通孔は一部シリコンで止まっていても、他の電極がメタライズされていてもよい。   In each of the above embodiments, the substrate 4 may be a ceramic substrate, a resin substrate, a resin sheet (polyimide flexible), or a silicon substrate. In the case of a silicon substrate (which may be a silicon interposer), the through hole is produced with dedicated equipment. The through holes may be partially stopped by silicon, or other electrodes may be metallized.

なお、図１，図７，図１０では、凹部本体１５の周辺と斜面１７の両方に電極１６または電極１６，１６ｂを形成してメタライズしたが、少なくとも一方に電極を形成して構成することもできる。   1, 7, and 10, the electrode 16 or the electrodes 16 and 16 b are formed on both the periphery of the concave body 15 and the inclined surface 17, and metallized. However, at least one of the electrodes may be formed. it can.

また、図１５に示した従来例などでは半導体チップ２の突起電極４が、基板１の上に形成された配線電極５の凹部６に必要以上の強固な状態で係合して連結されるので、廃棄された基板１をリサイクルするような場合には、基板１からの半導体チップ２の取り外しが難しいのに対して、本発明の構成ではアンダーフィルとして熱硬化性エポキシ樹脂１９などで連結することによって適度な状態で係合して連結されるので、廃棄された基板１をリサイクルするような場合に半導体チップ２の取り外しが容易で、リサイクル性の点でも優れている。   Further, in the conventional example shown in FIG. 15 and the like, the protruding electrode 4 of the semiconductor chip 2 is engaged and connected to the recess 6 of the wiring electrode 5 formed on the substrate 1 in a stronger state than necessary. When the discarded substrate 1 is recycled, it is difficult to remove the semiconductor chip 2 from the substrate 1, but in the configuration of the present invention, the underfill is connected with a thermosetting epoxy resin 19 or the like. Therefore, when the discarded substrate 1 is recycled, the semiconductor chip 2 can be easily removed and the recyclability is excellent.

本発明は狭ピッチや微細配線基板への位置ずれの回避に寄与することができ、フリップチップ実装した半導体素子を有する半導体装置の小型化にともなって低下する信頼性の低下を改善できる。   INDUSTRIAL APPLICABILITY The present invention can contribute to avoiding a narrow pitch and a position shift to a fine wiring board, and can improve a reduction in reliability which is reduced as a semiconductor device having a semiconductor element mounted with a flip chip is miniaturized.

本発明の実施の形態１の実装工程を示す拡大断面図The expanded sectional view which shows the mounting process of Embodiment 1 of this invention 同実施の形態の拡大平面図Enlarged plan view of the same embodiment 同実施の形態の簡略的な拡大断面図Simplified enlarged sectional view of the same embodiment 同実施の形態の基板の要部の拡大平面図The enlarged plan view of the principal part of the board | substrate of the embodiment 本発明の実施の形態２の簡略的な拡大断面図Simplified enlarged sectional view of Embodiment 2 of the present invention 本発明の実施の形態３の簡略的な拡大断面図Simplified enlarged sectional view of Embodiment 3 of the present invention 本発明の実施の形態４の簡略的な拡大断面図Simplified enlarged sectional view of the fourth embodiment of the present invention. 本発明の実施の形態５の簡略的な拡大断面図Simplified enlarged sectional view of the fifth embodiment of the present invention. 本発明の実施の形態６の簡略的な拡大断面図Simplified enlarged sectional view of the sixth embodiment of the present invention. 本発明の実施の形態７の簡略的な拡大断面図Simplified enlarged sectional view of the seventh embodiment of the present invention. 本発明の実施の形態８の簡略的な拡大断面図Simplified enlarged sectional view of the eighth embodiment of the present invention. 本発明の実施の形態９の実装工程を示す拡大断面図The expanded sectional view which shows the mounting process of Embodiment 9 of this invention 同実施の形態の基板の要部の拡大平面図The enlarged plan view of the principal part of the board | substrate of the embodiment 本発明の実施の形態１０の基板の要部の拡大平面図The enlarged plan view of the principal part of the board | substrate of Embodiment 10 of this invention 従来例の実装工程を示す拡大断面図Expanded sectional view showing the mounting process of the conventional example

符号の説明Explanation of symbols

１ 基板
２ 半導体チップ（電子部品）
７ 電極群
８１，８２，９ 電極
１１ 突起電極
１２ 位置合わせ突起
１３ 配線電極
１４ 凹部
１５ 凹部本体
１６，１６ａ，１６ｂ 電極
１７ 斜面
１８ 電極１６の内周側の角
１９ 熱硬化性エポキシ樹脂
２１ 台座
２２ ランド電極
２３ａ，２３ｂ ガイド片
２４ ガイド片２３ａ，２３ｂの内側の斜面 1 Substrate 2 Semiconductor chip (electronic component)
7 Electrode group 81, 82, 9 Electrode 11 Projection electrode 12 Alignment projection 13 Wiring electrode 14 Recess 15 Recess body 16, 16 a, 16 b Electrode 17 Slope 18 Corner 16 on inner periphery side of electrode 19 Thermosetting epoxy resin 21 Base 22 Land electrode 23a, 23b Guide piece 24 Slope inside guide piece 23a, 23b

Claims (17)

突起電極が形成された電子部品を、基板の上に形成された配線電極に電気的に接続して前記基板に前記電子部品を実装するに際し、
前記電子部品の前記突起電極が設けられている同じ面に、前記突起電極よりも高い少なくとも２個の位置合わせ突起を形成し、
前記突起電極に対応する配線電極を有する前記基板の側には、前記位置合わせ突起の位置にそれぞれ対応して配置され内周面が底部に向かって狭くなるように傾いた斜面を有する凹部を形成し、
前記突起電極よりも高い前記位置合わせ突起の先端を、前記基板の前記斜面に当接させて、前記位置合わせ突起を前記凹部の底部中央にガイドして前記電子部品の前記突起電極を前記基板の配線電極に位置合わせする
電子部品の実装方法。 When mounting the electronic component on the substrate by electrically connecting the electronic component on which the protruding electrode is formed to the wiring electrode formed on the substrate,
Forming at least two alignment protrusions higher than the protrusion electrodes on the same surface of the electronic component on which the protrusion electrodes are provided;
On the side of the substrate having the wiring electrode corresponding to the protruding electrode, a concave portion having a slope inclined so that the inner peripheral surface becomes narrower toward the bottom is formed corresponding to the position of the alignment protrusion. And
The tip of the alignment protrusion higher than the protrusion electrode is brought into contact with the inclined surface of the substrate, and the alignment protrusion is guided to the center of the bottom of the concave portion so that the protrusion electrode of the electronic component is placed on the substrate. A method for mounting electronic components to be aligned with wiring electrodes. 前記基板の側の凹部は、前記基板の表面よりも窪んでいることを特徴とする
請求項１記載の電子部品の実装方法。 The method of mounting an electronic component according to claim 1, wherein the concave portion on the substrate side is recessed from the surface of the substrate. 前記基板の側の凹部は、前記基板の表面に突出したガイド片で構成されていることを特徴とする
請求項１記載の電子部品の実装方法。 2. The electronic component mounting method according to claim 1, wherein the concave portion on the substrate side is constituted by a guide piece protruding from the surface of the substrate. 前記基板と前記電子部品の間に熱硬化性樹脂を介装して結合する
請求項１記載の電子部品の実装方法。 The electronic component mounting method according to claim 1, wherein a thermosetting resin is interposed between the substrate and the electronic component. 前記基板の前記凹部の形状を、前記基板の一方の面から他方の面に貫通させない
ことを特徴とする
請求項２記載の電子部品の実装方法。 The method of mounting an electronic component according to claim 2, wherein the shape of the concave portion of the substrate is not penetrated from one surface of the substrate to the other surface. 前記基板の前記凹部の形状を、前記基板の一方の面から他方の面に貫通させた
ことを特徴とする
請求項２記載の電子部品の実装方法。 3. The electronic component mounting method according to claim 2, wherein the shape of the concave portion of the substrate is penetrated from one surface of the substrate to the other surface. 前記基板の前記凹部の片側の面を配線電極で閉塞した
ことを特徴とする
請求項６記載の電子部品の実装方法。 The electronic component mounting method according to claim 6, wherein one surface of the concave portion of the substrate is closed with a wiring electrode. 前記基板に前記配線電極の形成時に、前記基板の前記凹部の周辺と前記斜面のうちの少なくとも一方に電極を形成する
請求項２記載の電子部品の実装方法。 The electronic component mounting method according to claim 2, wherein an electrode is formed on at least one of a periphery of the recess and the inclined surface of the substrate when the wiring electrode is formed on the substrate. 前記基板に前記配線電極の形成時に、前記基板の表面に前記ガイド片としての電極を形成することを特徴とする
請求項３記載の電子部品の実装方法。 4. The electronic component mounting method according to claim 3, wherein an electrode as the guide piece is formed on the surface of the substrate when the wiring electrode is formed on the substrate. 前記突起電極が前記基板の前記配線電極に当接した状態で、前記位置合わせ突起に当接する検出電極を前記凹部の底部に形成し、前記位置合わせ突起と前記検出電極との導通から実装状態を判定する
請求項１記載の電子部品の実装方法。 In a state where the protruding electrode is in contact with the wiring electrode of the substrate, a detection electrode that is in contact with the alignment protrusion is formed at the bottom of the recess, and the mounting state is determined from the conduction between the alignment protrusion and the detection electrode. The electronic component mounting method according to claim 1, wherein the electronic component mounting method is determined. 前記位置合わせ突起を、前記突起電極よりも少なくとも台座高さ分だけ高くすることを特徴とする請求項１記載の電子部品の実装方法。   2. The electronic component mounting method according to claim 1, wherein the alignment protrusion is made higher than the protrusion electrode by at least a pedestal height. 前記位置合わせ突起を、前記突起電極よりも高さが１．４倍以上にすることを特徴とする
請求項１記載の電子部品の実装方法。 The electronic component mounting method according to claim 1, wherein the alignment protrusion has a height 1.4 times or more than the protrusion electrode. 前記位置合わせ突起を、電子部品に矩形状に広がって前記突起電極が配置された突起電極群に対してこの突起電極群を横切る対角位置またはその近傍に配置する
ことを特徴とする
請求項１記載の電子部品の実装方法。 2. The alignment protrusion is disposed at or near a diagonal position across the protruding electrode group with respect to the protruding electrode group in which the protruding electrode is disposed in a rectangular shape on the electronic component. The electronic component mounting method described. 前記凹部の開口の最大幅は、前記位置合わせ突起の先端径に電気的接続用配線幅の５０％〜１００％未満を加えた幅とすることを特徴とする
請求項１記載の電子部品の実装方法。 2. The electronic component mounting according to claim 1, wherein a maximum width of the opening of the concave portion is a width obtained by adding 50% to less than 100% of a wiring width for electrical connection to a tip diameter of the alignment protrusion. Method. 前記位置合わせ突起を前記凹部の底部中央にガイドして前記電子部品の前記突起電極を前記基板の配線電極に位置合わせして、前記位置合わせ突起を変形させる
請求項１記載の電子部品の実装方法。 The electronic component mounting method according to claim 1, wherein the alignment protrusion is guided to the center of the bottom of the recess to align the protrusion electrode of the electronic component with the wiring electrode of the substrate to deform the alignment protrusion. . 加圧して前記電子部品を前記基板に仮実装して前記電子部品の前記突起電極を前記基板の配線電極に位置合わせし、
仮実装した前記電子部品を加熱しながら押圧して前記電子部品と前記基板との間に介装された熱硬化性樹脂を前記電子部品の周辺に押し出しながら硬化させ、前記位置合わせ突起を変形させる
請求項１記載の電子部品の実装方法。 Applying pressure to temporarily mount the electronic component on the substrate and align the protruding electrode of the electronic component with the wiring electrode of the substrate;
The temporarily mounted electronic component is pressed while being heated, and the thermosetting resin interposed between the electronic component and the substrate is cured while being pushed around the electronic component, thereby deforming the alignment protrusion. The electronic component mounting method according to claim 1. 突起電極が形成された電子部品を、基板の上に形成された配線電極に電気的に接続して実装した半導体装置であって、
前記電子部品には、前記突起電極が設けられている同じ面に、前記突起電極よりも高い少なくとも２個の位置合わせ突起を設け、
前記基板には、前記位置合わせ突起の位置にそれぞれ対応して配置され内周面が底部に向かって狭くなるように傾いた斜面を有する凹部を設け
前記突起電極が基板の上に形成された配線電極に当接するとともに、前記位置合わせ突起が前記凹部に係合している
半導体装置。 A semiconductor device in which an electronic component on which a protruding electrode is formed is mounted by electrically connecting to a wiring electrode formed on a substrate,
The electronic component is provided with at least two alignment protrusions higher than the protrusion electrode on the same surface where the protrusion electrode is provided,
The substrate is provided with a recess having an inclined surface that is arranged corresponding to the position of the alignment protrusion and is inclined so that the inner peripheral surface becomes narrower toward the bottom. The wiring in which the protruding electrode is formed on the substrate A semiconductor device in contact with an electrode and in which the alignment protrusion is engaged with the recess.
JP2006331245A 2006-12-08 2006-12-08 Electronic component mounting method Expired - Fee Related JP4889464B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006331245A JP4889464B2 (en) 2006-12-08 2006-12-08 Electronic component mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006331245A JP4889464B2 (en) 2006-12-08 2006-12-08 Electronic component mounting method

Publications (3)

Publication Number Publication Date
JP2008147317A true JP2008147317A (en) 2008-06-26
JP2008147317A5 JP2008147317A5 (en) 2009-11-05
JP4889464B2 JP4889464B2 (en) 2012-03-07

Family

ID=39607181

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006331245A Expired - Fee Related JP4889464B2 (en) 2006-12-08 2006-12-08 Electronic component mounting method

Country Status (1)

Country Link
JP (1) JP4889464B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011165872A (en) * 2010-02-09 2011-08-25 Renesas Electronics Corp Method of joining bga type semiconductor device
CN102543902A (en) * 2010-12-17 2012-07-04 索尼公司 Semiconductor device and method of manufacturing semiconductor device
WO2014182239A1 (en) * 2013-05-07 2014-11-13 Smartflex Technology Pte Ltd Ultra-thin smart card modules with chip bumps disposed in susbtrate via holes and methods of fabricating the same
EP2819162A1 (en) * 2013-06-24 2014-12-31 Imec Method for producing contact areas on a semiconductor substrate
EP2369617A3 (en) * 2010-03-26 2015-02-25 Fujitsu Limited Semiconductor device and method of manufacturing the same
JP2015149314A (en) * 2014-02-04 2015-08-20 富士通株式会社 Semiconductor device and method of manufacturing the same
CN109309069A (en) * 2018-09-19 2019-02-05 深圳市心版图科技有限公司 Welded ball array encapsulates chip and its welding method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021170582A (en) 2020-04-15 2021-10-28 株式会社村田製作所 Amplifier module

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02170444A (en) * 1988-12-22 1990-07-02 Matsushita Electric Works Ltd Mounting of semiconductor element
JPH03218039A (en) * 1990-01-23 1991-09-25 Sumitomo Electric Ind Ltd Mounting method of semiconductor element
JPH04199524A (en) * 1990-11-28 1992-07-20 Mitsubishi Electric Corp Semiconductor device
JPH05267393A (en) * 1992-03-19 1993-10-15 Nec Corp Semiconductor device and manufacture thereof
JPH10256308A (en) * 1997-03-06 1998-09-25 Oki Electric Ind Co Ltd Structure and method for mounting semiconductor chip
JPH11111772A (en) * 1997-10-07 1999-04-23 Matsushita Electric Ind Co Ltd Method for setting mounting position of carrier board, the carrier board, and wiring board
JPH11163194A (en) * 1997-11-26 1999-06-18 Oki Electric Ind Co Ltd Vlsi package
JP2002246512A (en) * 2001-02-16 2002-08-30 Nec Corp Structure of bga package and structure of mount substrate
JP2002373914A (en) * 2001-06-15 2002-12-26 Ricoh Co Ltd Electronic component connection structure
JP2006324577A (en) * 2005-05-20 2006-11-30 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method thereof

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02170444A (en) * 1988-12-22 1990-07-02 Matsushita Electric Works Ltd Mounting of semiconductor element
JPH03218039A (en) * 1990-01-23 1991-09-25 Sumitomo Electric Ind Ltd Mounting method of semiconductor element
JPH04199524A (en) * 1990-11-28 1992-07-20 Mitsubishi Electric Corp Semiconductor device
JPH05267393A (en) * 1992-03-19 1993-10-15 Nec Corp Semiconductor device and manufacture thereof
JPH10256308A (en) * 1997-03-06 1998-09-25 Oki Electric Ind Co Ltd Structure and method for mounting semiconductor chip
JPH11111772A (en) * 1997-10-07 1999-04-23 Matsushita Electric Ind Co Ltd Method for setting mounting position of carrier board, the carrier board, and wiring board
JPH11163194A (en) * 1997-11-26 1999-06-18 Oki Electric Ind Co Ltd Vlsi package
JP2002246512A (en) * 2001-02-16 2002-08-30 Nec Corp Structure of bga package and structure of mount substrate
JP2002373914A (en) * 2001-06-15 2002-12-26 Ricoh Co Ltd Electronic component connection structure
JP2006324577A (en) * 2005-05-20 2006-11-30 Matsushita Electric Ind Co Ltd Semiconductor device and manufacturing method thereof

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011165872A (en) * 2010-02-09 2011-08-25 Renesas Electronics Corp Method of joining bga type semiconductor device
EP2369617A3 (en) * 2010-03-26 2015-02-25 Fujitsu Limited Semiconductor device and method of manufacturing the same
US9318426B2 (en) 2010-03-26 2016-04-19 Fujitsu Limited Semiconductor device and method of manufacturing the same
CN102543902A (en) * 2010-12-17 2012-07-04 索尼公司 Semiconductor device and method of manufacturing semiconductor device
WO2014182239A1 (en) * 2013-05-07 2014-11-13 Smartflex Technology Pte Ltd Ultra-thin smart card modules with chip bumps disposed in susbtrate via holes and methods of fabricating the same
EP2819162A1 (en) * 2013-06-24 2014-12-31 Imec Method for producing contact areas on a semiconductor substrate
US10332850B2 (en) 2013-06-24 2019-06-25 Imec Method for producing contact areas on a semiconductor substrate
JP2015149314A (en) * 2014-02-04 2015-08-20 富士通株式会社 Semiconductor device and method of manufacturing the same
CN109309069A (en) * 2018-09-19 2019-02-05 深圳市心版图科技有限公司 Welded ball array encapsulates chip and its welding method

Also Published As

Publication number Publication date
JP4889464B2 (en) 2012-03-07

Similar Documents

Publication Publication Date Title
JP4889464B2 (en) Electronic component mounting method
US8697492B2 (en) No flow underfill
JP4988843B2 (en) Substrate and process for semiconductor flip chip packages
JP5606695B2 (en) Board with connection terminal
JP5713598B2 (en) Socket and manufacturing method thereof
JP2010277829A (en) Substrate having connection terminal
JP5788166B2 (en) Connection terminal structure, manufacturing method thereof, and socket
US8698311B2 (en) Package substrate and semiconductor package including the same
WO2018220998A1 (en) Semiconductor device and manufacturing method for semiconductor device
US7893550B2 (en) Semiconductor package comprising alignment members
US7315086B2 (en) Chip-on-board package having flip chip assembly structure and manufacturing method thereof
JP3878436B2 (en) Wiring board and semiconductor device
EP3301712A1 (en) Semiconductor package assembley
JPH11340277A (en) Semiconductor chip loading substrate, semiconductor device and method for loading semiconductor chip to semiconductor chip loading substrate
JP5794833B2 (en) Connection terminal, manufacturing method thereof, and socket
JPH11121524A (en) Semiconductor device
JP2005353854A (en) Wiring board and semiconductor device using the same
US10483195B2 (en) Resin board, method of manufacturing resin board, circuit board, and method of manufacturing circuit board
CN216120289U (en) Electronic device
KR100791575B1 (en) Semiconductor device of tape carrier type
JP4010615B2 (en) Semiconductor device
JP2003273148A (en) Flip chip mounting method
JP2003243447A (en) Method of mounting semiconductor element
JPH09246331A (en) Manufacture of semiconductor device and wire pattern film using it
JPH06209065A (en) Electronic component mounting device

Legal Events

Date Code Title Description
RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20080430

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090903

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090903

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091014

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110823

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110830

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111026

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20111115

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20111213

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20141222

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees