JPH11163194A - Vlsi package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a VSLI package which is high in connection reliability with respect to a motherboard and provided with pins that are disposed in a two-dimensional arrangement. SOLUTION: Aligning pins 21 are each bonded to PKG I/O pads 14' formed on the underside of a PKG board 13 near apexes. The aligning pins 21 are inserted into aligning pin insertion holes 22 bored in a motherboard 16 at prescribed positions, whereby a package 10 is aligned with the motherboard 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a VLSI package in which pins are two-dimensionally arranged on the lower surface of a package.

[0002]

2. Description of the Related Art With the recent increase in the integration of VLSIs, the number of pins in a package has been increased. Therefore, as a form of a package in which more pins can be arranged while keeping the package size small, a BGA (ball grid
An array is used in which pins are two-dimensionally arranged on the lower surface of the package, such as a package.

FIG. 4 is a side view showing an example of the structure of a conventional BGA package. In the BGA package 50,
The IC chip 51 is connected to a package (hereinafter, referred to as PKG) substrate 53 via an IC chip connection solder bump 52. The IC chip 51 is resin-sealed with a mold resin 58. IC chip 51
A plurality of PKG I / O pads 54 are provided on the back of the surface of the PKG substrate 53 connected to the IC chip 51 on which the IC chip 51 is mounted.
Are formed. These PKG I / O pads 54
Is a motherboard I / O formed on a motherboard (substrate) 56 via solder bumps 55 for PKG I / O connection.
They are connected to O pads 57, respectively.

When mounting the BGA package 50 on the motherboard 56, first, the positions of the respective PKG I / O pads 54 and the respective motherboard I / O pads 57 to be connected to the respective PKG I / O pads 54 are set. After the PKG substrate 53 is positioned with respect to the motherboard 56 by alignment or the like so that the position of
The G substrate 53 is temporarily fixed by a temporary fixing jig or the like. And
By melting these PKG I / O connection solder bumps 55 by a reflow method or the like, each PKGI / O
The pad 54 and each motherboard I / O pad 57 are connected.

[0005]

As described above, when the BGA package 50 having the conventional structure is mounted on the motherboard 56, the positioning of the PKG board 53 with respect to the motherboard 56 is visually performed. For this reason, when the BGA package 50 in which the variation in the size of the PKG substrate 53 is relatively large
There has been a problem that the position of the GI / O pad 54 and the position of each motherboard I / O pad 57 are shifted from each other, resulting in poor connection between the pads.

A VLSI package in which pins are two-dimensionally arranged on the surface of a package, such as a BGA package 50, is composed of a BGA package 50 and a motherboard 56.
The connection between the PGA I / O pad 54 and the motherboard I / O pad 57 cannot be visually inspected because the connection between the PKG I / O pad 54 and the motherboard I / O pad 57 is hidden behind the BGA package 50 itself. Therefore, conventionally, the connection between the PKG I / O pad 54 and the motherboard I / O pad 57 has been confirmed by appearance check by X-ray transmission or the like. With such a check method based on the appearance, a sufficient connection check cannot be performed, and it has been difficult to sufficiently secure the reliability of the VLSI package.

It is an object of the present invention to provide a VLSI package in which pins are two-dimensionally arranged on the lower surface of the package and which can be connected to a motherboard with high reliability.

[0008]

According to a first aspect of the present invention, there is provided a VLSI package comprising:
A package substrate for mounting an IC chip, a plurality of external connection terminals formed two-dimensionally on the surface of the package substrate, and the package for connecting each electrode of the IC chip to each of the external connection terminals The wiring in the package formed in the substrate and the substrate of each of the external connection terminals are inserted into holes drilled at predetermined positions of the substrate on which the substrate-side connection terminals connected to the external connection terminals are formed. And a plurality of alignment pins formed on the package substrate for adjusting connection positions to the side connection terminals.

That is, by inserting a plurality of positioning pins formed on the package substrate into holes formed on the substrate, the positioning of the VLSI package on the substrate can be performed more accurately than before. For this reason,
The reliability of connection of the VLSI package to the substrate can be improved.

In the case where such a VLSI package is used, it is preferable that each of the positioning pins is formed near an end of the surface of the package substrate.

Further, the second embodiment of the VLSI package of the present invention
In the aspect, the package substrate for mounting the IC chip, a plurality of external connection terminals formed two-dimensionally on the surface of the package substrate, and each electrode of the IC chip and each of the external connection terminals are connected. Wiring in the package formed in the package substrate, and a terminal connected to the external connection terminal via the wiring in the package, on a surface of the package substrate on which the external connection terminal is not formed. And a formed connection monitor terminal.

That is, in the VLSI package according to the second aspect, the connection monitor terminal electrically connected to the external connection terminal via the wiring in the package is formed on the package substrate. By connecting a measuring device to this connection monitor terminal, it is possible to directly electrically check the connection between the external connection terminal and the external circuit. Therefore,
The reliability of connection of the VLSI package to the substrate can be improved.

When such a VLSI package is used, the connection monitor terminals may be formed corresponding to the external connection terminals.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. <First Embodiment> FIG. 1 is a side view of a VLSI package according to a first embodiment of the present invention. FIG. 2 shows FIG.
5 is a bottom view of the VLSI package shown in FIG. FIGS. 1 and 2 show the structure of the BGA package.

The BGA package 10 according to the first embodiment includes:
An IC chip 11 and a PKG substrate 13 are provided. I
The C chip 11 is connected to the upper surface of the PKG substrate 13 via the IC chip connection solder bumps 12. The IC chip 11 and the solder bump 1 for connecting the IC chip
2 is sealed with a mold resin 18 and fixed on the PKG substrate 13. Lower surface of PKG substrate 13 (I
On the surface on which the C chip 11 is not fixed), a plurality of PKG I / O pads 14 as external connection terminals are formed by an Al pattern. The IC chip 11 and each of the PKG I / O pads 14 are electrically connected by a PKG wiring (not shown) formed inside the PKG substrate 13.

Each PKG I / O pad 14 is formed in a grid pattern over the entire back surface of the PKG substrate 13 as shown in FIG. And each PKG I / O pad 1
On P4, solder bumps 15 for PKG I / O connection are formed. Of these PKG I / O pads 14, four PKG I / O pads 14 'formed on the surface near the apex of the PKG substrate 13 have a PK
Alignment pins 21 are bonded instead of the GI / O connection solder bumps 15, respectively. Note that this PK
Description of the wiring inside the G substrate 13 is omitted.

On the surface of the motherboard 16 on which the BGA package 10 and other chips are mounted, each PKG I /
Motherboard I / O pads 17 (substrate-side connection terminals) for connection to the O-pads 14 are formed by Al patterns, respectively. These motherboard I / O pads 17 are also provided on PKGI /
Like the O pad 14, it is formed in a grid on the surface of the motherboard 16. In addition, each of these motherboards I
/ O pad 17 is a solder bump 1 for PKG I / O connection
5 are connected to the respective PKG I / O pads 14.

Further, four alignment pin insertion holes 22 formed in a cylindrical shape are formed through the mother board 16. When each positioning pin 21 is inserted into each of the positioning pin insertion holes 22, each PKG I /
Position of O pad 14 and each motherboard I / O pad 17
The positions where the positioning pin insertion holes 22 are formed on the motherboard 16 are determined so that the positions of the positioning pin insertion holes 22 exactly overlap. In each of these positioning pin insertion holes 22,
The positioning pins 21 provided on the package body 10 are respectively inserted. Then, each positioning pin 2 penetrating through each positioning pin insertion hole 22 of the motherboard 16.
The front end of the motherboard 1 is fixed by an adhesive 23 for fixing.
6 is fixed to the back surface (the surface on which the BGA package 10 is not mounted).

Hereinafter, the BGA package 1 of the first embodiment will be described.
Next, a procedure for mounting 0 on the motherboard 16 will be described. First, after aligning the orientation of the PKG board 13 and the motherboard 16, the positioning pins 21 of the PKG board 13 are inserted into the respective positioning pin insertion holes 22 of the motherboard 16, so that the PKG board 13 and the motherboard 17 are separated. Temporarily fix. And each PKG I / O
The solder bumps 15 for PKG I / O connection formed on the pads 14 are melted by a reflow method or the like, and each PKG is melted.
The I / O pad 14 and each motherboard I / O pad 17 are connected to each other. After that, the tip of the positioning pin 21 inserted into the positioning pin insertion hole 22 is fixed to the back surface of the motherboard 16 with a fixing adhesive 23.

As described above, according to the first embodiment, the PK
Four PKGs formed near the apex on the lower surface of the G substrate 13
Alignment pin 2 glued on I / O pad 14 '
1 is inserted into each of the four positioning pin insertion holes 22 formed in the motherboard 16, whereby P
The KG board 13 and the motherboard 16 are aligned. This allows the BGA package 10 to be attached to the motherboard 16 without performing visual alignment as in the conventional case.
PKG I / O pad 1
4 and the motherboard I / O pad 17 are more accurately aligned. Therefore, it is possible to prevent the occurrence of connection failure between these pads, and it is possible to improve the connection reliability between the BGA package 10 and the motherboard 16 as compared with the related art.

<Second Embodiment> VLSI of Second Embodiment
The package has a connection monitor pad formed on the upper surface of the PKG board, which can directly and electrically check a connection state between each PKG I / O pad and the motherboard I / O pad after being mounted on the motherboard. It is characterized by.

FIG. 3 shows a VL according to a second embodiment of the present invention.
It is a longitudinal section of an SI package. The VLSI package of the present embodiment also illustrates a BGA package as an example, as in the first embodiment. Hereinafter, the VLSI package of the second embodiment will be described.

The BGA package 30 of the present embodiment
A C chip 31 and a PKG substrate 33 are provided. As in the first embodiment, the IC chip 31 is connected to the upper surface of the PKG substrate 32 via the IC chip connection solder bumps 32 and is sealed with the mold resin 38. This PK
A plurality of PKs, which are external connection terminals, are
The G I / O pad 34 is formed by an Al pattern, and is connected via a solder bump 35 for PKG I / O connection.
Motherboard I / O pad 37 on motherboard 36
Connected to each other.

PKG board 3 on which IC chip 31 is mounted
Further, the same number of connection monitor pads 41 as the number of PKG I / O pads 34 are formed on the upper surface of Al by an Al pattern (only a part thereof is shown in FIG. 3). Also, vias (holes for wiring) are formed in the PKG substrate 33, and the IC chip 31 and each PKG I are formed by the wiring 42 in the PKG formed in the via.
/ O pad 34 is electrically connected. The PKG wiring 42 connected to each of the PKG I / O pads 34 is branched, and a part of the branched PKG wiring 42 is connected to each connection monitor pad 41 formed on the PKG substrate 33. I have. That is, motherboard I / O
The connection portion between the pad 37 and the PKG I / O pad 34 is in a state of being probed to the connection monitor pad 41 via the PKG wiring 42.

Hereinafter, the BGA package 30 of this embodiment will be described.
A method for checking the connection between the pads when the is mounted on the motherboard 36 will be described. First, after aligning the mounting position of the PKG substrate 33 with respect to the motherboard 36, the solder bumps 35 for PKG I / O connection are melted by a reflow method or the like, and the respective PKG I / O pads 3 are melted.
4 and each motherboard I / O pad 37 are connected. As described above, in the BGA package 30, the connection portion of each pad to the motherboard 36 is hidden by the BGA package 30 itself, so that it is impossible to visually check the connection.

Therefore, the connection monitor pad 41 formed on the upper surface of the PKG substrate 33 on which the IC chip 31 is mounted is connected to a measuring instrument, and the TDR function of a network analyzer or the like is used to check these connection portions electrically. Do it.

As described above, according to the second embodiment, the PK
By forming the connection monitor pad 41 electrically connected to the PKGI / O pad 34 via the G substrate wiring 42 on the upper surface of the PKG substrate 33, the electric resistance (impedance) of the connection portion between the pads is formed. Can be measured directly. Therefore, the connection check can be performed more reliably than before, and the connection reliability of the package is improved.

<Modifications> Various modifications can be made to the above-described embodiments. For example, in the first embodiment, the number of the alignment pins 21 connected to the PKG substrate 13 and the number of the alignment pin insertion holes 22 formed in the motherboard 16 may be 2 or 3, or 5 or more, respectively. good.

In the second embodiment, the number of connection monitor pads 41 formed on the IC chip mounting surface 33a of the PKG substrate 33 is the same as the number of the PKG I / O pads 34. However, the present invention is not limited to this. I / O pad 3
The connection monitor pads 41 may be connected to only some of the PKG I / Os 4, and the connection check may be performed for each of these PKG I / O pads 34.

Further, by combining the first embodiment and the second embodiment of the present invention, it is also possible to provide both the positioning pin 21 and the connection monitor pad 41. In addition,
In each of the embodiments, the BGA package has been described. However, the CSP (chip scale package, μ-BG
A), LGA (land grid array), surface mount PGA
(Pin grid array), other VLS of two-dimensional pin array
It can also be applied to I packages.

[0031]

According to the present invention, it is possible to provide a VLSI package with high connection reliability to a motherboard.

[Brief description of the drawings]

FIG. 1 is a side view of a VLSI package according to a first embodiment of the present invention.

FIG. 2 is a bottom view of the VLSI package of FIG. 1;

FIG. 3 is a longitudinal sectional view of a VLSI package according to a second embodiment of the present invention.

FIG. 4 is a side view of a conventional VLSI package.

[Description of Signs] 10, 30, 50 BGA package 11, 31, 51 IC chip 12, 32, 52 Solder bump for connecting IC chip 13, 33, 53 PKG board 14, 14 ', 34, 54 PKG I / O pad 15, 35, 55 PKG I / O connection solder bumps 16, 36, 56 Motherboard 17, 37, 57 Motherboard I / O pad 18, 38, 58 Mold resin 21 Alignment pin 22 Alignment pin insertion hole 41 Connection monitor Pad 42 PKG wiring

Claims (4)

[Claims] 1. A package substrate for mounting an IC chip, a plurality of external connection terminals formed two-dimensionally on a surface of the package substrate, and a connection between each electrode of the IC chip and each of the external connection terminals. The wiring in the package formed in the package substrate and the external connection terminals are inserted into holes formed at predetermined positions of the substrate on which the substrate side connection terminals are formed. A plurality of alignment pins formed on the package substrate for adjusting connection positions of the connection terminals to the board-side connection terminals.
LSI package. 2. The VLSI package according to claim 1, wherein each of said positioning pins is formed near an end of said package substrate surface. 3. A package substrate for mounting an IC chip, a plurality of external connection terminals formed two-dimensionally on the surface of the package substrate, and a connection between each electrode of the IC chip and each of the external connection terminals. And a terminal connected to the external connection terminal via the package internal wiring, wherein the external connection terminal of the package substrate is not formed. And a connection monitor terminal formed on the VLSI package. 4. The connection monitor terminal according to claim 3, wherein said connection monitor terminal is formed corresponding to said external connection terminal.
VLSI package as described.