JPH11121524A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH11121524A JPH11121524A JP9287393A JP28739397A JPH11121524A JP H11121524 A JPH11121524 A JP H11121524A JP 9287393 A JP9287393 A JP 9287393A JP 28739397 A JP28739397 A JP 28739397A JP H11121524 A JPH11121524 A JP H11121524A
- Authority
- JP
- Japan
- Prior art keywords
- interposer
- motherboard
- downward
- insulating substrate
- convex
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
- H01L2924/15156—Side view
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置に係り、
特に半導体べアチップがインターポーザを介してマザー
ボードに実装されている半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device in which a semiconductor bear chip is mounted on a motherboard via an interposer.
【０００２】[0002]
【従来の技術】従来の半導体べアチップがインターポー
ザに搭載されている半導体パッケージは、例えばＢＧＡ
（Ball Grid Array ）やＣＳＰ（Chip Size Package ）
等のように、ボンディング法を用いて半導体ベアチップ
からインターポーザにワイヤ配線したり、半導体ベアチ
ップをインターポーザにフリップチップ実装したりして
作製するのが一般的である。そして、この半導体パッケ
ージのインターポーザ底面に配置されたバンプ電極とマ
ザーボード上面に配置されたランドとの位置合わせを行
った後、両者を接合して、半導体パッケージをマザーボ
ードに実装している。このようにして、従来の半導体べ
アチップがインターポーザを介してマザーボードに実装
されている半導体装置が作製される。2. Description of the Related Art A semiconductor package in which a conventional semiconductor bear chip is mounted on an interposer is, for example, a BGA.
(Ball Grid Array) and CSP (Chip Size Package)
It is common to wire the semiconductor bare chip to the interposer by using a bonding method, or to flip-chip mount the semiconductor bare chip on the interposer, as described above. Then, after positioning the bump electrodes arranged on the bottom surface of the interposer of the semiconductor package with the lands arranged on the top surface of the motherboard, the two are joined to mount the semiconductor package on the motherboard. In this manner, a semiconductor device in which a conventional semiconductor bear chip is mounted on a motherboard via an interposer is manufactured.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記従
来の半導体べアチップがインターポーザを介してマザー
ボードに実装されている半導体装置においては、半導体
パッケージをマザーボードに実装する際に、半導体パッ
ケージのインターポーザ底面のバンプ電極とマザーボー
ド上面のランドとを精度よく位置合わせすることが必要
となり、この位置合わせが良好でない場合には、接続不
良や信頼性の低下を招くことになる。However, in a semiconductor device in which the conventional semiconductor bear chip is mounted on a motherboard via an interposer, when the semiconductor package is mounted on the motherboard, a bump on the bottom surface of the interposer of the semiconductor package is required. It is necessary to accurately align the electrodes with the lands on the upper surface of the motherboard. If the alignment is not good, poor connection or reduced reliability will be caused.
【０００４】そして、こうした半導体パッケージをマザ
ーボードに実装する際の必要搭載精度は、電子機器の高
性能化・小型化による超小型パッケージ化や実装密度の
高度化の進展に伴って、更に高度なものが要求されるよ
うになってきている。従って、半導体パッケージをマザ
ーボードに実装する際には、精度のよい位置合わせが要
求され、そのために実装のスループットが低下するとい
う問題が生じる。[0004] The mounting accuracy required when mounting such a semiconductor package on a motherboard is becoming more and more advanced with the development of ultra-small packages and higher mounting densities due to higher performance and smaller electronic devices. Is being required. Therefore, when the semiconductor package is mounted on the motherboard, accurate positioning is required, which causes a problem that mounting throughput is reduced.
【０００５】また、逆に、こうした位置合わせを容易に
して、半導体パッケージをマザーボードに実装する際の
スループットを向上させようとすると、現状において
は、半導体パッケージのインターポーザ底面のバンプ電
極やマザーボード上面のランドのピッチをラフにするし
かなく、そのために超小型パッケージ化や実装密度の高
度化に逆行するという問題が生じる。On the other hand, in order to improve the throughput when mounting the semiconductor package on the motherboard by facilitating such positioning, at present, the bump electrodes on the bottom surface of the interposer of the semiconductor package and the lands on the top surface of the motherboard are required. Has to be roughened, which causes a problem that goes against ultra-compact package and higher packaging density.
【０００６】そこで本発明は、上記問題点を鑑みてなさ
れたものであり、半導体べアチップをインターポーザを
介してマザーボードに実装する際に、精度の高い位置合
わを容易に行うことが可能になり、実装のスループット
を向上させると共に、接続不良等を防止して高い信頼性
を得ることができる半導体装置を提供することを目的と
する。Accordingly, the present invention has been made in view of the above problems, and it is possible to easily perform highly accurate alignment when mounting a semiconductor bare chip on a motherboard via an interposer. It is an object of the present invention to provide a semiconductor device capable of improving mounting throughput and preventing a connection failure or the like to obtain high reliability.
【０００７】[0007]
【課題を解決するための手段】上記課題は、以下の本発
明に係る半導体装置により達成される。即ち、請求項１
に係る半導体装置は、半導体べアチップがインターポー
ザを介してマザーボードに実装されている半導体装置で
あって、インターポーザが、平坦な上面と下向きに階段
状に凸形状をなしている底面をもつ第１の絶縁基板と、
この第１の絶縁基板の上面上に配列され、半導体べアチ
ップの電極と接合されている第１のランドと、第１の絶
縁基板を貫通して、第１のランドから第１の絶縁基板の
底面の階段状の平坦部に至るスルーホール配線とを有し
ており（以下、このようなインターポーザを「下向き階
段状凸形インターポーザ」と呼ぶ）、マザーボードが、
下向き階段状凸形インターポーザの下向きに階段状に凸
形状をなしている底面に対応して、階段状に凹形状をな
している上面をもつ第２の絶縁基板と、この第２の絶縁
基板中に積層されて形成されている複数の配線パターン
と、第２の絶縁基板の上面の階段状の平坦部に露出して
いる配線パターンからなる第２のランドとを有しており
（以下、このようなマザーボードを「階段状凹形マザー
ボード」と呼ぶ）、下向き階段状凸形インターポーザの
下向きに階段状に凸形状をなしている底面が、階段状凹
形マザーボードの階段状に凹形状をなしている上面に嵌
め込まれて、下向き階段状凸形インターポーザのスルー
ホール配線の下端部が、階段状凹形マザーボードの第２
のランドに接合されていることを特徴とする。The above object is achieved by the following semiconductor device according to the present invention. That is, claim 1
Is a semiconductor device in which a semiconductor bear chip is mounted on a motherboard via an interposer, wherein the interposer has a flat top surface and a bottom surface having a stepwise downwardly convex shape. An insulating substrate;
A first land arranged on the upper surface of the first insulating substrate and joined to the electrode of the semiconductor bear chip; and a first land penetrating through the first insulating substrate and extending from the first land to the first insulating substrate. And a through-hole wiring reaching a stepped flat portion on the bottom surface (hereinafter, such an interposer is referred to as a “downward stepped convex interposer”), and the motherboard has
A second insulating substrate having a stepped concave upper surface corresponding to the downward stepped convex bottom surface of the downward stepped convex interposer; And a second land made of a wiring pattern exposed on a stepped flat portion on the upper surface of the second insulating substrate (hereinafter, referred to as the Such a motherboard is referred to as a “stepped concave motherboard”), a downwardly stepped convex interposer having a downwardly stepped, convexly shaped bottom surface, and a steppedly concave motherboard having a steppedly concave shape. The lower end of the through-hole wiring of the stepped convex interposer facing downward is connected to the second step of the stepped concave motherboard.
Characterized by being joined to the land.
【０００８】このように請求項１に係る半導体装置にお
いては、下向き階段状凸形インターポーザの底面の階段
状の凸形状と階段状凹形マザーボードの上面の階段状の
凹形状とが互いに対応して、下向き階段状凸形インター
ポーザの底面が階段状凹形マザーボードの上面にすっぽ
り嵌め込まれるようになっていることにより、平坦な上
面上に半導体べアチップを搭載した下向き階段状凸形イ
ンターポーザを、第２の絶縁基板中に複数の配線パター
ンが積層されている多層配線構造をなす階段状凹形マザ
ーボードに実装する際に、その位置合わを精度よく且つ
容易に行うことが可能になる。このため、半導体べアチ
ップを下向き階段状凸形インターポーザを介して階段状
凹形マザーボードに実装する際のスループットが向上す
ると共に、接続不良等が防止されて信頼性も向上する。As described above, in the semiconductor device according to the first aspect, the step-like convex shape on the bottom surface of the downward step-like convex interposer and the step-like concave shape on the upper surface of the step-like concave motherboard correspond to each other. The bottom surface of the step-shaped convex interposer is fitted into the top surface of the step-shaped concave motherboard completely, so that the step-shaped convex interposer having the semiconductor bear chip mounted on the flat top surface is formed in the second step. When mounting on a stepped concave motherboard having a multilayer wiring structure in which a plurality of wiring patterns are stacked on an insulating substrate, the positioning can be performed accurately and easily. For this reason, the throughput when the semiconductor bare chip is mounted on the step-shaped concave motherboard via the downward step-shaped convex interposer is improved, and a connection failure or the like is prevented to improve reliability.
【０００９】また、請求項２に係る半導体装置は、上記
請求項１に係る半導体装置において、下向き階段状凸形
インターポーザのスルーホール配線の下端部と階段状凹
形マザーボードの第２のランドとがはんだ又は異方性導
電樹脂や圧接によって接続されている構成とすることに
より、下向き階段状凸形インターポーザのスルーホール
配線と階段状凹形マザーボードの第２のランドとの電気
的接続が安定して確保される。このため、接続不良等が
確実に防止されて信頼性が更に向上する。According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the lower end of the through-hole wiring of the downward step-shaped convex interposer and the second land of the step-shaped concave motherboard are provided. By using a configuration in which the connection is made by solder or anisotropic conductive resin or pressure welding, the electrical connection between the through-hole wiring of the downward step-shaped convex interposer and the second land of the step-shaped concave motherboard is stabilized. Secured. For this reason, connection failure and the like are reliably prevented, and the reliability is further improved.
【００１０】また、請求項３に係る半導体装置は、上記
請求項１に係る半導体装置において、下向き階段状凸形
インターポーザの下向きに階段状に凸形状をなしている
底面と階段状凹形マザーボードの階段状に凹形状をなし
ている上面との間に所定の樹脂が充填されている構成と
することにより、この樹脂によって下向き階段状凸形イ
ンターポーザが階段状凹形マザーボード上に固定される
ため、両者の位置ずれやそれに伴う接続不良等が防止さ
れて信頼性が更に向上する。According to a third aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the bottom surface of the downwardly stepped convex interposer has a downwardly stepped convex shape and a stepped concave motherboard. By having a configuration in which a predetermined resin is filled between the upper surface and the stepped concave shape, the downward stepped convex interposer is fixed on the stepped concave motherboard by this resin, The displacement between the two and the resulting connection failure are prevented, and the reliability is further improved.
【００１１】[0011]
【発明の実施の形態】以下、添付図面を参照しながら、
本発明の実施の形態を説明する。図１は本発明の一実施
形態に係る半導体装置、即ち半導体べアチップが下向き
階段状凸形インターポーザを介して階段状凹形マザーボ
ードに実装されている半導体装置を示す断面図である。BRIEF DESCRIPTION OF THE DRAWINGS FIG.
An embodiment of the present invention will be described. FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention, that is, a semiconductor device in which a semiconductor bear chip is mounted on a stepped concave motherboard via a downward stepped convex interposer.
【００１２】図１に示されるように、所定の半導体素子
が形成された半導体ベアチップ１０には、所定のピッチ
でバンプ電極１２が配置されている。また、下向き階段
状凸形インターポーザ２０は、従来のインターポーザの
場合と同様に例えばエポキシ剤等を材料とし、平坦な上
面と下向きに階段状に凸形状をなしている底面をもつ絶
縁基板２２と、この絶縁基板２２の平坦な上面上に配列
されているランド２４と、絶縁基板２２を垂直に貫通す
ると共に、上端部が各ランド２４に接続し、下端部が絶
縁基板２２底面の階段状の平坦部に露出しているスルー
ホール配線２６とから構成されている。As shown in FIG. 1, bump electrodes 12 are arranged at a predetermined pitch on a semiconductor bare chip 10 on which predetermined semiconductor elements are formed. Further, as in the case of the conventional interposer, the downwardly stepped convex interposer 20 is made of, for example, an epoxy agent, and has a flat top surface and an insulating substrate 22 having a downwardly stepped convex bottom surface, The lands 24 arranged on the flat upper surface of the insulating substrate 22 penetrate the insulating substrate 22 vertically, the upper end is connected to each land 24, and the lower end is a step-like flat surface on the bottom surface of the insulating substrate 22. And the through-hole wiring 26 exposed at the portion.
【００１３】そして、この下向き階段状凸形インターポ
ーザ２０には、半導体ベアチップ１０がフリップチップ
実装されている。即ち、半導体ベアチップ１０がフェイ
スダウン状態において下向き階段状凸形インターポーザ
２０上に搭載され、半導体ベアチップ１０の各バンプ電
極１２が下向き階段状凸形インターポーザ２０の各ラン
ド２４に接合している。また、半導体ベアチップ１０と
下向き階段状凸形インターポーザ２０との間には、所定
の絶縁性樹脂２８が充填され、互いに接合しているバン
プ電極１２及びランド２４の周囲を覆っている。The semiconductor bare chip 10 is flip-chip mounted on the downward stepped convex interposer 20. That is, the semiconductor bare chip 10 is mounted on the downward step-shaped convex interposer 20 in the face-down state, and each bump electrode 12 of the semiconductor bare chip 10 is joined to each land 24 of the downward step-shaped convex interposer 20. In addition, a predetermined insulating resin 28 is filled between the semiconductor bare chip 10 and the downward step-shaped convex interposer 20, and covers the periphery of the bump electrode 12 and the land 24 which are bonded to each other.
【００１４】また、多層配線構造の階段状凹形マザーボ
ード３０は、下向き階段状凸形インターポーザ２０底面
の下向きの階段状の凸形状に対応して、階段状に凹形状
をなしている上面をもつ絶縁基板３２と、この絶縁基板
３２中に積層されて形成されている複数の配線パターン
３４と、絶縁基板３２の上面の階段状の平坦部に露出し
ている複数の配線パターン３４からなるランド３６とか
ら構成されている。The stepped concave motherboard 30 having a multilayer wiring structure has a stepped concave upper surface corresponding to the downward stepped convex shape of the bottom surface of the stepped convex interposer 20 facing downward. A land 36 composed of an insulating substrate 32, a plurality of wiring patterns 34 laminated and formed in the insulating substrate 32, and a plurality of wiring patterns 34 exposed on a step-like flat portion on the upper surface of the insulating substrate 32. It is composed of
【００１５】そして、この多層配線構造の階段状凹形マ
ザーボード３０には、半導体ベアチップ１０をフリップ
チップ実装した下向き階段状凸形インターポーザ２０が
実装されている。即ち、下向き階段状凸形インターポー
ザ２０の下向きに階段状に凸形状をなしている底面が、
階段状凹形マザーボード３０の階段状に凹形状をなして
いる上面にすっぽりと嵌め込まれ、下向き階段状凸形イ
ンターポーザ２０の絶縁基板２２底面の階段状の平坦部
から露出しているスルーホール配線２６の下端部が、は
んだ又は異方性導電樹脂や圧接（図示せず）によって階
段状凹形マザーボード３０上面の階段状の平坦部に露出
しているランド３６に接続されている。On the stepped concave motherboard 30 having the multilayer wiring structure, a downward stepped convex interposer 20 on which the semiconductor bare chip 10 is flip-chip mounted is mounted. That is, the bottom surface having a downwardly stepped convex interposer 20 is formed in a downwardly stepped convex shape.
The through-hole wiring 26 which is completely fitted on the stepped concave upper surface of the stepped motherboard 30 and is exposed from the stepped flat portion on the bottom surface of the insulating substrate 22 of the downward stepped convex interposer 20. Is connected to a land 36 which is exposed on a step-shaped flat portion on the upper surface of the step-shaped concave motherboard 30 by soldering, anisotropic conductive resin, or pressure welding (not shown).
【００１６】ここで、下向き階段状凸形インターポーザ
２０の絶縁基板２２底面の階段状の垂直面と階段状凹形
マザーボード３０上面の階段状の垂直面との間には、そ
れぞれ隙間３８が形成されている。なお、これらの隙間
３８は、所定の絶縁性樹脂によって充填されていてもよ
い。Here, gaps 38 are respectively formed between the step-like vertical surface on the bottom surface of the insulating substrate 22 of the step-like convex interposer 20 facing downward and the step-like vertical surface on the upper surface of the step-like concave motherboard 30. ing. Note that these gaps 38 may be filled with a predetermined insulating resin.
【００１７】こうして、半導体ベアチップ１０の各バン
プ電極１２は、下向き階段状凸形インターポーザ２０の
ランド２４、スルーホール配線２６、はんだ又は異方性
導電樹脂、及び階段状凹形マザーボード３０のランド３
６を介して、階段状凹形マザーボード３０の各配線パタ
ーン３４に接続している。即ち、半導体べアチップ１０
が下向き階段状凸形インターポーザ２０を介して階段状
凹形マザーボード３０に実装されている。In this manner, each bump electrode 12 of the semiconductor bare chip 10 has a land 24 of the downward step-shaped convex interposer 20, a through-hole wiring 26, a solder or anisotropic conductive resin, and a land 3 of the step-shaped concave motherboard 30.
6, it is connected to each wiring pattern 34 of the stepped concave motherboard 30. That is, the semiconductor bear chip 10
Are mounted on the stepped concave motherboard 30 via the downward stepped convex interposer 20.
【００１８】次に、図１に示す下向き階段状凸形インタ
ーポーザ２０の製造方法を、図２の断面図を用いて説明
する。先ず、例えばエポキシ剤等を材料とする大きさの
異なる絶縁基板２２ａ、２２ｂ、…、２２ｅを積層し
て、平坦な上面と下向きに階段状に凸形状をなしている
底面をもつ絶縁基板２２を形成する。Next, a method of manufacturing the downward step-shaped convex interposer 20 shown in FIG. 1 will be described with reference to the sectional view of FIG. First, insulating substrates 22a, 22b,..., 22e of different sizes made of, for example, an epoxy agent or the like are laminated to form an insulating substrate 22 having a flat upper surface and a bottom surface having a convex shape stepwise downward. Form.
【００１９】続いて、例えばドリルを用いて、絶縁基板
２２を垂直に貫通し、その上面から底面の階段状の平坦
部に至るスルーホールを開口する。そして、例えば銅メ
ッキ法を用いて、スルーホール内壁に銅膜を形成する。
こうして、絶縁基板２２上面から底面の階段状の平坦部
に垂直に貫通すると共に、上端部が絶縁基板２２上面に
僅かに露出し、下端部が絶縁基板２２底面の階段状の平
坦部に僅かに露出しているスルーホール配線２６を形成
する。Subsequently, for example, a drill is used to vertically penetrate the insulating substrate 22 and open a through hole extending from the upper surface to the stepped flat portion on the bottom surface. Then, a copper film is formed on the inner wall of the through hole by using, for example, a copper plating method.
Thus, while penetrating perpendicularly from the upper surface of the insulating substrate 22 to the step-shaped flat portion of the bottom surface, the upper end portion is slightly exposed to the upper surface of the insulating substrate 22, and the lower end portion is slightly exposed to the step-shaped flat portion of the bottom surface of the insulating substrate 22. An exposed through-hole wiring 26 is formed.
【００２０】続いて、絶縁基板２２の平坦な上面上に所
定の金属膜を堆積した後、この金属膜をパターニングし
て、絶縁基板２２の平坦な上面上に所定のピッチで配列
されると共に、各スルーホール配線２６の上端部にそれ
ぞれ接続するランド２４を形成する。なお、これらのラ
ンド２４は、例えば銅メッキ法を用いてスルーホール配
線２６を形成する際に、同時に形成してもよい。このよ
うにして、図２に示される下向き階段状凸形インターポ
ーザ２０を作製する。Subsequently, after a predetermined metal film is deposited on the flat upper surface of the insulating substrate 22, the metal film is patterned and arranged at a predetermined pitch on the flat upper surface of the insulating substrate 22. The lands 24 connected to the upper end of each through-hole wiring 26 are formed. These lands 24 may be formed at the same time when the through-hole wirings 26 are formed using, for example, a copper plating method. In this way, the downward stepped convex interposer 20 shown in FIG. 2 is manufactured.
【００２１】次に、図１に示す多層配線構造の階段状凹
形マザーボード３０の製造方法を、図３の断面図を用い
て説明する。先ず、絶縁基板３２ａ上に配線パターン３
４ａを形成する。続いて、絶縁基板３２ｂ上に配線パタ
ーン３４ｂを形成すると共に、その中央部に所定の大き
さの開口部を形成する。続いて、絶縁基板３２ｃ上に配
線パターン３４ｃを形成すると共に、その中央部に絶縁
基板３２ｂに形成した開口部よりも大きな開口部を形成
する。このようにして、順番に絶縁基板３２ｄ、３２ｅ
上にそれぞれ配線パターン３４ｄ、３４ｅを形成すると
共に、その中央部により大きな開口部を形成していく。
そして、最後に配線パターンを形成しない絶縁基板３２
ｆの中央部に最も大きな開口部を形成する。Next, a method of manufacturing the stepped concave motherboard 30 having the multilayer wiring structure shown in FIG. 1 will be described with reference to the sectional view of FIG. First, the wiring pattern 3 is placed on the insulating substrate 32a.
4a is formed. Subsequently, a wiring pattern 34b is formed on the insulating substrate 32b, and an opening having a predetermined size is formed in the center thereof. Subsequently, a wiring pattern 34c is formed on the insulating substrate 32c, and an opening larger than the opening formed on the insulating substrate 32b is formed at the center thereof. In this manner, the insulating substrates 32d, 32e
The wiring patterns 34d and 34e are formed thereon, and a larger opening is formed at the center thereof.
Finally, an insulating substrate 32 on which no wiring pattern is formed
The largest opening is formed at the center of f.
【００２２】次いで、これらの絶縁基板３２ａ、３２
ｂ、…、３２ｆを重ね合わせて、絶縁基板３２を形成す
る。このとき、絶縁基板３２ｂ、３２ｃ、…、３２ｆの
中央部に形成した開口部が順により大きくなっているた
め、絶縁基板３２ａ、３２ｂ、…、３２ｆが順に積層さ
れた絶縁基板３２の上面は、下向き階段状凸形インター
ポーザ２０の底面の下向きの階段状の凸形状に対応し
て、階段状に凹形状をなすようにする。こうして、下向
き階段状凸形インターポーザ２０の下向きに階段状に凸
形状をなしている底面に対応し、階段状に凹形状をなし
ている上面をもつ絶縁基板３２を形成すると共に、この
絶縁基板３２中に複数の配線パターン３４ａ、３４ｂ、
…、３４ｅ（以下、これら複数の配線パターン３４ａ、
３４ｂ、…、３４ｅを概括して「配線パターン３４」と
呼ぶ）が積層されている多層配線構造を形成する。Next, these insulating substrates 32a, 32
The insulating substrate 32 is formed by superimposing b,..., 32f. At this time, since the openings formed in the central portions of the insulating substrates 32b, 32c,..., 32f become larger in order, the upper surface of the insulating substrate 32 on which the insulating substrates 32a, 32b,. A concave shape is formed in a stepwise manner corresponding to the downward stepped convex shape of the bottom surface of the downward stepped convex interposer 20. In this manner, the insulating substrate 32 having a stepped concave top surface corresponding to the downward stepped convex bottom surface corresponding to the downward stepped convex interposer 20 is formed. A plurality of wiring patterns 34a, 34b,
, 34e (hereinafter, the plurality of wiring patterns 34a,
34b,..., 34e are generally referred to as “wiring patterns 34”).
【００２３】また、絶縁基板３２ｂ、３２ｃ、…、３２
ｆの中央部に形成した開口部が順により大きくなってい
ることから、絶縁基板３２ａ、３２ｂ、…、３２ｆを重
ね合わせる際に、各絶縁基板３２ａ、３２ｂ、…、３２
ｅ上にそれぞれ形成した配線パターン３４の端部が露出
する。そして、絶縁基板３２上面の階段状の平坦部に露
出しているこれらの配線パターン３２をそれぞれランド
３６とする。このようにして、図３に示される多層配線
構造の階段状凹形マザーボード３０を作製する。The insulating substrates 32b, 32c,.
Since the openings formed in the central portion of f are gradually increased, when the insulating substrates 32a, 32b,..., 32f are overlapped, the insulating substrates 32a, 32b,.
e, the end portions of the wiring patterns 34 formed on the respective portions e are exposed. These wiring patterns 32 exposed on the step-like flat portions on the upper surface of the insulating substrate 32 are used as lands 36, respectively. Thus, the step-shaped concave motherboard 30 having the multilayer wiring structure shown in FIG. 3 is manufactured.
【００２４】次に、図１に示す半導体装置の製造方法、
即ち半導体べアチップ１０を下向き階段状凸形インター
ポーザ２０を介して階段状凹形マザーボード３０に実装
する実装方法を、図４及び図５の断面図を用いて説明す
る。先ず、図４に示されるように、半導体ベアチップ１
０を下向き階段状凸形インターポーザ２０にフリップチ
ップ実装する。即ち、半導体ベアチップ１０をフェイス
ダウン状態にして下向き階段状凸形インターポーザ２０
の上面上に搭載し、半導体ベアチップ１０の各バンプ電
極１２を下向き階段状凸形インターポーザ２０の各ラン
ド２４に接合させる。続いて、半導体ベアチップ１０と
下向き階段状凸形インターポーザ２０との間に絶縁性樹
脂２８を充填し、この絶縁性樹脂２８によって互いに接
合しているバンプ電極１２及びランド２４の周囲を覆
う。また、圧接用樹脂や異方導電性樹脂や異方性導電膜
を用いて加熱・加圧をし、半導体ベアチップ１０を下向
き階段状凸形インターポーザ２０の各ランド２４に接合
させる方法もある。Next, a method of manufacturing the semiconductor device shown in FIG.
That is, a mounting method for mounting the semiconductor bear chip 10 on the stepped concave motherboard 30 via the downward stepped convex interposer 20 will be described with reference to the cross-sectional views of FIGS. First, as shown in FIG.
0 is flip-chip mounted on the downward step-shaped convex interposer 20. That is, the semiconductor bare chip 10 is placed in a face-down state, and the downward step-shaped convex interposer 20 is turned down.
And the bump electrodes 12 of the semiconductor bare chip 10 are joined to the lands 24 of the step-shaped convex interposer 20 facing downward. Subsequently, an insulating resin 28 is filled between the semiconductor bare chip 10 and the downward step-shaped convex interposer 20, and the periphery of the bump electrode 12 and the land 24 bonded to each other is covered with the insulating resin 28. Alternatively, there is a method in which the semiconductor bare chip 10 is bonded to each land 24 of the downwardly stepped convex interposer 20 by applying heat and pressure using a pressing resin, an anisotropic conductive resin, or an anisotropic conductive film.
【００２５】次いで、図５に示されるように、半導体ベ
アチップ１０をフリップチップ実装した下向き階段状凸
形インターポーザ２０を、階段状凹形マザーボード３０
に実装する。即ち、下向き階段状凸形インターポーザ２
０の下向きに階段状に凸形状をなしている底面を、階段
状凹形マザーボード３０の階段状に凹形状をなしている
上面にすっぽりと嵌め込む。そして、下向き階段状凸形
インターポーザ２０の絶縁基板２２底面の階段状の平坦
部から露出しているスルーホール配線２６の下端部を、
例えばはんだ付け又は導電樹脂圧着等により、階段状凹
形マザーボード３０上面の階段状の平坦部に露出してい
るランド３６に接続させる。Next, as shown in FIG. 5, the downward stepped convex interposer 20 on which the semiconductor bare chip 10 is flip-chip mounted is connected to the stepped concave motherboard 30.
To be implemented. That is, the downward stepped convex interposer 2
The bottom surface of the step-shaped concave motherboard 30 having a downwardly convex shape is fitted into the upper surface of the stepped concave mother board 30. Then, the lower end of the through-hole wiring 26 exposed from the step-like flat portion on the bottom surface of the insulating substrate 22 of the downward step-like convex interposer 20 is
For example, by soldering or conductive resin crimping, it is connected to the land 36 exposed on the step-like flat portion on the upper surface of the step-like concave motherboard 30.
【００２６】こうして、半導体べアチップ１０を下向き
階段状凸形インターポーザ２０を介して階段状凹形マザ
ーボード３０に実装する。即ち、半導体ベアチップ１０
の各バンプ電極１２が、下向き階段状凸形インターポー
ザ２０のランド２４、スルーホール配線２６、はんだ又
は導電樹脂、及び階段状凹形マザーボード３０のランド
３６を介して、階段状凹形マザーボード３０の各配線パ
ターン３４に接続している、上記図１の半導体装置を作
製する。In this manner, the semiconductor bear chip 10 is mounted on the stepped concave motherboard 30 via the downward stepped convex interposer 20. That is, the semiconductor bare chip 10
Of the step-shaped concave motherboard 30 via the lands 24 of the downward step-shaped convex interposer 20, through-hole wiring 26, solder or conductive resin, and lands 36 of the step-shaped concave motherboard 30. The semiconductor device of FIG. 1 connected to the wiring pattern 34 is manufactured.
【００２７】このように本実施形態によれば、下向き階
段状凸形インターポーザ２０底面の階段状の凸形状と階
段状凹形マザーボード３０上面の階段状の凹形状とが互
いに対応して、下向き階段状凸形インターポーザ２０底
面が階段状凹形マザーボード３０上面にすっぽり嵌め込
まれていることにより、半導体べアチップ１０をフリッ
プチップ実装した下向き階段状凸形インターポーザ２０
を、絶縁基板３２中に複数の配線パターン３４が積層さ
れている多層配線構造をなす階段状凹形マザーボード３
０に実装する際に、その位置合わを精度よく且つ容易に
行うことが可能になるため、半導体べアチップ１０を下
向き階段状凸形インターポーザ２０を介して階段状凹形
マザーボード３０に実装する際のスループットを向上さ
せることができる。As described above, according to the present embodiment, the step-shaped convex shape on the bottom surface of the step-shaped convex interposer 20 and the step-shaped concave shape on the upper surface of the step-shaped concave motherboard 30 correspond to each other, and the downward staircase is formed. The bottom surface of the step-shaped convex interposer 20 is completely fitted on the top surface of the step-shaped concave motherboard 30, so that the semiconductor step chip 10 is flip-chip mounted and the downward step-shaped convex interposer 20 is mounted.
A stepped concave motherboard 3 having a multilayer wiring structure in which a plurality of wiring patterns 34 are laminated on an insulating substrate 32.
When the semiconductor bare chip 10 is mounted on the step-shaped concave motherboard 30 via the downward step-shaped convex interposer 20, it becomes possible to accurately and easily perform the alignment when mounting the semiconductor chip on the motherboard 30. Throughput can be improved.
【００２８】また、このようにして半導体べアチップ１
０が下向き階段状凸形インターポーザ２０を介して階段
状凹形マザーボード３０に実装された半導体装置は、そ
の構造上、半導体べアチップ１０をフリップチップ実装
した下向き階段状凸形インターポーザ２０と階段状凹形
マザーボード３０との位置ずれが抑制されるため、接続
不良等を防止して信頼性を向上させることができる。Further, the semiconductor bear chip 1
The semiconductor device mounted on the step-shaped concave motherboard 30 via the step-shaped convex interposer 20 with the downwardly directed step-shaped convex interposer 20 and the step-shaped concave interposer 20 in which the semiconductor bear chip 10 is flip-chip mounted is provided. Since the misalignment with the motherboard 30 is suppressed, a connection failure or the like can be prevented and reliability can be improved.
【００２９】また、下向き階段状凸形インターポーザ２
０底面の階段状の平坦部から露出しているスルーホール
配線２６の下端部が、はんだ又は異方性導電樹脂や圧接
によって階段状凹形マザーボード３０上面の階段状の平
坦部に露出しているランド３６に接続されていることに
より、これら下向き階段状凸形インターポーザ２０のス
ルーホール配線２６と階段状凹形マザーボード３０のラ
ンド３６との電気的接続が安定して確保されるため、接
続不良等を確実に防止して信頼性を更に向上させること
ができる。Further, the downward step-shaped convex interposer 2
The lower end of the through-hole wiring 26 exposed from the step-shaped flat portion on the bottom surface is exposed to the step-shaped flat portion on the upper surface of the step-shaped concave motherboard 30 by soldering, anisotropic conductive resin, or pressure welding. By being connected to the land 36, the electrical connection between the through-hole wiring 26 of the downward step-shaped convex interposer 20 and the land 36 of the step-shaped concave motherboard 30 is stably ensured. And the reliability can be further improved.
【００３０】なお、上記実施形態においては、下向き階
段状凸形インターポーザ２０の下向きに階段状に凸形状
をなしている底面と階段状凹形マザーボード３０の階段
状に凹形状をなしている上面との間に形成される隙間３
８はそのままの状態に放置されているが、これらの隙間
３８を所定の絶縁性樹脂によって充填してもよい。この
場合、この絶縁性樹脂によって下向き階段状凸形インタ
ーポーザ２０が階段状凹形マザーボード３０上に確りと
固定されるため、両者の位置ずれやそれに伴う接続不良
等をより確実に防止して信頼性を更に向上させることが
できる。In the above embodiment, the bottom surface of the stepped convex interposer 20 having the downwardly convex shape and the upper surface of the stepped concave motherboard 30 having the concave shape are formed. Gap 3 formed between
Although 8 is left as it is, these gaps 38 may be filled with a predetermined insulating resin. In this case, since the downward step-shaped convex interposer 20 is firmly fixed on the step-shaped concave motherboard 30 by the insulating resin, the positional displacement between the two and the connection failure resulting therefrom are more reliably prevented, and the reliability is improved. Can be further improved.
【００３１】[0031]
【発明の効果】以上詳細に説明した通り、本発明に係る
半導体装置によれば、次のような効果を奏することがで
きる。即ち、請求項１に係る半導体装置によれば、下向
き階段状凸形インターポーザの底面の階段状の凸形状と
階段状凹形マザーボードの上面の階段状の凹形状とが互
いに対応して、下向き階段状凸形インターポーザの底面
が階段状凹形マザーボードの上面にすっぽり嵌め込まれ
るようになっていることにより、平坦な上面上に半導体
べアチップを搭載した下向き階段状凸形インターポーザ
を、絶縁基板中に複数の配線パターンが積層された多層
配線構造をなす階段状凹形マザーボードに実装する際
に、その位置合わを精度よく且つ容易に行うことが可能
になるため、半導体べアチップを下向き階段状凸形イン
ターポーザを介して階段状凹形マザーボードに実装する
際のスループットが向上を向上させることができる。ま
た、このようにして半導体べアチップが下向き階段状凸
形インターポーザを介して階段状凹形マザーボードに実
装された半導体装置は、その構造上、半導体べアチップ
を搭載した下向き階段状凸形インターポーザと階段状凹
形マザーボードとの位置ずれが抑制されるため、接続不
良等を防止して信頼性を向上させることができる。As described in detail above, according to the semiconductor device of the present invention, the following effects can be obtained. That is, according to the semiconductor device of the first aspect, the step-like convex shape on the bottom surface of the step-like convex interposer facing downward and the step-like concave shape on the upper surface of the step-like concave motherboard correspond to each other. The bottom surface of the step-shaped convex interposer fits snugly on the top surface of the step-shaped concave motherboard, so that a plurality of downward step-shaped convex interposers with a semiconductor bear chip mounted on a flat top surface are placed on the insulating substrate. When mounting on a step-shaped concave motherboard having a multilayer wiring structure in which the wiring patterns of the above are stacked, it is possible to accurately and easily perform the alignment. Throughput can be improved when mounted on a stepped concave motherboard. Further, in this manner, the semiconductor device in which the semiconductor bear chip is mounted on the step-shaped concave motherboard via the downward step-shaped convex interposer is structurally similar to the downward step-shaped convex interposer having the semiconductor bear chip mounted thereon. Since the misalignment with the concave motherboard is suppressed, poor connection and the like can be prevented, and the reliability can be improved.
【００３２】また、請求項２に係る半導体装置によれ
ば、下向き階段状凸形インターポーザのスルーホール配
線の下端部と階段状凹形マザーボードの第２のランドと
がはんだ又は異方性導電樹脂や圧接によって接続されて
いることにより、下向き階段状凸形インターポーザのス
ルーホール配線と階段状凹形マザーボードの第２のラン
ドとの電気的接続が安定して確保されるため、接続不良
等を確実に防止して信頼性を更に向上させることができ
る。Further, according to the semiconductor device of the present invention, the lower end of the through-hole wiring of the downward step-shaped convex interposer and the second land of the step-shaped concave motherboard are formed of solder or anisotropic conductive resin. By being connected by pressure contact, the electrical connection between the through-hole wiring of the downward step-shaped convex interposer and the second land of the step-shaped concave motherboard is stably secured, so that a connection failure or the like can be reliably prevented. Prevention can further improve the reliability.
【００３３】また、請求項３に係る半導体装置によれ
ば、下向き階段状凸形インターポーザの下向きに階段状
に凸形状をなしている底面と階段状凹形マザーボードの
階段状に凹形状をなしている上面との間に所定の樹脂が
充填されていることにより、この樹脂によって下向き階
段状凸形インターポーザが階段状凹形マザーボード上に
固定されるため、両者の位置ずれやそれに伴う接続不良
等をより確実に防止して信頼性を更に向上させることが
できる。Further, according to the semiconductor device of the third aspect, the bottom surface of the downward step-shaped convex interposer has a step-shaped convex shape and the step-shaped concave motherboard has a step-shaped concave shape. When the predetermined resin is filled between the upper surface and the upper surface, the downward step-shaped convex interposer is fixed on the step-shaped concave motherboard by this resin, so that the positional displacement of the two and the connection failure accompanying the same are prevented. The reliability can be further reliably improved to further improve the reliability.
【図１】本発明の一実施形態に係る半導体装置。即ち半
導体べアチップが下向き階段状凸形インターポーザを介
して階段状凹形マザーボードに実装されている半導体装
置を示す断面図である。FIG. 1 is a semiconductor device according to an embodiment of the present invention. That is, it is a cross-sectional view showing a semiconductor device in which a semiconductor bear chip is mounted on a step-shaped concave motherboard via a downward step-shaped convex interposer.
【図２】図１に示す下向き階段状凸形インターポーザの
製造方法を説明するための断面図である。FIG. 2 is a cross-sectional view for explaining a method of manufacturing the downward stepped convex interposer shown in FIG.
【図３】図１に示す多層配線構造の階段状凹形マザーボ
ードの製造方法を説明するための断面図である。FIG. 3 is a cross-sectional view for explaining a method of manufacturing the stepped concave motherboard having the multilayer wiring structure shown in FIG.
【図４】図１に示す半導体装置の製造方法。即ち半導体
べアチップを下向き階段状凸形インターポーザを介して
階段状凹形マザーボードに実装する実装方法を説明する
ための断面図（その１）である。FIG. 4 is a method for manufacturing the semiconductor device shown in FIG. 1; That is, FIG. 10 is a cross-sectional view (part 1) for describing a mounting method of mounting a semiconductor bare chip on a step-shaped concave motherboard via a downward step-shaped convex interposer.
【図５】図１に示す半導体装置の製造方法。即ち半導体
べアチップを下向き階段状凸形インターポーザを介して
階段状凹形マザーボードに実装する実装方法を説明する
ための断面図（その２）である。FIG. 5 is a method for manufacturing the semiconductor device shown in FIG. 1; That is, it is a sectional view (part 2) for explaining a mounting method of mounting a semiconductor bare chip on a stepped concave motherboard via a downward stepped convex interposer.
１０…半導体ベアチップ、１２…バンプ電極、２０…下
向き階段状凸形インターポーザ、２２、２２ａ、２２
ｂ、２２ｃ、２２ｄ、２２ｅ…絶縁基板、２４…ラン
ド、２６…スルーホール配線、２８…絶縁性樹脂、３０
…階段状凹形マザーボード、３２、３２ａ、３２ｂ、３
２ｃ、３２ｄ、３２ｅ、３２ｆ…絶縁基板、３４、３４
ａ、３４ｂ、３４ｃ、３４ｄ、３４ｅ…配線パターン、
３６…ランド、３８…隙間。DESCRIPTION OF SYMBOLS 10 ... Semiconductor bare chip, 12 ... Bump electrode, 20 ... Downward stepped convex interposer, 22, 22a, 22
b, 22c, 22d, 22e: insulating substrate, 24: land, 26: through-hole wiring, 28: insulating resin, 30
… Step-shaped concave motherboard, 32, 32a, 32b, 3
2c, 32d, 32e, 32f ... insulating substrate, 34, 34
a, 34b, 34c, 34d, 34e ... wiring pattern,
36: land, 38: gap.
Claims (3)
してマザーボードに実装されている半導体装置であっ
て、 前記インターポーザが、平坦な上面と下向きに階段状に
凸形状をなしている底面をもつ第１の絶縁基板と、前記
第１の絶縁基板の上面上に配列され、前記半導体べアチ
ップの電極と接合されている第１のランドと、前記第１
の絶縁基板を貫通して、前記第１のランドから前記第１
の絶縁基板の底面の階段状の平坦部に至るスルーホール
配線とを有しており、 前記マザーボードが、前記インターポーザの下向きに階
段状に凸形状をなしている底面に対応して、階段状に凹
形状をなしている上面をもつ第２の絶縁基板と、前記第
２の絶縁基板中に積層されて形成されている複数の配線
パターンと、前記第２の絶縁基板の上面の階段状の平坦
部に露出している前記配線パターンからなる第２のラン
ドとを有しており、 前記インターポーザの下向きに階段状に凸形状をなして
いる底面が、前記マザーボードの階段状に凹形状をなし
ている上面に嵌め込まれて、前記インターポーザの前記
スルーホール配線の下端部が、前記マザーボードの前記
第２のランドに接合されていることを特徴とする半導体
装置。1. A semiconductor device in which a semiconductor bear chip is mounted on a motherboard via an interposer, wherein the interposer has a flat top surface and a bottom surface having a downwardly stepped convex shape. An insulating substrate; a first land arranged on an upper surface of the first insulating substrate and joined to an electrode of the semiconductor bear chip;
Through the insulating substrate, and from the first land to the first land.
And a through-hole wiring reaching a step-like flat portion on the bottom surface of the insulating substrate, wherein the motherboard has a step-like shape corresponding to the bottom surface having a step-like convex shape facing down the interposer. A second insulating substrate having an upper surface having a concave shape, a plurality of wiring patterns laminated and formed in the second insulating substrate, and a step-like flat surface on the upper surface of the second insulating substrate. And a second land made of the wiring pattern exposed to the portion, wherein the bottom surface of the interposer has a downward convex shape in a stepwise shape, and the bottom surface has a concave shape in a step shape of the motherboard. A lower end of the through-hole wiring of the interposer is joined to the second land of the motherboard.
記インターポーザの前記スルーホール配線の下端部と前
記マザーボードの前記第２のランドとが、はんだ又は異
方性導電樹脂や圧接によって接続されていることを特徴
とする半導体装置。2. The semiconductor device according to claim 1, wherein a lower end of said through-hole wiring of said interposer and said second land of said motherboard are connected by solder, anisotropic conductive resin, or pressure welding. A semiconductor device characterized by the above-mentioned.
している底面と前記マザーボードの前記階段状に凹形状
をなしている上面との間に、所定の樹脂が充填されてい
ることを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein: between the bottom surface of the interposer, which has a downwardly convex shape, and the top surface of the motherboard, which has a concave shape. A semiconductor device filled with a predetermined resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9287393A JPH11121524A (en) | 1997-10-20 | 1997-10-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9287393A JPH11121524A (en) | 1997-10-20 | 1997-10-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11121524A true JPH11121524A (en) | 1999-04-30 |
Family
ID=17716774
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9287393A Pending JPH11121524A (en) | 1997-10-20 | 1997-10-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11121524A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6335210B1 (en) | 1999-12-17 | 2002-01-01 | International Business Machines Corporation | Baseplate for chip burn-in and/of testing, and method thereof |
| WO2004066691A1 (en) * | 2003-01-22 | 2004-08-05 | Nec Corporation | Circuit board device and method for interconnecting wiring boards |
| EP1465471A3 (en) * | 2003-04-03 | 2005-07-27 | Matsushita Electric Industrial Co., Ltd. | Wiring board, method for manufacturing a wiring board and electronic equipment |
| US7151319B2 (en) * | 2003-06-27 | 2006-12-19 | Hitachi, Ltd. | Semiconductor device |
| JP2007081071A (en) * | 2005-09-14 | 2007-03-29 | Tokai Denshi Kogyo Kk | Semiconductor wiring pullout structure |
| JP2012104662A (en) * | 2010-11-10 | 2012-05-31 | Nikon Corp | Imaging apparatus |
| WO2016133836A1 (en) | 2015-02-17 | 2016-08-25 | Intel Corporation | Microelectronic interconnect adaptor |
| WO2018101051A1 (en) * | 2016-12-01 | 2018-06-07 | 株式会社村田製作所 | Multilayer substrate connecting body and transmission line device |
-
1997
- 1997-10-20 JP JP9287393A patent/JPH11121524A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6335210B1 (en) | 1999-12-17 | 2002-01-01 | International Business Machines Corporation | Baseplate for chip burn-in and/of testing, and method thereof |
| KR100718850B1 (en) * | 2003-01-22 | 2007-05-16 | 닛본 덴끼 가부시끼가이샤 | Circuit board device and method for interconnecting wiring boards |
| WO2004066691A1 (en) * | 2003-01-22 | 2004-08-05 | Nec Corporation | Circuit board device and method for interconnecting wiring boards |
| US7405948B2 (en) | 2003-01-22 | 2008-07-29 | Nec Corporation | Circuit board device and method of interconnecting wiring boards |
| EP1465471A3 (en) * | 2003-04-03 | 2005-07-27 | Matsushita Electric Industrial Co., Ltd. | Wiring board, method for manufacturing a wiring board and electronic equipment |
| US7151319B2 (en) * | 2003-06-27 | 2006-12-19 | Hitachi, Ltd. | Semiconductor device |
| JP2007081071A (en) * | 2005-09-14 | 2007-03-29 | Tokai Denshi Kogyo Kk | Semiconductor wiring pullout structure |
| JP2012104662A (en) * | 2010-11-10 | 2012-05-31 | Nikon Corp | Imaging apparatus |
| WO2016133836A1 (en) | 2015-02-17 | 2016-08-25 | Intel Corporation | Microelectronic interconnect adaptor |
| US20170278778A1 (en) * | 2015-02-17 | 2017-09-28 | Intel Corporation | Microelectronic interconnect adaptor |
| EP3259778A4 (en) * | 2015-02-17 | 2018-11-07 | Intel Corporation | Microelectronic interconnect adaptor |
| WO2018101051A1 (en) * | 2016-12-01 | 2018-06-07 | 株式会社村田製作所 | Multilayer substrate connecting body and transmission line device |
| US11056756B2 (en) | 2016-12-01 | 2021-07-06 | Murata Manufacturing Co., Ltd. | Multilayer substrate connecting body and transmission line device |
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