JPH10209216A - Chip size package and its production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To joint bumps having high bump height with high accuracy. SOLUTION: In order to form bumps 2 on a semiconductor 1 and bumps 8 having shape and arrangement identical to those of the bumps 2 on a carrier board 3, recesses are made in the carrier board 3 coated with resin by stamping the bumps 2 on the semiconductor 1 and filled with a conductive bump material. This arrangement eliminates positional shift between the bump and the electrode. Alignment is controlled optimally by arranging joint detection elements previously above the semiconductor and the carrier board in the process for jointing a semiconductor wafer or a chip to the carrier board thereby measuring the resistance between a pair of electrodes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a chip size package for mounting a semiconductor chip on a circuit board at a high density and a method of manufacturing the same.

[0002]

2. Description of the Related Art The demand for high-density mounting has been increasing with the trend of miniaturization and higher functionality of electronic devices. These demands are being met to some extent by recent breakthroughs in surface mount technology. Elemental technologies for high-density mounting include miniaturization of components to be mounted including packages, densification of connection terminals, densification of circuit patterns, low thermal resistance, and the like. The mounted components mainly include passive components such as resistors and capacitors as well as semiconductor components such as ICs and LSIs.

[0003] In particular, the progress of semiconductor components has been remarkable, and from the viewpoint of packages, progress has been made from DIL packages to QFP packages and BGA packages. The BGA package includes a semiconductor chip 1, connection bumps 2 attached to the semiconductor chip, and a carrier substrate 3, as shown in a sectional view of FIG. The carrier substrate 3 includes a substrate-side electrode 7, an insulating layer 4, a wiring layer 5, a via hole 6, a connection bump 11 as an external connection terminal, and the like.
3648, and JP-A-6-296080.
FIG. 7A is a plan view of the front surface of the carrier substrate 3 on the semiconductor chip 1 side, and FIG. 7B is a plan view of the rear surface of the carrier substrate 3. Between the semiconductor chip 1 and the carrier substrate 3, pads and bumps are arranged at high density along four sides around the semiconductor chip as shown in FIG.
It is connected to an electrode 7 on the carrier substrate 3. Since the external connection terminals 11 are arranged two-dimensionally in a grid on the back surface of the carrier substrate 3, the number of bumps per area can be maximized by setting the bump pitch to a specified value. That is, the carrier substrate 3 has a function of converting the pad arrangement of the four-sided arrangement into a two-dimensional grid arrangement.

[0004] With such a structure, even if the number of external connection terminals 11 increases with high performance, it is possible to minimize the increase in package size. If a BGA package is used, a package almost the same size as a semiconductor chip, that is, a chip size package can be realized. After that, the chip size package was changed to CSP
It is written. In addition, passive components such as resistors and capacitors also respond to the demand for high-density surface mounting, and small chip components of 1 mm □ or less have been developed and put into practical use, and ways to extract electrode terminals have been studied to reduce the size of mounting. ing.

In the CSP, the connection structure and connection method between the bumps provided on the electrodes (pads) of the semiconductor chip and the carrier substrate greatly affect the assembly yield and reliability. In the case of a high-performance chip, the number of pads becomes several hundred or more, and a pad pitch of 0.1 mm or less is required. It is desired to develop a method for accurately connecting a semiconductor chip having such a fine pad pitch to a carrier substrate. For that purpose, the bump surface is required to be flattened, the bump pitch is made uniform, and a high-precision alignment technique is required.

[0006]

The CSP comprises a semiconductor chip, bumps provided on electrodes, and a carrier multilayer substrate. The bump is formed by coating a photosensitive resist on an Si wafer to which a barrier metal is attached, and forming a solder or plated bump through an opening formed by a photolithography method so as to match an electrode (pad) portion of the semiconductor chip. Further, the electrode pattern on the carrier substrate side is formed by etching according to a photoresist pattern formed by a photolithography method. The photolithography method requires steps of coating, drying, exposing, developing, and curing a photoresist on a substrate. The pattern accuracy is good, but the number of steps is large, and the process cost is high. When creating a CSP by flip-chip mounting, it is necessary to turn the semiconductor wafer or chip upside down and connect the bumps and the electrodes on the substrate. However, since the bump positions and the electrode positions are not visible, they must be aligned. Is extremely difficult. Although alignment is performed with respect to the position reference provided on the side surface, deviation from the position reference is a fatal problem and the mounting yield is reduced.

[0007] In the case of stud bumps in which bumps are formed by a method similar to the wire bonding method, there is a problem in that since the bumps are formed one pad at a time, the pad positions are individually shifted due to variations in the control accuracy of equipment. In this case, even if the alignment between the bump pattern on the semiconductor wafer or chip and the electrode pattern on the substrate is sufficient, the mounting yield is reduced due to the displacement of each bump.

According to the present invention, the second bumps having substantially the same shape as the first bumps formed on the semiconductor wafer or the chip can be formed at substantially the same position on the carrier substrate. It is an object of the present invention to provide a chip size package and a manufacturing method capable of connecting with high accuracy and manufacturing a highly reliable CSP with high yield.

[0009]

The present invention is implemented by the following procedure. That is, the semiconductor wafer provided with the first bumps is stamped or pasted on the carrier substrate as a stamper on the carrier substrate coated with a resin having a desired thickness, thermally cured, and then the semiconductor wafer or chip is separated. By the stamping step and the peeling step, a concave pattern is formed on the resin on the carrier substrate at a position corresponding to the bump on the semiconductor wafer. The concave pattern is opened at the position of the electrode on the carrier substrate, but since a small amount of resin remains on the electrode, the resin is removed by a plasma asher.

[0010] By flowing a solder paste or a conductive paste into the recesses by a printing method, the first paste on the semiconductor substrate is formed.
A second bump having the same shape as the bump is formed on the carrier substrate. Thereafter, the bumps and the substrate electrodes are connected again by attaching a semiconductor wafer or chip with bumps on the carrier substrate with reference to the side guide again.

Further, in the step of attaching the semiconductor wafer or chip to the carrier substrate, a pair of bumps and a wiring between bumps are previously formed on the semiconductor wafer or chip in order to highly accurately and automatically perform mutual alignment. A connection detecting element comprising a pair of bumps corresponding to bumps on a semiconductor wafer or a chip on a carrier substrate, a wiring penetrating through the carrier substrate, and a pair of external electrodes, and measuring the resistance between the pair of electrodes. Controls the optimization of positioning.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a CS according to an embodiment of the present invention.
It is sectional drawing of P. Reference numeral 1 denotes a semiconductor wafer or chip, and a first bump 2 made of a conductive material is formed on each pad. Reference numeral 3 denotes a carrier substrate, which is a multilayer substrate including an insulator 4, a wiring layer 5, a via hole 6, a substrate-side electrode 7, and the like, and can convert a four-sided pad array into a two-dimensional grid array. Reference numeral 8 denotes a second bump formed on the carrier substrate 3 and is surrounded by a polyimide or epoxy resin 9. The semiconductor chip 1 is connected to the carrier substrate 3 via the first bump 2 and the second bump 8.
Reference numeral 10 denotes a sealing resin, and reference numeral 11 denotes solder bumps arranged in a grid for connecting the CSP and the printed circuit board.

A second bump 8 having substantially the same shape as the first bump formed on the semiconductor wafer or chip 1 is formed at a corresponding position on the carrier substrate 3 side. Second bump 8
Is formed by a stamper method as shown in the following manufacturing method. Since the second bumps 8 are formed corresponding to the first bumps 2 on the semiconductor wafer or chip 1 to be mounted on each other, that is, even if the position of the first bumps 2 is shifted,
Since the second bumps 8 are correspondingly displaced, a decrease in mounting yield due to misalignment is minimized.

Even if the bumps become high (> 50 μm), the bump material on the carrier substrate 3 side is wrapped with resin, so that in the step of connecting the semiconductor wafer or chip 1 and the carrier substrate 3, the bump material is Does not flow in the plane direction. Therefore, fine connection is possible. In the CSP, matching between the thermal expansion coefficient of the semiconductor wafer or chip 1 and the thermal expansion coefficient of the carrier substrate 3 is required from the viewpoint of reliability. That is, when there is a large mismatch in the coefficient of thermal expansion, a shear stress is applied to the bump portion in the thermal cycle test, and the electrical connection is broken. However, in the present structure, the bump height is doubled as compared with the conventional CSP due to the two-stage bump, so that the shear stress is reduced, and the distance between the semiconductor wafer or the semiconductor chip 1 and the carrier substrate 3 is reduced. Is reduced to a minimum due to a mismatch in the thermal expansion coefficient. Further, after the connection, since the first bumps 2 and the second bumps 8 are both surrounded by the resin, stress due to thermal expansion distortion is reduced.

FIG. 2 shows a method for manufacturing a CSP according to the present invention. As shown in FIG. 2A, a substrate-side electrode 7 is formed on the carrier substrate 3. The side where the electrode 7 is located is the surface of the carrier substrate 3, and a precursor of polyimide or epoxy resin 9 is applied here as shown in FIG. After drying, as shown in FIG. 2 (c), the semiconductor wafer or chip 1 with bumps is imprinted or bonded on this surface with its back face down.

In this step, the bumps on the semiconductor wafer or chip 1 penetrate into the uncured resin, push the resin layer, and reach the vicinity of the electrodes 7 on the carrier substrate 3. In this state, these resins are thermally cured. The curing temperature is about 150-300C. After curing, the first bumped semiconductor wafer or chip 1 is separated from the carrier substrate 3. By this step, the first bump 2 on the semiconductor wafer or chip 1 is formed on the carrier substrate 3 as shown in FIG.
And a pair of recesses 9a are formed.

Thereafter, although not shown, the resin layer slightly remaining on the electrode 7, that is, on the bottom of the depression 9a is removed by a plasma asher. As shown in FIG. 2E, a conductive paste or a solder paste is buried in the depression on the carrier substrate by a printing method. In the case of a conductive paste, the surface can be further stabilized by applying an Au film to the surface by plating or vapor deposition. By this step, the second bumps 8 of the same shape that form a pair with the first bumps 2 on the semiconductor wafer or chip 1 are formed at the same positions on the carrier substrate 3 side.

Next, as shown in FIG. 2 (f), the semiconductor wafer or the chip 1 is turned upside down, and the carrier is aligned while the reference side of the peripheral portion and the reference of the peripheral portion of the carrier substrate 3 are aligned. It is attached to the surface of the substrate 3. The CSP is completed by injecting the sealing resin 10 from the side surface and curing the resin.

In the present manufacturing method, since the stamping method, that is, the stamping method, which is simpler than the photolithographic method, is used for forming the bump shape, there is no need to impart photosensitivity to the polyimide or epoxy resin 9. Therefore, the selection range of these resin materials is wide, and it is possible to select a resin with higher reliability in terms of moisture absorption characteristics and the like.

FIG. 3 shows a CSP having a three-stage bump structure composed of a bump on a semiconductor wafer or chip 1 and a two-stage bump on a carrier substrate 3. This embodiment is shown in FIG.
The structure has a third bump 12 added thereto. In general, it has already been described that there is a difference between the thermal expansion coefficient of a semiconductor wafer or a chip and the thermal expansion coefficient of a carrier substrate, and in a thermal cycle test, a shear stress is applied to a bump portion to cause a connection failure. When the bumps are made higher by forming three bumps as in the embodiment, the shear stress is further reduced, and the reliability is improved. The CSP of the present embodiment is shown in FIG.
The third bump 12 can be formed by adding the steps of FIGS. 2B to 2E in the manufacturing method of FIG.

Next, a description will be given of a high-precision alignment when the semiconductor wafer or chip 1 and the carrier substrate 3 are connected. This alignment structure and method are particularly effective for producing a CSP at the wafer level where high alignment accuracy is required.

The alignment of the present invention is as shown in FIG.
Connection detection elements 13a, 13b, 13c, and 13d with bumps in which connections for connection detection are formed in the squares of the semiconductor wafer or chip 1 and the carrier substrate 3 are formed in advance. FIG. 5 shows a cross section of the connection detecting element 13a. FIG.
3A is a cross-sectional view of the connection detecting element 13a formed on the semiconductor wafer or chip 1 side, and is composed of a pair of first bumps 2 provided with wirings 14. FIG. FIG. 5B shows the carrier substrate 3.
FIG. 10 is a cross-sectional view of the connection detection element 13a formed on the side of the semiconductor device, showing a pair of second bumps 8 provided on the carrier substrate 3 and a pair of external detection terminals connected by through holes 15 or via holes 6 connected to the respective second bumps 8; It consists of 16.

The operation of the positioning method using these detecting elements will be described. If the first bump 2 and the second bump 8 corresponding to each other are not connected due to a displacement during mounting, the external detection terminals 16 are non-conductive,
Alternatively, the electric resistance becomes very large. When the displacement is small, the electric resistance between the external detection terminals 16 is small, which is a value estimated from the structure. The optimum alignment state is when the resistance values of the four external detection terminals are all small.
That is, the connection state is optimal. If the four corners are in the optimum alignment state, the connection between the first bump and the second bump necessary for the operation inside the four corners is in the optimum state. 4
When the connection detecting elements are arranged at the corners, not only the planar alignment but also the accuracy of the inclination in the height direction can be detected. For example, the connection detecting elements 13a, 13b, 13c, 1
3d are represented by R (a), R (b), R
(C), R (d), and R (a)> R (b) ≒ R (d)
> R (c) indicates that the gap between the wafer or chip 1 and the carrier substrate 3 is large on the detection element 13a side. FIG. 4 illustrates the case where the connection detection elements 13 are arranged at four corners. However, if there is no space, even if a pair of connection detection elements 13 are arranged at both ends, planar alignment can be detected. Conversely, in order to obtain more detailed position information, it is possible to arrange a larger number of pairs of connection detecting elements 13.

In the above description, the case where a polyimide or epoxy resin for plate making is used has been described. However, the resin must be cured at a temperature of 400 ° C. or less at which the semiconductor device thermally breaks down, have low hygroscopicity, and have good mold release characteristics. If so, other resins can be used.

[0026]

As is apparent from the above description, according to the present invention, the second bump having substantially the same shape as the first bump formed on the semiconductor wafer or the chip is provided at the substantially same position on the carrier substrate. Because it can be formed, and since bumps having a high bump height can be connected with high accuracy, a highly reliable CSP can be manufactured with high yield.

Further, since no photolithography step is required, the process is simple and the process cost is low.

By providing the position detecting elements at two or four corners of the semiconductor wafer or chip and the carrier substrate, the alignment state can be detected as an electric signal, so that high-precision control can be performed on the alignment.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a CSP according to an embodiment of the present invention;

FIG. 2 shows a method for manufacturing a CSP according to the present invention.

FIG. 3 shows a CSP having a three-stage bump structure according to the present invention.
Cross section of

FIG. 4 is a plan view of a connection detection element used for mounting a CSP according to the present invention.

FIG. 5 is a cross-sectional view of a connection detection element used for mounting a CSP according to the present invention.

FIG. 6 is a sectional view of a CSP in a conventional example.

FIG. 7 is a plan view of the front and back surfaces of the carrier substrate.

[Explanation of symbols]

1 ··· semiconductor wafer or chip 2 ··· first bump formed on pad 3 ··· carrier substrate 7 ··· substrate-side electrode 8 ··· second formed on carrier substrate Bump 9 ... Polyimide or epoxy resin 10 ... Resin for sealing 11 ... Solder bump 13a, 13b, 13c, 13d ... Connection detecting element 14 ... Semiconductor wafer Alternatively, a wiring layer provided on the chip 15: a through-hole conductive layer 16: an external detection terminal

Claims (8)

[Claims] 1. A chip size package, wherein a second bump having substantially the same shape and arrangement as a first bump formed on a semiconductor wafer or chip is formed on a carrier substrate. 2. A recess formed by peeling a semiconductor wafer or a semiconductor chip provided with the first bump on a carrier substrate coated with a resin and then peeling the second bump having substantially the same shape and the same arrangement. 2. The chip size package according to claim 1, wherein the chip size package is formed on a chip. 3. A third bump having substantially the same shape as the first bump is formed at a substantially corresponding position on the second bump already formed on the carrier substrate. 1 chip size package. 4. A concave portion is formed at a position on the carrier substrate corresponding to the first bump by pressing the semiconductor wafer or chip having the first bump on a carrier substrate coated with a resin precursor by using the stamper as a stamper and thermally curing the resin. And forming a second bump on the substrate side by embedding solder or conductive paste therein, and connecting the semiconductor wafer or chip with the first bump used as a stamper to the carrier substrate. Manufacturing method of size package. 5. The method according to claim 4, wherein a precursor of a polyimide resin or an epoxy resin is applied. 6. A method for manufacturing a chip-size package according to claim 4, wherein a multilayer carrier substrate having all-layer via holes is used as the carrier substrate. 7. A connection detecting element having a pair of wiring-provided bumps provided on a semiconductor wafer or chip, a pair of bumps or electrodes provided on a carrier substrate, and a pair of external electrodes. And chip size package. 8. A corner or two corners of a semiconductor wafer or chip.
A chip size package by arranging the connection detection elements according to claim 7 at corners, detecting a resistance value between external electrode terminals of each connection detection element, and performing control so as to minimize a resistance value between each external electrode terminal. How to align the mounting position.