JP3598189B2 - Chip size package, its manufacturing method, and its mounting alignment method - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a chip size package for mounting a semiconductor chip on a circuit board at a high density and a method of manufacturing the same.
[0002]
[Prior art]
The demand for high-density mounting has been increasing with the trend of miniaturization and higher functionality of electronic devices. These demands are being met to some extent by recent breakthroughs in surface mounting technology. Elemental technologies for high-density mounting include miniaturization of components to be mounted including packages, densification of connection terminals, densification of circuit patterns, low thermal resistance, and the like. The mounted components mainly include passive components such as resistors and capacitors as well as semiconductor components such as ICs and LSIs.
[0003]
In particular, the progress of semiconductor components has been remarkable, and from a package point of view, progress has been made from DIL packages to QFP packages and BGA packages. The BGA package includes a semiconductor chip 1, connection bumps 2 attached to the semiconductor chip, and a carrier substrate 3, as shown in a sectional view of FIG. The carrier substrate 3 includes a substrate-side electrode 7, an insulating layer 4, a wiring layer 5, a via hole 6, a connection bump 11 as an external connection terminal, and the like, which are disclosed in, for example, JP-A-61-203648 and JP-A-6-296080. I have. FIG. 7A is a plan view of the front surface of the carrier substrate 3 on the semiconductor chip 1 side, and FIG. 7B is a plan view of the rear surface of the carrier substrate 3. As shown in FIG. 7A, pads and bumps are arranged at high density along the four sides around the semiconductor chip between the semiconductor chip 1 and the carrier substrate 3 and are connected to the electrodes 7 on the carrier substrate 3. ing. Since the external connection terminals 11 are arranged two-dimensionally and in a grid on the back surface of the carrier substrate 3, the number of bumps per area can be maximized by setting the bump pitch to a specified value. That is, the carrier substrate 3 has a function of changing the pad arrangement of the four-sided arrangement into a two-dimensional grid arrangement.
[0004]
With such a structure, even if the number of external connection terminals 11 increases with high performance, it is possible to minimize an increase in package size. If a BGA package is used, a package almost the same size as a semiconductor chip, that is, a chip size package can be realized. Hereinafter, the chip size package is referred to as CSP. In addition, passive components such as resistors and capacitors also respond to the demand for high-density surface mounting, and small chip components of 1 mm □ or less have been developed and put into practical use. ing.
[0005]
In the CSP, a connection structure and a connection method between a bump provided on an electrode (pad) of a semiconductor chip and a carrier substrate have a large influence on an assembly yield and reliability. In the case of a high-performance chip, the number of pads becomes several hundreds or more, and a pad pitch of 0.1 mm or less is required. It is desired to develop a method for accurately connecting a semiconductor chip having such a fine pad pitch to a carrier substrate. For that purpose, a technique for flattening the bump surface, making the bump pitch uniform, and a high-precision alignment technique is required.
[0006]
[Problems to be solved by the invention]
The CSP includes a semiconductor chip, bumps provided on electrodes, and a carrier multilayer substrate. The bump is formed by coating a photosensitive resist on a Si wafer provided with a barrier metal, and forming a solder or plating bump through an opening formed by a photolithography method so as to match an electrode (pad) portion of the semiconductor chip. The electrode pattern on the carrier substrate side is formed by etching according to a photoresist pattern formed by a photolithography method. The photolithography method requires steps of applying a photoresist on a substrate, drying, exposing, developing, and curing. The pattern accuracy is good, but the number of steps is large, and the process cost is high. When creating a CSP by flip-chip mounting, it is necessary to connect the bumps and the electrodes on the substrate with the semiconductor wafer or chip turned upside down. Is extremely difficult. Although alignment is performed with respect to the position reference provided on the side surface, deviation from the position reference is a fatal problem, and the mounting yield is reduced.
[0007]
In the case of stud bumps in which bumps are formed by a method similar to the wire bonding method, there is a problem in that since the bumps are formed one pad at a time, the pad positions are individually shifted due to variations in the control accuracy of equipment. In this case, even if the alignment between the bump pattern on the semiconductor wafer or chip and the electrode pattern on the substrate is sufficient, the mounting yield is reduced due to displacement of individual bumps.
[0008]
According to the present invention, since a second bump having substantially the same shape as a first bump formed on a semiconductor wafer or a chip can be formed at substantially the same position on a carrier substrate, bumps having a high bump height are connected with high precision. It is an object of the present invention to provide a chip size package and a manufacturing method capable of manufacturing a highly reliable CSP with high yield.
[0009]
[Means for Solving the Problems]
The present invention is performed by the following procedure. That is, the semiconductor wafer provided with the first bumps is stamped or pasted on the carrier substrate as a stamper on a carrier substrate coated with a resin having a desired thickness, thermally cured, and then the semiconductor wafer or chip is separated. By the stamping step and the peeling step, a concave pattern is formed on the resin on the carrier substrate at a position corresponding to the bump on the semiconductor wafer. The concave pattern is opened at the position of the electrode on the carrier substrate, but since a small amount of resin remains on the electrode, the resin is removed by a plasma asher.
[0010]
A second bump having the same shape as the first bump on the semiconductor substrate is formed on the carrier substrate by pouring a solder paste or a conductive paste into the concave portion by a printing method. Then, the bump and the substrate electrode are connected again by attaching a semiconductor wafer or a chip with a bump on the carrier substrate with reference to the side guide again.
[0011]
Furthermore, in the process of attaching the semiconductor wafer or chip to the carrier substrate, in order to perform mutual alignment with high accuracy and automation, a connection detection including a pair of bumps and wiring between bumps is previously performed on the semiconductor wafer or chip. The element is provided with a pair of bumps corresponding to bumps on a semiconductor wafer or a chip on a carrier substrate, wiring penetrating through the carrier substrate, and a pair of external electrodes, and measuring a resistance between the pair of electrodes to position the element. Perform optimization control for alignment.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0013]
FIG. 1 is a sectional view of a CSP according to an embodiment of the present invention. Reference numeral 1 denotes a semiconductor wafer or chip, and a first bump 2 made of a conductive material is formed on each pad. Reference numeral 3 denotes a carrier substrate, which is a multilayer substrate including an insulator 4, a wiring layer 5, a via hole 6, a substrate-side electrode 7, and the like, and can convert a four-sided pad arrangement into a two-dimensional grid arrangement. Reference numeral 8 denotes a second bump formed on the carrier substrate 3 and is surrounded by a polyimide or epoxy resin 9. The semiconductor chip 1 is connected to the carrier substrate 3 via the first bump 2 and the second bump 8. Reference numeral 10 denotes a sealing resin, and reference numeral 11 denotes solder bumps arranged in a grid for connecting the CSP and the printed circuit board.
[0014]
A second bump 8 having substantially the same shape as the first bump formed on the semiconductor wafer or chip 1 is formed at a corresponding position on the carrier substrate 3 side. The second bump 8 is formed by a stamper method as shown in the following manufacturing method. Since the second bumps 8 are formed corresponding to the first bumps 2 on the semiconductor wafer or the chip 1 to be mounted on each other, that is, even if the first bumps 2 are displaced, the second bumps 8 A corresponding decrease in the mounting yield due to misalignment can be minimized.
[0015]
Even if the bumps become high (> 50 μm), the bump material on the carrier substrate 3 side is wrapped with resin, so that the bump material may be in a planar direction in the connection process between the semiconductor wafer or chip 1 and the carrier substrate 3. Not flowing. Therefore, fine connection is possible. In the CSP, it is necessary to match the thermal expansion coefficient of the semiconductor wafer or chip 1 with the thermal expansion coefficient of the carrier substrate 3 from the viewpoint of reliability. That is, when there is a large mismatch in the coefficient of thermal expansion, a shear stress is applied to the bump portion in the thermal cycle test, and the electrical connection is broken. However, in this structure, since the bumps are two-stage, the height of the bumps is doubled as compared with the conventional CSP, so that the shear stress is reduced, and the distance between the semiconductor wafer or the semiconductor chip 1 and the carrier substrate 3 is reduced. Is reduced to a minimum due to a mismatch in the thermal expansion coefficient. Further, after the connection, since the first bumps 2 and the second bumps 8 are both surrounded by the resin, stress due to thermal expansion distortion is reduced.
[0016]
FIG. 2 shows a method for manufacturing a CSP according to the present invention. As shown in FIG. 2A, a substrate-side electrode 7 is formed on the carrier substrate 3. The side where the electrode 7 is located is the surface of the carrier substrate 3, and a precursor of polyimide or epoxy resin 9 is applied here as shown in FIG. After the drying, as shown in FIG. 2 (c), the semiconductor wafer or chip 1 with bumps is imprinted or bonded on the surface with the back side facing down.
[0017]
By this step, the bumps on the semiconductor wafer or the chip 1 penetrate into the uncured resin and push the resin layer to reach the vicinity of the electrodes 7 on the carrier substrate 3. In this state, these resins are thermally cured. The curing temperature is about 150-300 ° C. After curing, the first bumped semiconductor wafer or chip 1 is separated from the carrier substrate 3. By this step, as shown in FIG. 2D, a depression 9a paired with the first bump 2 on the semiconductor wafer or chip 1 is formed on the carrier substrate 3.
[0018]
Thereafter, although not shown, the resin layer slightly remaining on the electrode 7, that is, the bottom of the depression 9a is removed by a plasma asher. As shown in FIG. 2E, a conductive paste or a solder paste is buried in the depression on the carrier substrate by a printing method. In the case of a conductive paste, the surface can be further stabilized by applying an Au film to the surface by plating or vapor deposition. By this step, the second bumps 8 of the same shape, which form a pair with the first bumps 2 on the semiconductor wafer or chip 1, are formed at the same positions on the carrier substrate 3 side.
[0019]
Next, as shown in FIG. 2F, the surface of the carrier substrate 3 is aligned with the reference side of the peripheral portion and the reference of the peripheral portion of the carrier substrate 3 while the semiconductor wafer or the chip 1 is turned upside down. Attach to. The CSP is completed by injecting the sealing resin 10 from the side and curing the resin.
[0020]
In the present manufacturing method, a stamping method, which is a simpler stamping method than the photolithographic method, is used for forming the bump shape, so that it is not necessary to impart photosensitivity to the polyimide or epoxy resin 9. Therefore, the selection range of these resin materials is wide, and it is possible to select a resin with higher reliability in terms of moisture absorption characteristics and the like.
[0021]
FIG. 3 shows a CSP having a three-stage bump structure including a bump on a semiconductor wafer or chip 1 and a two-stage bump on a carrier substrate 3. This embodiment has a structure in which a third bump 12 is added as compared with FIG. Generally, it has already been described that there is a difference between the thermal expansion coefficient of a semiconductor wafer or a chip and the thermal expansion coefficient of a carrier substrate, and in a thermal cycle test, a shear stress is applied to a bump portion to cause a connection failure. When the bumps are made even higher by forming three bumps as in the embodiment, the shear stress is further reduced, and the reliability is improved. The CSP of the present embodiment can form the third bump 12 by adding the steps of FIG. 2B to FIG. 2E in the manufacturing method of FIG.
[0022]
Next, a description will be given of a high-accuracy alignment when the semiconductor wafer or chip 1 and the carrier substrate 3 are connected. This alignment structure and method are particularly effective for producing a CSP at the wafer level where high alignment accuracy is required.
[0023]
In the alignment of the present invention, as shown in FIG. 4, bump-formed connection detecting elements 13a, 13b, 13c, and 13d in which connection detection connection lines are formed in advance on squares of the semiconductor wafer or chip 1 and the carrier substrate 3 are formed. Keep it. FIG. 5 shows a cross section of the connection detecting element 13a. FIG. 5A is a cross-sectional view of the connection detecting element 13a formed on the semiconductor wafer or chip 1 side, and is composed of a pair of first bumps 2 provided with wiring. FIG. 5B is a cross-sectional view of the connection detecting element 13 a formed on the carrier substrate 3 side, and shows a pair of second bumps 8 provided on the carrier substrate 3 and a through hole 15 or a via hole connected to each second bump 8. 6 comprises a pair of external detection terminals 16 connected.
[0024]
The operation of the positioning method using these detection elements will be described. If the first bump 2 and the second bump 8 corresponding to each other are not connected due to a positional shift during mounting, the external detection terminals 16 are non-conductive or have extremely large electric resistance. When the displacement is small, the electric resistance between the external detection terminals 16 is small, which is a value estimated from the structure. The case where the resistance values of the four external detection terminals are all small is the optimum alignment state, that is, the optimum connection state. If the four corners are in the optimum alignment state, the connection between the first bump and the second bump necessary for the operation inside the four corners is in the optimum state. When the connection detecting elements are arranged at the four corners, not only the planar alignment but also the accuracy of the inclination in the height direction can be detected. For example, the resistance values of the connection detection elements 13a, 13b, 13c, and 13d are R (a), R (b), R (c), and R (d), and R (a)> R (b) ≒ R If (d)> R (c), it indicates that the gap between the wafer or chip 1 and the carrier substrate 3 is large on the detection element 13a side. FIG. 4 illustrates the case where the connection detection elements 13 are arranged at four corners. However, if there is no space, even if a pair of connection detection elements 13 are arranged at both ends, a planar alignment can be detected. Conversely, to obtain more detailed position information, it is possible to arrange a larger number of pairs of connection detecting elements 13.
[0025]
In the above description, the case where a polyimide or epoxy resin for plate making is used has been described. However, if the resin is cured at a temperature of 400 ° C. or less at which the semiconductor device is thermally broken, the resin has a low hygroscopic property and a good release property. Other resins can also be used.
[0026]
【The invention's effect】
As is apparent from the above description, according to the present invention, the second bump having substantially the same shape as the first bump formed on the semiconductor wafer or the chip can be formed at the substantially same position on the carrier substrate. Further, since bumps having a high bump height can be connected with high accuracy, a CSP with high reliability can be manufactured with high yield.
[0027]
Further, since a photolithography step is not required, the process is simple and the process cost is low.
[0028]
By providing the position detection elements at two or four corners of the semiconductor wafer or chip and the carrier substrate, the alignment state can be detected as an electric signal, so that the alignment can be controlled with high precision.
[Brief description of the drawings]
FIG. 1 is a sectional view showing a structure of a CSP according to an embodiment of the present invention; FIG. 2 is a method of manufacturing a CSP according to the present invention; FIG. 3 is a sectional view of a CSP having a three-stage bump structure according to the present invention; FIG. 4 is a plan view of a connection detection element used for mounting a CSP according to the present invention. FIG. 5 is a cross-sectional view of a connection detection element used for mounting a CSP according to the present invention. FIG. 6 is a cross-sectional view of a CSP in a conventional example. Plan view on front and back of carrier substrate [Explanation of reference numerals]
1, a semiconductor wafer or a chip 2, a first bump 3 formed on a pad, a carrier substrate 7, a substrate-side electrode 8, a second electrode formed on a carrier substrate Bump 9, polyimide or epoxy resin 10, sealing resin 11, solder bumps 13a, 13b, 13c, 13d for connecting CSP and printed circuit board, connection detecting element 14, semiconductor wafer Or the wiring layer 15 provided on the chip: the through-hole conductive layer 16: the external detection terminal

Claims (6)

A second bump having substantially the same shape and the same arrangement as the first bump formed on the semiconductor wafer or chip is formed on the carrier substrate ,
The second bump is formed in a concave portion formed by stamping a semiconductor wafer or a semiconductor chip provided with the first bump on a carrier substrate coated with a resin and then peeling off the resin. Chip size package. The first bump and the third bumps substantially the same shape, the chip size of claim 1, characterized in that it is formed in substantially corresponding positions on the second bump already formed on the carrier substrate package. A semiconductor wafer or chip with a first bump is used as a stamper and pressed against a carrier substrate coated with a resin precursor to be thermally cured, thereby forming a recess at a position of the carrier substrate corresponding to the first bump, and soldering there. Or forming a second bump on the substrate side by embedding a conductive paste, and then connecting the semiconductor wafer or the chip with the first bump used as a stamper to the carrier substrate. . Method of manufacturing a chip size package of claim 3, wherein the precursor of the resin is a polyimide resin or epoxy resin. Claim, characterized in that it comprises a pair of bumps subjected to wiring provided on a semiconductor wafer or chip, a pair of bumps or electrodes provided on the carrier substrate, and a connection detection device having a pair of external electrodes 1 Or 2 chip size packages. A connection detecting elements are arranged at the four corners or two corners of the semiconductor wafer or chip, and detecting the resistance value between the external electrode terminals of the connection detection device, control so as to minimize the resistance between the external electrode terminals 6. The method of claim 5 , wherein the mounting position of the chip size package is adjusted.

Images