JP2002064177A - Semiconductor element and its manufacturing method - Google Patents
Semiconductor element and its manufacturing methodInfo
- Publication number
- JP2002064177A JP2002064177A JP2000248061A JP2000248061A JP2002064177A JP 2002064177 A JP2002064177 A JP 2002064177A JP 2000248061 A JP2000248061 A JP 2000248061A JP 2000248061 A JP2000248061 A JP 2000248061A JP 2002064177 A JP2002064177 A JP 2002064177A
- Authority
- JP
- Japan
- Prior art keywords
- chip components
- substrate
- insulating film
- chip
- protrusions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、基板上に複数のチ
ップ部品を実装して成る半導体素子およびその製造方法
に関する。The present invention relates to a semiconductor device having a plurality of chip components mounted on a substrate and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】ＬＳＩは様々な用途で活用されていると
ともに、高集積化および高密度化を目指した開発が日々
続けられている。近年では、複数のチップを一つのＬＳ
Ｉに集積してパッケージ化したマルチチップモジュール
も考えられており、その製造技術も盛んになってきてい
る。2. Description of the Related Art LSIs are used for various purposes, and developments for high integration and high density are being continued every day. In recent years, multiple chips have been
A multi-chip module integrated and packaged in the I. has also been considered, and its manufacturing technology has also become active.
【０００３】マルチチップモジュールの一形態として、
複数のチップを１枚の基板上に並べて配置し、各チップ
と基板とをワイヤーボンドで配線してチップ間の導通や
外部との接続用のパッドとの導通を得るものがある。As one form of a multi-chip module,
There is a type in which a plurality of chips are arranged side by side on a single substrate, and each chip and the substrate are wired by wire bonding to obtain conduction between the chips and a pad for connection to the outside.
【０００４】また、ワイヤーボンド以上に配線密度を高
める必要から、各チップ間を直接配線パターンで接続す
るものもある。各チップ間を直接配線パターンで接続す
るには、チップ上およびチップ間に絶縁膜を塗布し、そ
の絶縁膜の表面から各チップのパッド上にスルーホール
を形成した後、スルーホール内を導体で埋め込み、各導
体間をつなぐよう絶縁膜上に配線パターンを形成してい
る。[0004] Further, since it is necessary to increase the wiring density more than the wire bonding, there is a type in which each chip is directly connected by a wiring pattern. To connect each chip directly with a wiring pattern, apply an insulating film on the chips and between the chips, form through holes on the pads of each chip from the surface of the insulating film, and then use conductors in the through holes. A wiring pattern is formed on the insulating film so as to be embedded and to connect between the conductors.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、このよ
うな配線パターンで直接チップ間を接続する半導体素子
では、チップ間における絶縁膜の埋め込みが最大の課題
となる。すなわち、複数のチップを実装し、その上に絶
縁膜を塗布した場合、チップ間の絶縁膜に段差が生じ、
この段差が大きいと配線パターンの露光時の焦点深度が
大きすぎて正確な露光が行えず、配線パターン形成の妨
げとなってしまう。However, embedding an insulating film between chips is the biggest problem in a semiconductor element in which chips are directly connected by such a wiring pattern. In other words, when a plurality of chips are mounted and an insulating film is applied thereon, a step occurs in the insulating film between the chips,
If the level difference is large, the depth of focus at the time of exposure of the wiring pattern is too large, so that accurate exposure cannot be performed and the formation of the wiring pattern is hindered.
【０００６】[0006]
【課題を解決するための手段】本発明は、このような課
題を解決するために成されたものである。すなわち、本
発明の半導体素子は、基板上に実装される複数のチップ
部品と、複数のチップ部品の間で、そのチップ部品の実
装面から突出する凸部と、複数のチップ部品および凸部
を覆う状態で形成される絶縁膜とを備えている。SUMMARY OF THE INVENTION The present invention has been made to solve such problems. That is, the semiconductor element of the present invention includes a plurality of chip components mounted on a substrate, a plurality of chip components, a protrusion projecting from the mounting surface of the chip component, and a plurality of chip components and protrusions. And an insulating film formed in a state of being covered.
【０００７】このような本発明の半導体素子では、複数
のチップ部品の間に凸部があることから、チップ部品間
の隙間が狭くなっており、この上に塗布される絶縁膜の
平坦性を向上できるようになる。In such a semiconductor device of the present invention, since there is a projection between a plurality of chip components, a gap between the chip components is narrowed, and the flatness of an insulating film applied thereon is reduced. Be able to improve.
【０００８】また、本発明の半導体素子の製造方法は、
基板上に凸部を形成する工程と、基板上の凸部が間とな
るよう複数のチップ部品を基板上に実装する工程と、複
数のチップ部品および凸部を覆う状態で絶縁膜を形成す
る工程とを備えている。Further, the method of manufacturing a semiconductor device according to the present invention comprises:
Forming a protrusion on the substrate, mounting a plurality of chip components on the substrate such that the protrusions on the substrate are interposed, and forming an insulating film covering the plurality of chip components and the protrusions And a process.
【０００９】このような本発明の半導体素子の製造方法
では、基板上に形成した凸部が間となるよう複数のチッ
プ部品を実装しているため、チップ部品間の隙間を凸部
で埋めることができ、その後に塗布する絶縁膜の段差を
減少させることができる。In the method of manufacturing a semiconductor device according to the present invention, since a plurality of chip components are mounted such that the protrusions formed on the substrate are interposed, the gap between the chip components is filled with the protrusions. And the step of the insulating film to be subsequently applied can be reduced.
【００１０】[0010]
【発明の実施の形態】以下、本発明の実施の形態を図に
基づいて説明する。図１は、第１実施形態を説明する模
式断面図である。すなわち、この半導体素子１は、基板
１０上に実装される複数のチップ部品２ａ、２ｂと、こ
のチップ部品２ａ、２ｂの間に設けられている凸部１１
と、チップ部品２ａ、２ｂおよび凸部１１を覆う状態で
形成される絶縁膜３と、絶縁膜３上に形成され、チップ
部品２ａ、２ｂを電気的に接続する配線４とを備えてい
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic sectional view illustrating the first embodiment. That is, the semiconductor element 1 includes a plurality of chip components 2a and 2b mounted on a substrate 10 and a protrusion 11 provided between the chip components 2a and 2b.
And an insulating film 3 formed so as to cover the chip components 2a, 2b and the protrusions 11, and a wiring 4 formed on the insulating film 3 and electrically connecting the chip components 2a, 2b.
【００１１】この基板１としては、例えばシリコンウェ
ハを用いており、このシリコンウェハから成る基板１上
に複数のチップ部品２ａ、２ｂを所定の位置に実装す
る。なお、この図では２つのチップ部品２ａ、２ｂを実
装しているが、さらに多くのチップ部品を実装してもよ
い。また、半導体素子１としては、最終的に所定の大き
さにシリコンウェハから成る基板１を切断し、マルチチ
ップモジュール化してもよい。As the substrate 1, for example, a silicon wafer is used, and a plurality of chip components 2a, 2b are mounted at predetermined positions on the substrate 1 made of the silicon wafer. Although two chip components 2a and 2b are mounted in this figure, more chip components may be mounted. Further, as the semiconductor element 1, the substrate 1 made of a silicon wafer may be finally cut into a predetermined size to form a multi-chip module.
【００１２】基板１０上に形成される凸部１１として
は、絶縁材や金属材料を用いることができる。凸部１１
は、実装されるチップ部品２ａ、２ｂの高さとほぼ等し
い高さにするのが望ましい。この凸部１１が形成される
ことで、実装するチップ部品２ａ、２ｂの間は数十μｍ
あるものの、チップ部品２ａ、２ｂと凸部１１との隙間
は数μｍ程度になり、その上に塗布する絶縁膜３の段差
を少なくできるようになる。As the protrusions 11 formed on the substrate 10, an insulating material or a metal material can be used. Convex part 11
Is desirably set to a height substantially equal to the height of the chip components 2a and 2b to be mounted. Due to the formation of the protrusions 11, the distance between the mounted chip components 2a and 2b is several tens of μm.
However, the gap between the chip parts 2a and 2b and the protrusion 11 is about several μm, and the step of the insulating film 3 applied thereon can be reduced.
【００１３】次に、この半導体素子１の製造方法を図２
および図３の模式断面図に沿って説明する。先ず、図２
（ａ）に示すように、基板１０上に凸部１１を形成す
る。この凸部１１は、絶縁材でも金属材料でもよく、例
えば、スクリーン印刷法によって土手状に形成する。な
お、凸部１１の高さはチップ部品２ａ、２ｂの高さとほ
ぼ等しくすることが望ましい。Next, a method of manufacturing the semiconductor device 1 will be described with reference to FIG.
And a schematic cross-sectional view of FIG. First, FIG.
As shown in FIG. 1A, a projection 11 is formed on a substrate 10. The protrusion 11 may be made of an insulating material or a metal material, and is formed in a bank shape by, for example, a screen printing method. It is desirable that the height of the convex portion 11 be substantially equal to the height of the chip components 2a and 2b.
【００１４】次いで、図２（ｂ）に示すように、基板１
０上の凸部１１を間としてチップ部品２ａ、２ｂを実装
する。この際、凸部１１をアライメントマークとしてチ
ップ部品２ａ、２ｂを位置決めすると、各チップ部品２
ａ、２ｂを正確に実装できるとともに、各チップ部品２
ａ、２ｂと凸部１１とを非常に接近させることができ
る。Next, as shown in FIG.
The chip components 2a and 2b are mounted with the convex portion 11 on the space between them. At this time, when the chip parts 2a and 2b are positioned using the convex part 11 as an alignment mark, each chip part 2a is positioned.
a and 2b can be mounted accurately and each chip component 2
a, 2b and the convex portion 11 can be brought very close to each other.
【００１５】つまり、チップ部品２ａ、２ｂを直接接近
させるには、ダイボンド装置の機械的な位置合わせ精度
や、チップ部品２ａ、２ｂの衝突による破損を回避する
ため、ある程度余裕を持った間隔で配置する必要があ
る。しかし、各チップ部品２ａ、２ｂを凸部１１に対し
て位置合わせするには、凸部１１とチップ部品２ａ、２
ｂとの衝突によるチップ部品２ａ、２ｂの破損の危険が
少ないことから、ダイボンド装置の位置合わせ精度で実
装を行うことができ、各チップ部品２ａ、２ｂと凸部１
１とを接近させることができる。That is, in order to bring the chip components 2a and 2b directly closer to each other, the chip components 2a and 2b are arranged at an interval having a certain margin in order to prevent mechanical damage of the die components 2a and 2b due to mechanical alignment accuracy and collision of the chip components 2a and 2b. There is a need to. However, in order to align each of the chip components 2a and 2b with respect to the protrusion 11, the protrusion 11 and the chip components 2a and 2b
b, there is little risk of breakage of the chip components 2a, 2b due to the collision with the chip components 2a, 2b.
1 can be approached.
【００１６】次に、図３（ａ）に示すように、基板１０
上の凸部１１および各チップ部品２ａ、２ｂを覆う状態
で絶縁膜３を塗布する。ここで、絶縁膜３は、例えばス
ピンコーター等の装置によって回転塗布する。この絶縁
膜３の塗布では、チップ部品２ａ、２ｂ間が凸部１１に
よってほとんど埋められているため、塗布後の段差発生
を抑制できることになる。Next, as shown in FIG.
An insulating film 3 is applied so as to cover the upper convex portion 11 and the chip components 2a and 2b. Here, the insulating film 3 is spin-coated by a device such as a spin coater. In the application of the insulating film 3, since the space between the chip components 2a and 2b is almost completely filled with the convex portions 11, the occurrence of a step after application can be suppressed.
【００１７】絶縁膜３を塗布した後は、図３（ｂ）に示
すように、チップ部品２ａ、２ｂの配線パッド（図示せ
ず）上の絶縁膜３にスルーホール３１を形成する。この
スルーホール３１は、絶縁膜３上に塗布したレジストを
フォトリソグラフィー技術によってマスクとし、このレ
ジストのマスクを介したエッチングで形成される。After the application of the insulating film 3, as shown in FIG. 3B, through holes 31 are formed in the insulating film 3 on the wiring pads (not shown) of the chip components 2a and 2b. The through hole 31 is formed by using a resist applied on the insulating film 3 as a mask by a photolithography technique and etching through the resist mask.
【００１８】その後、図３（ｃ）に示すように、スルー
ホール３１（図３（ｂ）参照）内に電極材を埋め込んで
スルーホール電極３２を形成し、必要に応じてスルーホ
ール電極３２間を接続するよう配線４を絶縁膜３上に形
成する。Thereafter, as shown in FIG. 3C, a through-hole electrode 32 is formed by embedding an electrode material in the through-hole 31 (see FIG. 3B). Are formed on the insulating film 3 so as to connect them.
【００１９】本実施形態では、先に塗布した絶縁膜３の
平坦性が高いことから、スルーホール電極３２間を接続
する配線４を絶縁膜３上に形成するにあたり、露光を正
確に行うことができる。これにより、２つのチップ部品
２ａ、２ｂが電気的に接続され、半導体素子１が完成す
る。In this embodiment, since the flatness of the insulating film 3 previously applied is high, when the wiring 4 connecting between the through-hole electrodes 32 is formed on the insulating film 3, it is necessary to perform exposure accurately. it can. Thereby, the two chip components 2a and 2b are electrically connected, and the semiconductor element 1 is completed.
【００２０】なお、このようなチップ部品２ａ、２ｂか
ら成る半導体素子１の組みをシリコンウェハ等から成る
基板１０上に複数形成しておき、適宜切断することで１
つの半導体素子１（マルチチップモジュール）を構成し
てもよい。It should be noted that a plurality of sets of the semiconductor element 1 including such chip parts 2a and 2b are formed on a substrate 10 formed of a silicon wafer or the like, and are appropriately cut.
One semiconductor element 1 (multi-chip module) may be configured.
【００２１】また、上記説明した例では、凸部１１を２
つのチップ部品２ａ、２ｂ間に形成したが、各チップ部
品２ａ、２ｂの周囲を囲む状態で形成してもよい。この
ような囲まれた凸部１１では、この囲みの中に各チップ
部品２ａ、２ｂを実装することで位置合わせを容易にす
ることができるとともに、チップ部品２ａ、２ｂの位置
ずれを防止できるようになる。In the example described above, the protrusion 11 is
Although formed between the two chip components 2a and 2b, they may be formed so as to surround the respective chip components 2a and 2b. In the enclosed convex portion 11, the positioning can be facilitated by mounting the chip components 2a and 2b in the enclosure, and the displacement of the chip components 2a and 2b can be prevented. become.
【００２２】さらに、基板１０としてシリコンウェハを
用いる例を示したが、他の材料から成るウェハや、ウェ
ハ以外の板状基材を基板１０として用いてもよい。Further, although an example in which a silicon wafer is used as the substrate 10 has been described, a wafer made of another material or a plate-like base material other than a wafer may be used as the substrate 10.
【００２３】次に、第２実施形態の説明を行う。図４
は、第２実施形態を説明する模式断面図である。すなわ
ち、この半導体素子１は、基板１０上に実装される複数
のチップ部品２ａ、２ｂと、チップ部品２ａ、２ｂを実
装する位置に対応した基板１０に形成される凹部１２
と、この凹部１２によってチップ部品２ａ、２ｂの間に
設けられる凸部１１と、チップ部品２ａ、２ｂおよび凸
部１１を覆う状態で形成される絶縁膜３と、絶縁膜３上
に形成され、チップ部品２ａ、２ｂを電気的に接続する
配線４とを備えている。Next, a second embodiment will be described. FIG.
FIG. 4 is a schematic sectional view illustrating a second embodiment. That is, the semiconductor element 1 includes a plurality of chip components 2a and 2b mounted on the substrate 10 and a recess 12 formed on the substrate 10 corresponding to a position where the chip components 2a and 2b are mounted.
A convex portion 11 provided between the chip components 2a and 2b by the concave portion 12, an insulating film 3 formed so as to cover the chip components 2a and 2b and the convex portion 11, and formed on the insulating film 3; And a wiring 4 for electrically connecting the chip components 2a and 2b.
【００２４】この基板１としては、例えばシリコンウェ
ハを用いており、このシリコンウェハから成る基板１上
の複数のチップ部品２ａ、２ｂが実装される位置に凹部
１２を形成し、この凹部１２内に各々チップ部品２ａ、
２ｂを実装している。なお、この図では２つのチップ部
品２ａ、２ｂを実装しているが、さらに多くのチップ部
品を実装してもよい。また、半導体素子１としては、最
終的に所定の大きさにシリコンウェハから成る基板１を
切断し、マルチチップモジュール化してもよい。As the substrate 1, for example, a silicon wafer is used. A concave portion 12 is formed at a position where a plurality of chip components 2a and 2b are mounted on the substrate 1 made of the silicon wafer. Each of the chip components 2a,
2b is implemented. Although two chip components 2a and 2b are mounted in this figure, more chip components may be mounted. Further, as the semiconductor element 1, the substrate 1 made of a silicon wafer may be finally cut to a predetermined size to form a multi-chip module.
【００２５】基板１０上の凸部１１は、凹部１２の形成
によって基板１０と一体に形成されるもので、凹部１２
にチップ部品２ａ、２ｂを実装した際にそのチップ部品
２ａ、２ｂの上面と凸部１１の上面とがほぼ等しい位置
になることが望ましい。The convex portion 11 on the substrate 10 is formed integrally with the substrate 10 by forming the concave portion 12.
When the chip components 2a and 2b are mounted on the upper surface, it is desirable that the upper surfaces of the chip components 2a and 2b and the upper surface of the protrusion 11 be located at substantially the same position.
【００２６】この凹部１２内にチップ部品２ａ、２ｂを
実装することで、チップ部品２ａ、２ｂ間に凸部１１が
配置され、実装するチップ部品２ａ、２ｂの間は数十μ
ｍあるものの、チップ部品２ａ、２ｂと凸部１１との隙
間は数μｍ程度になり、その上に塗布する絶縁膜３の段
差を少なくできることになる。By mounting the chip components 2a and 2b in the concave portions 12, the convex portions 11 are arranged between the chip components 2a and 2b, and the distance between the mounted chip components 2a and 2b is several tens μm.
Although the distance is m, the gap between the chip parts 2a and 2b and the protrusion 11 is about several μm, and the step of the insulating film 3 applied thereon can be reduced.
【００２７】次に、この半導体素子１の製造方法を図５
および図６の模式断面図に沿って説明する。先ず、図５
（ａ）に示すように、基板１０上のチップ部品が実装さ
れる位置に凹部１２を形成する。凹部１２は、例えばウ
ェットエッチングによってチップ部品の高さを同じ程度
の深さに形成する。Next, a method of manufacturing the semiconductor device 1 will be described with reference to FIG.
And a schematic cross-sectional view of FIG. First, FIG.
As shown in FIG. 1A, a recess 12 is formed on the substrate 10 at a position where a chip component is mounted. The concave portion 12 is formed by, for example, wet etching so that the chip components have the same height.
【００２８】次いで、図５（ｂ）に示すように、基板１
０上の凹部１２内に各チップ部品２ａ、２ｂを実装す
る。この際、凸部１１をアライメントマークとしてチッ
プ部品２ａ、２ｂを実装すると、各チップ部品２ａ、２
ｂを正確に実装できるとともに、各チップ部品２ａ、２
ｂと凸部１１との非常に接近させることができる。ま
た、凹部１２はチップ部品２ａ、２ｂの外形に対応して
いることから、この中にチップ部品２ａ、２ｂを実装す
ることにより、実装後の位置ずれを防止できることにも
なる。Next, as shown in FIG.
Each of the chip components 2a and 2b is mounted in the concave portion 12 on the zero. At this time, when the chip parts 2a and 2b are mounted with the protrusions 11 as alignment marks, the chip parts 2a and 2b are mounted.
b can be mounted accurately, and each chip component 2a, 2
b and the convex portion 11 can be brought very close to each other. In addition, since the concave portion 12 corresponds to the outer shape of the chip components 2a and 2b, by mounting the chip components 2a and 2b therein, it is possible to prevent displacement after mounting.
【００２９】次に、図６（ａ）に示すように、基板１０
上の凸部１１および各チップ部品２ａ、２ｂを覆う状態
で絶縁膜３を塗布する。ここで、絶縁膜３は、例えばス
ピンコーター等の装置によって回転塗布する。この絶縁
膜３の塗布では、チップ部品２ａ、２ｂ間が凸部１１に
よってほとんど埋められているため、塗布後の段差発生
を抑制できることになる。Next, as shown in FIG.
An insulating film 3 is applied so as to cover the upper convex portion 11 and the chip components 2a and 2b. Here, the insulating film 3 is spin-coated by a device such as a spin coater. In the application of the insulating film 3, since the space between the chip components 2a and 2b is almost completely filled with the convex portions 11, the occurrence of a step after application can be suppressed.
【００３０】絶縁膜３を塗布した後は、図６（ｂ）に示
すように、チップ部品２ａ、２ｂの配線パッド（図示せ
ず）上の絶縁膜３にスルーホール３１を形成する。この
スルーホール３１は、絶縁膜３上に塗布したレジストを
フォトリソグラフィー技術によってマスクとし、このレ
ジストのマスクを介したエッチングで形成される。After the application of the insulating film 3, as shown in FIG. 6B, through holes 31 are formed in the insulating film 3 on the wiring pads (not shown) of the chip components 2a and 2b. The through hole 31 is formed by using a resist applied on the insulating film 3 as a mask by a photolithography technique and etching through the resist mask.
【００３１】その後、図６（ｃ）に示すように、スルー
ホール３１（図６（ｂ）参照）内に電極材を埋め込んで
スルーホール電極３２を形成し、必要に応じてスルーホ
ール電極３２間を接続するよう配線４を絶縁膜３上に形
成する。Thereafter, as shown in FIG. 6C, an electrode material is buried in the through-hole 31 (see FIG. 6B) to form a through-hole electrode 32. Are formed on the insulating film 3 so as to connect them.
【００３２】本実施形態では、先に塗布した絶縁膜３の
平坦性が高いことから、スルーホール電極３２間を接続
する配線４を絶縁膜３上に形成するにあたり、露光を正
確に行うことができる。これにより、２つのチップ部品
２ａ、２ｂが電気的に接続され、半導体素子１が完成す
る。In the present embodiment, since the insulating film 3 previously applied has high flatness, the exposure can be accurately performed when the wiring 4 connecting the through-hole electrodes 32 is formed on the insulating film 3. it can. Thereby, the two chip components 2a and 2b are electrically connected, and the semiconductor element 1 is completed.
【００３３】なお、このようなチップ部品２ａ、２ｂか
ら成る半導体素子１の組みをシリコンウェハ等から成る
基板１０上に複数形成しておき、適宜切断することで１
つの半導体素子１（マルチチップモジュール）を構成し
てもよい。It should be noted that a plurality of such sets of the semiconductor element 1 composed of the chip components 2a and 2b are formed on a substrate 10 made of a silicon wafer or the like, and are appropriately cut.
One semiconductor element 1 (multi-chip module) may be configured.
【００３４】また、基板１０としてシリコンウェハを用
いる例を示したが、他の材料から成るウェハや、ウェハ
以外の板状基材を基板１０として用いてもよい。Although an example in which a silicon wafer is used as the substrate 10 has been described, a wafer made of another material or a plate-like base material other than a wafer may be used as the substrate 10.
【００３５】また、本発明は、上記説明した第１実施形
態および第２実施形態を組み合わせた構成にしてもよ
い。すなわち、基板１０のチップ部品２ａ、２ｂを実装
する位置に凹部１２を形成するとともに、チップ部品２
ａ、２ｂの間に基板１０とは別体の凸部１１を形成し、
この凹部１２内にチップ部品２ａ、２ｂを実装して、絶
縁膜３で覆う構造にしてもよい。Further, the present invention may have a configuration in which the first and second embodiments described above are combined. That is, the concave portion 12 is formed at the position where the chip components 2a and 2b are mounted on the substrate 10, and the chip component 2
a, a projection 11 separate from the substrate 10 is formed between
The chip components 2 a and 2 b may be mounted in the recess 12 and covered with the insulating film 3.
【００３６】[0036]
【発明の効果】以上説明したように、本発明によれば次
のような効果がある。すなわち、複数のチップ部品間に
凸部が形成されていることから、これらの上に絶縁膜を
塗布した場合の段差を抑制でき、絶縁膜の平坦性を高め
ることが可能となる。これにより、絶縁膜上に形成する
配線の信頼性を向上できるとともに、配線の微細化が可
能となる。As described above, the present invention has the following effects. That is, since the protrusions are formed between the plurality of chip components, a step when an insulating film is applied thereon can be suppressed, and the flatness of the insulating film can be improved. Thereby, the reliability of the wiring formed on the insulating film can be improved, and the wiring can be miniaturized.
【図１】第１実施形態を説明する模式断面図である。FIG. 1 is a schematic cross-sectional view illustrating a first embodiment.
【図２】第１実施形態に係る半導体素子の製造方法を説
明する模式断面図（その１）である。FIG. 2 is a schematic cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment.
【図３】第１実施形態に係る半導体素子の製造方法を説
明する模式断面図（その２）である。FIG. 3 is a schematic cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment.
【図４】第２実施形態を説明する模式断面図である。FIG. 4 is a schematic sectional view illustrating a second embodiment.
【図５】第２実施形態に係る半導体素子の製造方法を説
明する模式断面図（その１）である。FIG. 5 is a schematic cross-sectional view (part 1) illustrating a method for manufacturing a semiconductor device according to a second embodiment.
【図６】第２実施形態に係る半導体素子の製造方法を説
明する模式断面図（その２）である。FIG. 6 is a schematic cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment.
１…半導体素子、２ａ…チップ部品、２ｂ…チップ部
品、３…絶縁膜、４…配線、１０…基板DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2a ... Chip parts, 2b ... Chip parts, 3 ... Insulating film, 4 ... Wiring, 10 ... Substrate
Claims (8)
と、 前記複数のチップ部品の間で、そのチップ部品の実装面
から突出する凸部と、 前記複数のチップ部品および前記凸部を覆う状態で形成
される絶縁膜とを備えることを特徴とする半導体素子。A plurality of chip components mounted on a substrate; a projection projecting from a mounting surface of the chip component between the plurality of chip components; and covering the plurality of chip components and the projection. And an insulating film formed in a state.
間の電気的接続を行う配線を備えていることを特徴とす
る請求項１記載の半導体素子。2. The semiconductor device according to claim 1, further comprising a wiring for electrically connecting said plurality of chip components on said insulating film.
れる土手から成ることを特徴とする請求項１記載の半導
体素子。3. The semiconductor device according to claim 1, wherein the projection is formed of a bank formed separately on the substrate.
る土手から成ることを特徴とする請求項１記載の半導体
素子。4. The semiconductor device according to claim 1, wherein the protrusion is formed of a bank formed integrally with the substrate.
記基板上に実装する工程と、 前記複数のチップ部品および前記凸部を覆う状態で絶縁
膜を形成する工程とを備えることを特徴とする半導体素
子の製造方法。5. A step of forming a protrusion on a substrate; a step of mounting a plurality of chip components on the substrate such that the protrusions on the substrate are interposed; a step of forming the protrusions on the substrate; Forming an insulating film in a state covering the semiconductor device.
間の電気的接続を行う配線を形成することを特徴とする
請求項５記載の半導体素子の製造方法。6. The method according to claim 5, wherein a wiring for electrically connecting the plurality of chip components is formed on the insulating film.
れる土手から成ることを特徴とする請求項５記載の半導
体素子の製造方法。7. The method according to claim 5, wherein the protrusion is formed of a bank formed separately on the substrate.
る土手から成ることを特徴とする請求項５記載の半導体
素子の製造方法。8. The method according to claim 5, wherein the protrusion is formed of a bank formed integrally with the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000248061A JP2002064177A (en) | 2000-08-18 | 2000-08-18 | Semiconductor element and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000248061A JP2002064177A (en) | 2000-08-18 | 2000-08-18 | Semiconductor element and its manufacturing method |
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| Publication Number | Publication Date |
|---|---|
| JP2002064177A true JP2002064177A (en) | 2002-02-28 |
Family
ID=18738042
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
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| Country | Link |
|---|---|
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008091763A (en) * | 2006-10-04 | 2008-04-17 | Mitsubishi Electric Corp | Semiconductor device, manufacturing method thereof, and manufacturing method of mounting substrate |
| JP2013038306A (en) * | 2011-08-10 | 2013-02-21 | Fujitsu Ltd | Electronic device and method for manufacturing the same |
| JP2014236095A (en) * | 2013-05-31 | 2014-12-15 | 富士通株式会社 | Electronic apparatus and manufacturing method of the same |
| WO2019230243A1 (en) * | 2018-05-28 | 2019-12-05 | ソニーセミコンダクタソリューションズ株式会社 | Imaging device |
-
2000
- 2000-08-18 JP JP2000248061A patent/JP2002064177A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008091763A (en) * | 2006-10-04 | 2008-04-17 | Mitsubishi Electric Corp | Semiconductor device, manufacturing method thereof, and manufacturing method of mounting substrate |
| JP2013038306A (en) * | 2011-08-10 | 2013-02-21 | Fujitsu Ltd | Electronic device and method for manufacturing the same |
| JP2014236095A (en) * | 2013-05-31 | 2014-12-15 | 富士通株式会社 | Electronic apparatus and manufacturing method of the same |
| WO2019230243A1 (en) * | 2018-05-28 | 2019-12-05 | ソニーセミコンダクタソリューションズ株式会社 | Imaging device |
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