JPH01258458A - Wafer integration type integrated circuit - Google Patents

Wafer integration type integrated circuit

Info

Publication number
JPH01258458A
JPH01258458A JP63086381A JP8638188A JPH01258458A JP H01258458 A JPH01258458 A JP H01258458A JP 63086381 A JP63086381 A JP 63086381A JP 8638188 A JP8638188 A JP 8638188A JP H01258458 A JPH01258458 A JP H01258458A
Authority
JP
Japan
Prior art keywords
semiconductor
master substrate
semiconductor chips
chips
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63086381A
Other languages
Japanese (ja)
Inventor
Takeo Yoshikawa
吉川　武夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63086381A priority Critical patent/JPH01258458A/en
Publication of JPH01258458A publication Critical patent/JPH01258458A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/24147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect not connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted, e.g. the upper semiconductor or solid-state body being mounted in a cavity or on a protrusion of the lower semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48149—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the wire connector connecting to a bonding area protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82909—Post-treatment of the connector or the bonding area
    • H01L2224/82951—Forming additional members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15156—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To improve semiconductor chips in their heat-radiating capability and to prevent the substrate potential from elevation by a method wherein the semiconductor chips are fixed tight by a conducting adhesive agent into recesses provided at specified locations on one main surface of a semiconductor master substrate. CONSTITUTION:An integrated circuit of this design includes a plurality of semiconductor chips 2 consisting of semiconductor substrates of one conductivity type mounted with circuits or elements and a semiconductor master substrate 1 of the same conductivity type mounted with said semiconductor chips 2. The semiconductor chips 2 are fixed tight by an conducting adhesive agent 3 into recesses 11 provided at prescribed locations on one main surface of the semiconductor master substrate 1. The semiconductor chips 2 and the semiconductor master substrate 1 are integrated into one piece, thermally and electrically. In this way, the chips 2 are improved in their heat-radiating efficiency, and the potential level of the semiconductor master substrate 1 is prevented from elevation.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置分野に利用される。[Detailed description of the invention] [Industrial application field] The present invention is utilized in the field of semiconductor devices.

本発明は半導体集積回路に関し、特に特定機能を有する
複数の半導体集積回路チップを、他の１つの半導体マス
タ基板上に集積して搭載するいわゆるウェーハインテグ
レーシ、　ン（Ｗａｆｅｒ　Ｉｎｔｅｇｒａ−ｔｉｏｎ
）　と呼ばれるウェーハ集積型集積回路に関する。The present invention relates to semiconductor integrated circuits, and in particular to so-called wafer integration, in which a plurality of semiconductor integrated circuit chips having specific functions are integrated and mounted on another semiconductor master substrate.
) concerning wafer-integrated integrated circuits.

〔概要〕〔overview〕

本発明は、複数個の半導体チップが一つの半導体マスタ
基板に搭載されたウェーハ集積型集積回路において、 前記半導体チップを、前記半導体マスタ基板の一主面に
設けられた凹状部に、導電性接着剤で固着された構造と
することにより、 半導体チップの放熱性を向上し、基板電位の上昇を押さ
え、かつブレーナ技術を用いて簡単に製造できるように
したものである。The present invention provides a wafer-integrated integrated circuit in which a plurality of semiconductor chips are mounted on one semiconductor master substrate, in which the semiconductor chips are attached to a concave portion provided on one main surface of the semiconductor master substrate using conductive adhesive. The structure is fixed with a chemical agent, which improves the heat dissipation of the semiconductor chip, suppresses the increase in substrate potential, and makes it easy to manufacture using brainer technology.

〔従来の技術〕[Conventional technology]

従来、この種のウェーハ集積型集積回路として、第３図
に示すものがある（例えば、米国、電気電子学会、固体
回路（ＩＥＥＥ　Ｊｏｕｒｎａｌ　ｏｆ　５ｏｌｉｄ−
３ｔａｔｅＣｉｒｃｕｉｔｓ）ｖｏｌ、５Ｃ−２１ｎｏ
、５１）り８４５〜８５１０ｃｔ、１９８６）。Conventionally, there is a wafer-integrated integrated circuit of this type, as shown in FIG.
3tate Circuits) vol, 5C-21no
, 51) Ri 845-8510ct, 1986).

これは、まず半導体マスタ基板１上の所定領域をエツチ
ングによって貫通孔１２を形成し、その後半導体チップ
２を前記貫通孔に搭載する。このとき接着剤１３によっ
て半導体チップ２を半導体マスタ基板１に固着する。次
に、酸化膜７による通常のプレーナ技術によって、半導
体チップ２間の接続としてチップ接続用パッド５と配線
層６を形成する。そして酸化膜９を保護膜として被覆す
る。First, a through hole 12 is formed by etching a predetermined area on the semiconductor master substrate 1, and then the semiconductor chip 2 is mounted in the through hole. At this time, the semiconductor chip 2 is fixed to the semiconductor master substrate 1 using the adhesive 13. Next, a chip connection pad 5 and a wiring layer 6 are formed as connections between the semiconductor chips 2 by using a normal planar technique using an oxide film 7. Then, an oxide film 9 is applied as a protective film.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

前述した従来のウェーハ集積型集積回路には、■　半導
体チップ１２が接着剤１３を経由して半導体マスタ基板
１１と固着されているため、半導体チップ１２の熱放散
性が悪い、 ■　半導体チップ１２の基板電位と半導体マスタ基板１
の基板電位とを等しくする場合、配線層６を経由するた
め基板電位が上昇しやすい、■　半導体チップ２と半導
体マスタ基板１とを整合性をとって固着できにくく、そ
のためそれぞれの接続界面で半導体チップ２間に凹凸が
生じるため、後々の配線層形成工程でプレーナ技術が適
用し難い、 などの欠点があった。The conventional wafer-integrated integrated circuit described above has the following problems: (1) the semiconductor chip 12 is fixed to the semiconductor master substrate 11 via the adhesive 13, so the heat dissipation of the semiconductor chip 12 is poor; Substrate potential and semiconductor master substrate 1
When making the substrate potential equal to the substrate potential of There were drawbacks such as the difficulty of applying planar technology in the later wiring layer formation process because of the unevenness between the two chips.

本発明の目的は、前記の欠点を除去することにより、半
導体チップの放熱性がよく、基板電位の上昇を押さえ、
かつプレーナ技術を用いて簡単に製造できるウェーハ集
積型集積回路を提供することにある。The purpose of the present invention is to eliminate the above-mentioned drawbacks, thereby improving the heat dissipation of the semiconductor chip, suppressing the rise in substrate potential, and
Another object of the present invention is to provide a wafer-integrated integrated circuit that can be easily manufactured using planar technology.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、一導電型の半導体基板に回路または素子が形
成された複数個の半導体チップと、この半導体チップが
それぞれの所定位置に搭載された一導電型の半導体マス
タ基板とを含むウェーハ集積型集積回路において、前記
半導体チップは、前記半導体マスタ基板の一主面の所定
の位置に設けられた凹状部に導電性接着剤により固着さ
れたことを特徴とする。The present invention relates to a wafer integrated type that includes a plurality of semiconductor chips in which circuits or elements are formed on semiconductor substrates of one conductivity type, and a semiconductor master substrate of one conductivity type on which the semiconductor chips are mounted at respective predetermined positions. In the integrated circuit, the semiconductor chip is fixed to a concave portion provided at a predetermined position on one principal surface of the semiconductor master substrate using a conductive adhesive.

〔作用〕[Effect]

半導体チップは、半導体マスタ基板の一主面の所定領域
に、例えば異方性エツチングによりあらかじめ設けられ
た凹状部に、例えばＡｇペーストなどの導電性接着剤で
固着される。The semiconductor chip is fixed to a predetermined region of one main surface of the semiconductor master substrate in a recessed portion previously provided by, for example, anisotropic etching, using a conductive adhesive such as, for example, Ag paste.

従って、半導体チップと半導体マスタ基板とは熱的およ
び電気的に一体となり、半導体チップの放熱性の向上を
図り、基板電位の上昇を押さえることが可能となる。さ
らに、凹状部は均一な形状に形成でき、プレーナ技術を
用いて全体を簡単に製造することが可能となる。Therefore, the semiconductor chip and the semiconductor master substrate are thermally and electrically integrated, and it is possible to improve the heat dissipation of the semiconductor chip and suppress the increase in substrate potential. Furthermore, the concave portion can be formed into a uniform shape, and the whole can be easily manufactured using planar technology.

〔実施例〕〔Example〕

以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.

第１図は本発明の第一実施例を示す縦断面図である。FIG. 1 is a longitudinal sectional view showing a first embodiment of the present invention.

本第−実施例は、一導電型の半導体基板に回路または素
子が形成された複数個の半導体チップ２と、この半導体
チップ２をそれぞれの所定位置に搭載した一導電型の半
導体マスタ基板１とを含むウェーハ集積型集積回路にお
いて、 半導体チップ２は、半導体マスタ基板１の一主面の所定
の位置に設けられた凹状部１１に導電性接着剤としての
Ａｇペースト３により固着された構造を有する。The present embodiment includes a plurality of semiconductor chips 2 in which circuits or elements are formed on semiconductor substrates of one conductivity type, and a semiconductor master substrate 1 of one conductivity type on which the semiconductor chips 2 are mounted at respective predetermined positions. In a wafer-integrated integrated circuit including: The semiconductor chip 2 has a structure in which the semiconductor chip 2 is fixed to a concave portion 11 provided at a predetermined position on one principal surface of the semiconductor master substrate 1 with an Ag paste 3 as a conductive adhesive. .

次に、本第−実施例の製造方法について説明する。Next, the manufacturing method of this embodiment will be explained.

厚さ数ｍｍの半導体マスタ基板１の特定領域を、異方性
エツチングで除去して凹状部１１を形成する。A specific region of a semiconductor master substrate 1 having a thickness of several mm is removed by anisotropic etching to form a concave portion 11 .

この凹状部１１の深さは搭載半導体チップ２の厚さ、例
えば５００μｍ程度で、凹状部の底部の大きさは半導体
チップ面積に等しくなるよう、レジストをマスタとして
ＫＯＨ等による異方性エツチングを行う。適当なエツチ
ングを行うことにより、半導体チップ２の搭載時の位置
決めが正確にできる。半導体マスタ基板１の導電型は、
搭載する半導体チップの導電型に一致させることが必要
であり、また低抵抗率であることが望ましい。The depth of this recessed portion 11 is the thickness of the mounted semiconductor chip 2, for example, about 500 μm, and anisotropic etching is performed using KOH or the like using a resist as a master so that the bottom size of the recessed portion is equal to the area of the semiconductor chip. . By performing appropriate etching, the semiconductor chip 2 can be accurately positioned during mounting. The conductivity type of the semiconductor master substrate 1 is
It is necessary to match the conductivity type of the semiconductor chip to be mounted, and it is desirable that the resistivity be low.

搭載する半導体チップ２は、すでに通常のプレーナ技術
等によって回路が形成されている。この半導体チップ２
を、導電性接着剤として、例えばＡｇペースト３を用い
て半導体マスタ基板１に固着させる。次に、例えばポリ
イミド樹脂４等の絶縁性充填剤で、異方性エツチングに
よって形成された凹状部と半導体チップ２間の空隙を埋
める。そして、チップ接続用パッド５を例えばＡＩから
なる配線層６で接続し、それぞれの半導体チップ２を相
互に接続する。A circuit has already been formed on the semiconductor chip 2 to be mounted using a normal planar technology or the like. This semiconductor chip 2
is fixed to the semiconductor master substrate 1 using, for example, Ag paste 3 as a conductive adhesive. Next, the gap between the semiconductor chip 2 and the concave portion formed by the anisotropic etching is filled with an insulating filler such as polyimide resin 4, for example. Then, the chip connection pads 5 are connected with a wiring layer 6 made of, for example, AI, and the respective semiconductor chips 2 are connected to each other.

次に、配線層６上の所定の位置に、ケース接続用パッド
８となる部分を残して、全面に保護膜として酸化膜９を
形成する。Next, at a predetermined position on the wiring layer 6, an oxide film 9 is formed as a protective film over the entire surface, leaving a portion that will become the case connection pad 8.

以上のように、通常のプレーナ技術等で製作された小規
模な機能を有する半導体チップ２を、あらかじめ他の半
導体基板マスタ基板１上に、矩形で凹状に作られた凹状
部１１に搭載し、その後再びプレーナ技術等によって配
線を施して半導体チップ２それぞれを相互に結線すれば
、機能の複合化した新しいウェーハ集積型集積回路を実
現することができる。As described above, the semiconductor chip 2 having a small-scale function manufactured by ordinary planar technology etc. is mounted in advance on another semiconductor substrate master substrate 1 in the concave portion 11 made in a rectangular concave shape, Thereafter, by interconnecting the semiconductor chips 2 by wiring again using planar technology or the like, it is possible to realize a new wafer-integrated integrated circuit with multiple functions.

なお、第１図は、行あるいは列の単方向のみの構造を示
す縦断面図であるが、行列状に半導体チップ２を同様に
搭載できる。Although FIG. 1 is a vertical cross-sectional view showing the structure in only one direction of rows or columns, the semiconductor chips 2 can be similarly mounted in a matrix.

第２図は本発明の第二実施例を示す縦断面図である。本
第二実施例は、半導体チップ２相互の結線を、半導体マ
スタ基板１上の表面に形成された配線層６を介してボン
ディング線１０で接続した構造としたものである。本第
二実施例では、半導体チップ相互の接続をボンディング
線１０で行うため、配線層６で接続する第一実施例に比
し、簡単に製造できる利点がある。FIG. 2 is a longitudinal sectional view showing a second embodiment of the present invention. The second embodiment has a structure in which semiconductor chips 2 are connected to each other by bonding wires 10 via a wiring layer 6 formed on the surface of a semiconductor master substrate 1. In the second embodiment, since the semiconductor chips are connected to each other by the bonding wires 10, there is an advantage that the semiconductor chips can be easily manufactured compared to the first embodiment in which the semiconductor chips are connected by the wiring layer 6.

本発明の特徴は、第１図および第２図において、半導体
チップ２が、半導体マスタ基板１の凹状部１１にＡｇペ
ースト（導電性接着剤）３で固着された構造を有するこ
とにある。A feature of the present invention is that, as shown in FIGS. 1 and 2, the semiconductor chip 2 has a structure in which the semiconductor chip 2 is fixed to the concave portion 11 of the semiconductor master substrate 1 with Ag paste (conductive adhesive) 3.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、半導体マスタ基板上の
貫通までは至らない凹状部を異方性エツチングで形成す
ることにより、半導体チップを精度よく搭載でき、その
結果半導体チップ間接続のためのプレーナ技術が適用し
やすい効果がある。As explained above, the present invention enables semiconductor chips to be mounted with high precision by forming concave portions that do not penetrate through the semiconductor master substrate by anisotropic etching, thereby making it possible to mount semiconductor chips with high accuracy. Planar technology has the effect of being easy to apply.

さらに、半導体チップと半導体マスタ基板は、凹状部底
面の導電性ペーストで接続されるため、半導体チップの
熱放散性が向上し、半導体チップと半導体マスタ基板を
共通電位（共通グランド）でとりやすく基板電位を上昇
を押さえる効果がある。Furthermore, since the semiconductor chip and the semiconductor master board are connected with the conductive paste on the bottom of the recessed part, the heat dissipation of the semiconductor chip is improved, and it is easy to connect the semiconductor chip and the semiconductor master board to a common potential (common ground). It has the effect of suppressing the increase in potential.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の第一実施例を示す縦断面図。 第２図は本発明の第二実施例を示す縦断面図。 第３図は従来例を示す縦断面図。 １・・・半導体マスタ基板、２・・・半導体チップ、３
・・・Ａｇペースト、４・・・ポリイミド樹脂、５・・
・チップ接続用パッド、６・・・配線層、７．９・・・
酸化膜、８・・・ケース接続用パッド、１０・・・ボン
ディング線、１１・・・凹状部、１２・・・貫通孔、１
３・・・接着剤。 特許出願人　日本電気株式会社、− 代理人　　弁理士　井　出　直　孝FIG. 1 is a longitudinal sectional view showing a first embodiment of the present invention. FIG. 2 is a longitudinal sectional view showing a second embodiment of the present invention. FIG. 3 is a longitudinal sectional view showing a conventional example. 1... Semiconductor master board, 2... Semiconductor chip, 3
...Ag paste, 4...Polyimide resin, 5...
・Chip connection pad, 6... wiring layer, 7.9...
Oxide film, 8... Case connection pad, 10... Bonding wire, 11... Concave portion, 12... Through hole, 1
3...Adhesive. Patent applicant: NEC Corporation, − Agent: Naotaka Ide, patent attorney

Claims (1)

【特許請求の範囲】 １、一導電型の半導体基板に回路または素子が形成され
た複数個の半導体チップ（２）と、この半導体チップが
それぞれの所定位置に搭載された一導電型の半導体マス
タ基板（１）とを含むウェーハ集積型集積回路において
、 前記半導体チップは、前記半導体マスタ基板の一主面の
所定の位置に設けられた凹状部（１１）に導電性接着剤
（３）により固着された ことを特徴とするウェーハ集積型集積回路。[Claims] 1. A plurality of semiconductor chips (2) in which circuits or elements are formed on a semiconductor substrate of one conductivity type, and a semiconductor master of one conductivity type in which these semiconductor chips are mounted at respective predetermined positions. In a wafer-integrated integrated circuit including a substrate (1), the semiconductor chip is fixed to a recess (11) provided at a predetermined position on one main surface of the semiconductor master substrate with a conductive adhesive (3). A wafer-integrated integrated circuit characterized by:
JP63086381A 1988-04-08 1988-04-08 Wafer integration type integrated circuit Pending JPH01258458A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63086381A JPH01258458A (en) 1988-04-08 1988-04-08 Wafer integration type integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63086381A JPH01258458A (en) 1988-04-08 1988-04-08 Wafer integration type integrated circuit

Publications (1)

Publication Number Publication Date
JPH01258458A true JPH01258458A (en) 1989-10-16

Family

ID=13885296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63086381A Pending JPH01258458A (en) 1988-04-08 1988-04-08 Wafer integration type integrated circuit

Country Status (1)

Country Link
JP (1) JPH01258458A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002532876A (en) * 1998-12-07 2002-10-02 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング Method for enclosing electronic components in a casing
JP2006054493A (en) * 2000-10-20 2006-02-23 Silverbrook Research Pty Ltd Multi-chip integrated circuit carrier
JP2006080556A (en) * 2000-10-20 2006-03-23 Silverbrook Research Pty Ltd Integrated circuit carrier
JP2006080555A (en) * 2000-10-20 2006-03-23 Silverbrook Research Pty Ltd Method of manufacturing integrated circuit carrier
JP2006245226A (en) * 2005-03-02 2006-09-14 Oki Electric Ind Co Ltd Semiconductor device and manufacturing method therefor
JP2012028692A (en) * 2010-07-27 2012-02-09 Sumitomo Electric Ind Ltd Semiconductor device and method of manufacturing the same
JP2013522917A (en) * 2010-04-06 2013-06-13 インテル コーポレイション Method for forming metal filled die backside film for electromagnetic interference shield with coreless package
JP2013524491A (en) * 2010-04-16 2013-06-17 インテル・コーポレーション Formation of functionalized carrier structure using coreless package

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002532876A (en) * 1998-12-07 2002-10-02 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング Method for enclosing electronic components in a casing
JP4528246B2 (en) * 2000-10-20 2010-08-18 シルバーブルック リサーチ ピーティワイ リミテッド Multi-chip integrated circuit package
JP2006080556A (en) * 2000-10-20 2006-03-23 Silverbrook Research Pty Ltd Integrated circuit carrier
JP2006080555A (en) * 2000-10-20 2006-03-23 Silverbrook Research Pty Ltd Method of manufacturing integrated circuit carrier
JP4528245B2 (en) * 2000-10-20 2010-08-18 シルバーブルック リサーチ ピーティワイ リミテッド Integrated circuit package
JP2006054493A (en) * 2000-10-20 2006-02-23 Silverbrook Research Pty Ltd Multi-chip integrated circuit carrier
JP4658772B2 (en) * 2000-10-20 2011-03-23 シルバーブルック リサーチ ピーティワイ リミテッド Method of manufacturing an integrated circuit package
JP2006245226A (en) * 2005-03-02 2006-09-14 Oki Electric Ind Co Ltd Semiconductor device and manufacturing method therefor
JP4659488B2 (en) * 2005-03-02 2011-03-30 Ｏｋｉセミコンダクタ株式会社 Semiconductor device and manufacturing method thereof
JP2013522917A (en) * 2010-04-06 2013-06-13 インテル コーポレイション Method for forming metal filled die backside film for electromagnetic interference shield with coreless package
JP2013524491A (en) * 2010-04-16 2013-06-17 インテル・コーポレーション Formation of functionalized carrier structure using coreless package
US8987065B2 (en) 2010-04-16 2015-03-24 Intel Corporation Forming functionalized carrier structures with coreless packages
US9257380B2 (en) 2010-04-16 2016-02-09 Intel Corporation Forming functionalized carrier structures with coreless packages
JP2012028692A (en) * 2010-07-27 2012-02-09 Sumitomo Electric Ind Ltd Semiconductor device and method of manufacturing the same

Similar Documents

Publication Publication Date Title
US3903590A (en) Multiple chip integrated circuits and method of manufacturing the same
US8357999B2 (en) Assembly having stacked die mounted on substrate
US7847415B2 (en) Method for manufacturing a multichip module assembly
US6028358A (en) Package for a semiconductor device and a semiconductor device
US6816385B1 (en) Compliant laminate connector
CN100433313C (en) Method and device for heat dissipation in semiconductor modules
JPH0754845B2 (en) Stepped electronic device package
JPH01132151A (en) Module for interconnection of integrated circuits
JPS61502294A (en) High density IC module assembly
JPS5839048A (en) Flexible region adhesive tape
KR100255476B1 (en) Ball grid array package
JPH06244360A (en) Semiconductor device
JP3927783B2 (en) Semiconductor parts
CN111554613A (en) Chip packaging method
JPH01258458A (en) Wafer integration type integrated circuit
CN111554617A (en) Chip packaging method
JP3018789B2 (en) Semiconductor device
JP2021530098A (en) Semiconductor chip stacking arrangements, and semiconductor chips for manufacturing such semiconductor chip stacking arrangements
JPS6220707B2 (en)
JP2004087700A (en) Semiconductor device and its manufacturing method
US6965162B2 (en) Semiconductor chip mounting substrate and semiconductor device using it
KR20040055590A (en) Circuit device and method of manufacturing the same
Kanbach et al. 3D Si‐on‐Si stack packaging
JP4168494B2 (en) Manufacturing method of semiconductor device
JPH0744243B2 (en) Semiconductor integrated circuit module