JP2004247464A - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

Info

Publication number
JP2004247464A
JP2004247464A JP2003034962A JP2003034962A JP2004247464A JP 2004247464 A JP2004247464 A JP 2004247464A JP 2003034962 A JP2003034962 A JP 2003034962A JP 2003034962 A JP2003034962 A JP 2003034962A JP 2004247464 A JP2004247464 A JP 2004247464A
Authority
JP
Japan
Prior art keywords
semiconductor element
wiring board
semiconductor device
semiconductor
slit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003034962A
Other languages
Japanese (ja)
Inventor
Koji Yamaguchi
浩司 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2003034962A priority Critical patent/JP2004247464A/en
Publication of JP2004247464A publication Critical patent/JP2004247464A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15162—Top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that can relieve the stress between a semiconductor element and a wiring board due to the difference of the coefficient of thermal expansions, and to provide a manufacturing method of the device. <P>SOLUTION: The semiconductor device is provided with a semiconductor element 1 having a plurality of pad electrodes at the peripheral edge of an element forming face, a relay substrate 5 which has a prescribed copper wiring layer and supports an element forming face-side of the semiconductor element 1, and a bump 11 whose one end is bonded to the pad electrodes of the semiconductor element 1 and whose other end is bonded to the copper wiring layer on the relay substrate 5 facing the semiconductor element 1. The relay substrate 5 is provided with L-shaped slits 7A and 7B which sandwich corners of the semiconductor element from an inner side and an outer side by a plane view and follow the corners. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置及びその製造方法に係り、特に、ＢＧＡ等のエリアレイパッケージを有するＬＳＩに適用して好適な半導体装置及びその製造方法に関するものである。
【０００２】
【従来の技術】
近年、パーソナルコンピュータ等の電子機器に搭載される半導体装置はますます高集積化しつつある。これに伴って、半導体装置の多ピン化、狭ピッチ化も進みつつあり、ＢＧＡ（ｂａｌｌ ｇｒｉｄ ａｒｒａｙ）等のエリアアレイパッケージが普及しつつある。
【０００３】
図１１は従来例に係る半導体装置９０の構成例を示す断面図である。この半導体装置９０は、ＢＧＡ型のＬＳＩである。この半導体装置９０では、シリコンチップからなる半導体素子（図示せず）の素子形成面側が中継基板９２に実装され、表面実装された半導体素子が樹脂パッケージ９３によって封止されている。
図１１に示す中継基板９２は、ガラス布にエポキシ樹脂を含浸させたガラスエポキシプリプレグと、パターニングされた銅配線層とが多層に積み重ねられて形成されたものである。中継基板９２の最上面とした最下面は銅配線層である。また、最上面から最下面までの各銅配線層は、内壁面がめっき処理されたスルーホールによって、必要に応じて接続されている。図１１に示すように、この中継基板９２は板状であり、その表面は平らである。
【０００４】
この中継基板９２の最上面にある銅配線層と、中継基板９２に表面実装された半導体素子間の電気的接続は、バンプによって行なわれる（例えば、特許文献１参照。）。このバンプは、はんだからなるものである。
また、図１１に示すように、この中継基板９２の下面は、ガラスエポキシプリプレグからなるプリント配線基板９４に実装されている。このプリント配線基板９４の上面には、複数の配線パターン（図示せず）が設けられており、プリント配線基板９４上面の配線パターンと、中継基板９２の最下面にある銅配線層とがボール電極によって電気的に接続されている（例えば、特許文献１参照。）。
【０００５】
【特許文献１】
特開平１１−１３５６７５号公報
【特許文献２】
特開２０００−１００８６６号公報
【特許文献３】
特開平１０−１８９８１５号公報
【特許文献４】
特開平１０−１５０１１７号公報
【特許文献５】
特開平６−３４２９６６号公報
【０００６】
【発明が解決しようとする課題】
ところで、従来例に係る半導体装置９０によれば、半導体素子はシリコンチップからなり、中継基板９２はガラスエポキシプリプレグからなるので、半導体素子９１と中継基板９２との間で熱膨張係数の整合性がとれていない。
このため、ボール電極をプリント配線基板９４上面の配線パターンに接合するはんだリフロー等の加熱工程では、半導体素子９１と中継基板９２はそれぞれ異なる膨張率で膨張してしまい、半導体素子９１と中継基板９２を電気的に接続するバンプに過大な応力が負荷されてしまうといった問題があった。バンプにかかる応力が大きいと、バンプ自体が壊れるおそれがあり、半導体素子９１と中継基板９２との電気的接続の信頼性が低下してしまうという問題があった。
【０００７】
そこで、本発明は、このような従来技術の問題点を解決したものであって、熱膨張係数差によって半導体素子と配線基板との間に生じてしまう応力を緩和できるようにした半導体装置及びその製造方法の提供を目的とする。
【０００８】
【課題を解決するための手段】
上記した課題を解決するために、本発明に係る第１の半導体装置は、複数の端子部を素子形成面の周縁部に有する半導体素子と、所定の配線パターンを有し、半導体素子の素子形成面側を支持する配線基板と、一端を半導体素子の端子部に接合され、他端を当該半導体素子と向かい合う配線基板の配線パターンに接合された導電部材とを備え、配線基板は、半導体素子の角部を平面視で内側外側から挟み込み、且つその角部に沿ったＬ字状の溝部またはスリット部を少なくとも一対備えていることを特徴とするものである。
【０００９】
本発明に係る第２の半導体装置は、上述した第１の半導体装置において、導電部材は、この溝部またはスリット部によって内側と外側から挟み込まれていることを特徴とするものである。
本発明に係る第３の半導体装置は、上述した第１、第２の半導体装置において、この溝部またはスリット部は、半導体素子の角部に対してＲ状であることを特徴とするものである。
【００１０】
本発明に係る第４の半導体装置は、上述した第１〜第３の半導体装置において、この配線基板を第１の配線基板とすると共に、この導電部材を第１の導電部材とし、さらにこの溝部またはスリット部を第１の溝部またはスリット部としたとき、所定の配線パターンを有し、第１の配線基板の半導体素子が取り付けられた面の反対側を支持する第２の配線基板と、一端を第１の配線基板の配線パターンに接合され、他端を当該第１の配線基板と向かい合う第２の配線基板の配線パターンに接合された第２の導電部材とを備え、第２の配線基板は、平面視で第１の配線基板の角部に沿ったＬ字状の第２の溝部またはスリット部を備えたことを特徴とするものである。
【００１１】
ここで、半導体素子はシリコンからなり、配線基板はガラスエポキシプリプレグやセラミック等のシリコン以外の材料からなることが普通である。このため、半導体素子と配線基板とでは熱膨張係数が異なり、はんだリフロー等の加熱工程では、半導体素子と配線基板は異なる膨張率で膨張してしまう。また、半導体素子は、シリコンウェハが矩形にダイシングされて形成されることが通常である。このため、半導体素子の中で最も寸法長の大きい対角線上の一端、即ち半導体素子の角部周辺で、半導体素子と配線基板との間に特に大きな応力が生じる。
【００１２】
本発明に係る第１〜第４の半導体装置によれば、半導体素子の素子形成面側を支持する配線基板には、この半導体素子の角部を平面視で内側外側から挟み込み、且つその角部に沿ったＬ字状の溝部またはスリット部が少なくとも一対設けられている。従って、特に、半導体素子の角部にかかる応力を緩和することができ、半導体素子と配線基板との電気的接続の信頼性を向上させることができる。
【００１３】
本発明に係る半導体装置の製造方法は、複数の端子部を素子形成面の周縁部に有する半導体素子の該素子形成面側を所定の配線パターンを有する配線基板に取り付ける工程と、この半導体素子の端子部に導電部材の一端を接合すると共に、他端を当該半導体素子と向かい合う配線基板の配線パターンに接合する工程と、半導体素子の角部を平面視で内側外側から挟み込み、且つその角部に沿うようなＬ字状の溝部またはスリット部を配線基板に少なくとも一対形成する工程、とを有することを特徴とするものである。
【００１４】
本発明に係る半導体装置の製造方法によれば、半導体素子の角部の内側と外側で、この半導体素子にかかる応力を緩和することができ、半導体素子と配線基板間の電気的接続の信頼性を向上させることができる。
【００１５】
【発明の実施の形態】
以下、図面を参照しながら本発明の実施の形態について説明する。
図１は本発明の実施の形態に係る半導体装置１００の構成例を示す概念図である。この半導体装置１００は、ＢＧＡ型のパッケージを有するＬＳＩである。この半導体装置１００は、素子形成面の周縁部に複数のバッド電極を有する半導体素子と、この半導体素子を封止する樹脂パッケージ３と、銅配線層を有して半導体素子の素子形成面側を支持する中継基板（インターポーザ）５と、一端を半導体素子の端子部であるパッド電極に接合され、他端を中継基板５の最上面にあってパッド電極と向かい合う銅配線層に接合されたバンプとを備えている。また、この半導体装置１００は、プリント配線基板９と、一端を中継基板５の最下面にある銅配線層に接合され、他端をこの中継基板５と向かい合うプリント配線基板９上面の配線パターンに接合されたボール電極とを備えている。
【００１６】
図２は半導体素子１におけるバンプ１１の配置例を示す概念図である。図２における実線外枠は、樹脂パッケージ３の輪郭を示す。また、図２における破線内枠は、樹脂パッケージによって封止された半導体素子１の輪郭を示す。
半導体素子１は、例えばシリコンウェハの素子形成面側に多数の集積回路素子を形成した後に、このシリコンウェハを集積回路素子毎に１個１個矩形にダイシングして形成されたものである。この半導体素子１の大きさは、例えば縦×横×厚さ＝８ｍｍ×８ｍｍ×１００μｍ程度である。樹脂パッケージ３の大きさは、例えば縦×横×厚さ＝１０ｍｍ×１０ｍｍ×１ｍｍ程度である。
【００１７】
また、この半導体素子１の素子形成面の周縁部には、複数のパッド電極が設けられている。パッド電極とは、集積回路を保護する保護膜から、この集積回路素子を構成するＭＯＳトランジスタのソース・ドレインや、ゲート電極等をそれぞれ引き出す端子部である。これらのパッド電極も含めて半導体素子１は樹脂パッケージ３に覆われている。
【００１８】
バンプ１１は、図２に示すように、この半導体素子１の素子形成面側の周縁部に多数設けられている。これらのバンプ１１は、その一端が上述したパッド電極に接続し、その他端が樹脂パッケージ３から僅かに露出している。バンプ１１の横列の寸法幅をＷＢＵＭＰとしたとき、ＷＢＵＭＰ＝１ｍｍ程度である。
図３は中継基板５の構成例を示す平面図である。この中継基板５は、ガラス布にエポキシ樹脂を含浸させたガラスエポキシプリプレグと、パターニングされた銅配線層とが多層に積み重ねられて形成されたものである。例えば、この中継基板５は、Ｌｉｎｅ／Ｓｐａｃｅが１２５μｍ／１２５μｍ程度の銅配線層とガラスエポキシプリプレグとを交互に４〜６層程度積み重ねて形成したものである。
【００１９】
図示しないが、中継基板５の最上面と最下面には銅配線層が設けられている。また、最上面から最下面までの各銅配線層は、内壁面がめっき処理されたスルーホールによって、必要に応じて接続されている。この中継基板の略中央部に半導体素子が表面実装される。以下で、この半導体素子が表面実装される位置を半導体素子取付け位置３１ともいう。
【００２０】
図３に示すように、中継基板５には、半導体素子の角部を平面視で内側外側から挟み込み、且つその角部に沿ったＬ字状のスリット部（貫通溝部）７Ａ及び７Ｂが４対設けられている。スリット部７Ａ及び７Ｂの両方ともその輪郭は、中継基板５の縁部と平行であり、スリット部７Ａ及び７Ｂの角部分は中継基板５の対角線上に位置している。また、スリット部７Ｂは、スリット部７Ａの内側に設けられている。
【００２１】
中継基板５の大きさは、例えば縦×横×厚さ＝２０ｍｍ×２０ｍｍ×１ｍｍ程度である。また、スリット部７Ａ及び７Ｂは、半導体素子を支持するために必要な強度を損なわず、かつ中継基板５にある銅配線のとり回しが妨げられない程度の大きさに形成されている。例えば、スリット部７Ａの辺部分の長さと幅をそれぞれＬＡ、ＷＡとしたとき、ＬＡ＝５ｍｍ、ＷＡ＝１ｍｍである。スリット部７Ｂの辺部分の長さと幅をそれぞれＬＢ、ＷＢとしたとき、ＬＢ＝２ｍｍ、ＷＢ＝０．４ｍｍである。さらに、図５に示すように、スリット部７Ａ及び７Ｂの辺部分間の離隔距離をＬＡＢとしたとき、ＬＡＢ＝３ｍｍ程度である。図４に示すように、スリット部７Ａは樹脂パッケージ３から露出し、スリット部７Ｂは樹脂パッケージによって覆われる。
【００２２】
プリント配線基板９は、ガラス布にエポキシ樹脂を含浸させたガラスエポキシプリプレグを基体とし、この基体上に配線パターン（図示せず）を備えたものである。また、図４に示すように、プリント配線基板９には、中継基板５の角部に沿ってＬ字状のスリット部１７が設けられている。スリット部１７の輪郭は、中継基板５の縁部に平行である。このスリット部は、半導体素子と中継基板５を支持するために必要な強度を損なわず、かつ配線パターンのとり回しの妨げにならない程度の大きさに形成されている。例えば、スリット部１７の辺部分の長さと幅をそれぞれＬ、Ｗとしたとき、Ｌ＝１０ｍｍ、Ｗ＝２ｍｍである。また、スリット部１７と中継基板５間の離隔距離をＬ´としたとき、Ｌ´＝４ｍｍ程度である。
【００２３】
ところで、本発明に係る半導体装置１００によれば、図５に示すように、半導体素子１と中継基板５とを電気的に接続するバンプ１１は、中継基板５に設けられたスリット部７Ａ及び７Ｂによって、内側と外側から挟み込まれている。
この構造によって、はんだリフロー等の加熱工程において、半導体素子１と中継基板５とが異なる膨張率で膨張し、バンプ１１を内側または外側へ押し出すような応力が生じた場合でも、この応力はスリット部７Ａ及び７Ｂによってある程度吸収される。従って、バンプ１１にかかる応力を緩和することができるので、半導体素子１と中継基板５間の電気的接続の信頼性を向上させることができる。
【００２４】
また、中継基板５がセラミックからなり、プリント配線基板９がガラスエポキシプリプレグからなる場合には、両部材の熱膨張係数が異なるので、上記の加熱工程において、特に中継基板５とプリント配線基板９との間に応力が生じてしまう。この場合には、この応力はスリット部１７（図４参照）によってある程度吸収される。従って、ボール電極１３にかかる応力を緩和することができ、中継基板５とプリント配線基板９間の電気的接続の信頼性を向上させることができる。
【００２５】
この実施形態では、中継基板５は本発明の第１の配線基板に対応し、プリント配線基板９は本発明の第２の配線基板に対応している。また、バンプ１１は本発明の第１の導電部材に対応し、ボール電極１３は本発明の第２の導電部材に対応している。さらに、スリット部７Ａ及び７Ｂは本発明の第１のスリット部に対応し、スリット部１７は本発明の第２のスリット部に対応している。
【００２６】
なお、この実施形態では、本発明の第１、第２の配線基板に有機系のガラスエポキシプリプレグを使用する場合について説明したが、これに限られることはない。本発明の第１、第２の配線基板はその一方、またはその両方が、例えば無機系のセラミック配線板でもよい。これらの場合でも、半導体素子１と中継基板５との熱膨張係数の差によって、バンプ１１にかかる応力をスリット部７Ａ及び７Ｂで緩和することができる。
【００２７】
また、この実施形態では、スリット部７Ａ及び７Ｂが平面視でＬ字状であり、その角部が中継基板５の対角線上にある場合について説明したが、スリット部７Ａ及び７Ｂの角部は、図６に示すように、半導体素子取付位置３１の角部に対してＲ状に湾曲していても良い。また、スリット部１７の角部も、図７に示すように、Ｒ状に湾曲させても良い。これらの場合には、スリット部７Ａ及び７Ｂや、スリット部１７の角部（特異点）がなくなるので、中継基板５やプリント配線基板９の割れの可能性を低減することができる。
【００２８】
次に、本発明の実施形態に係る半導体装置１００の製造方法について説明する。
図８（Ａ）〜（Ｃ）と、図９は半導体装置１００の製造方法（その１、２）を示す工程図である。ここでは、図１に示した半導体装置１００を図８（Ａ）〜（Ｃ）と、図９の工程図に沿って説明する。従って、図８（Ａ）〜（Ｃ）と、図９において、図１と対応する部分には、同一符号を付す。
【００２９】
まず始めに、図８（Ａ）に示すように、ガラス布にエポキシ樹脂を含浸させたガラスエポキシプリプレグと、パターニングされた銅配線層とが多層に積み重ねられて形成された中継基板５´を用意する。この中継基板５´の製造は、周知のビルドアップ配線板技術を応用して行なう。
次に、図８（Ｂ）に示すように、スリット部７Ａ及び７Ｂとなる領域を開口し、その他の領域を覆うような感光性樹脂パターン１９を中継基板５´上に形成する。この感光性樹脂パターン１９の形成は、フォトリソグラフィ技術を用いて行なう。
【００３０】
そして、この感光性樹脂パターン１９をマスクにして、中継基板５にプラズマエッチングを施す。これにより、図８（Ｃ）に示すように、中継基板５を貫通するスリット部１７Ａ及び１７Ｂを形成する。
同様に、プリント配線基板上にもスリット部１７（図４参照）となる領域を開口するような感光性樹脂パターン（図示せず）を形成する。そして、この感光性樹脂パターンをマスクにしてプリント配線基板にプラズマエッチングを施して、プリント配線基板を貫通するスリット部１７を形成する。
【００３１】
その後、図９に示すように、半導体素子１の素子形成面側を中継基板５上に取り付けて、半導体素子１と中継基板５上とをバンプで接続する。このとき、スリット部７Ａ及び７Ｂを目印にして半導体素子の取付け位置を確認すると良い。これにより、半導体素子１の中継基板５への取付けミスを低減することができる。次に、中継基板５に取り付けられた半導体素子１を樹脂パッケージで封止する。
【００３２】
さらに、半導体素子１が取り付けられた中継基板５をプリント配線基板９上に取り付けて、中継基板５とプリント配線基板９をボール電極で接続する。このとき、スリット部１７を目印にして中継基板の取付け位置を確認すると良い。これにより、中継基板５のプリント配線基板９への取付けミスを低減することができる。このようにして、図１に示した半導体装置１００を完成させる。
【００３３】
本発明に係る半導体装置１００の製造方法によれば、図５に示したように、半導体素子１の角部に対応する領域であって、バンプ１１を内側と外側から挟み込むように中継基板５にスリット部７Ａ及び７Ｂを形成している。従って、バンプ１１の内側と外側の両側で、このバンプ１１にかかる応力を緩和することができ、半導体素子１と中継基板５間の電気的接続の信頼性を向上させることができる。
【００３４】
なお、この実施形態では、中継基板５に応力緩和用のスリット部７Ａ及び７Ｂを形成する場合について説明したが、図１０に示すように、この中継基板５には、スリット部ではなく、中継基板５を貫通しない溝部７Ａ´及び７Ｂ´を形成しても良い。この場合には、上述したスリット部７Ａ及び７Ｂと、中継基板５における位置、大きさ（深さを除く）が同じくなるように、溝部７Ａ´及び７Ｂ´を形成する。これにより、バンプ１１は、溝部７Ａ´及び７Ｂ´によって内側と外側から挟み込まれるので、バンプ１１にかかる応力を緩和することができ、半導体素子１と中継基板５間の電気的接続の信頼性を向上させることができる。また、溝部７Ａ´及び７Ｂ´を中継基板５の中層部分で止めるように形成することで、中継基板５の下層部分では、銅配線層のパターン形状を溝部の位置に関係なく決定することができる。これにより、スリット部７Ａ及び７Ｂを形成する場合と比べて、半導体装置１００を小さく形成することができる。
【００３５】
溝部７Ａ´及び７Ｂ´の形成方法は、例えば図８（Ｂ）において、中継基板５´上に感光性樹脂パターン１９を形成し、この感光性樹脂パターン１９をマスクにして、中継基板５´をハーフエッチングする。プラズマエッチングのエッチング時間を、スリット部７Ａ及び７Ｂを形成する際のエッチング時間の半分程度に設定することで、中継基板５´の中層部分まで溝部７Ａ´及び７Ｂ´を形成することができる。
【００３６】
同様に、この実施形態では、プリント配線基板９に応力緩和用のスリット部１７を形成する場合について説明したが、このプリント配線基板９には、スリット部ではなく、プリント配線基板９を貫通しない溝部を形成しても良い。ボール電極１３にかかる応力を緩和することができ、中継基板５とプリント配線基板９間の電気的接続の信頼性を向上させることができる。
【００３７】
また、この実施形態では、スリット部７Ａ及び７Ｂや、溝部７Ａ´及び７Ｂ´をプラズマエッチングによって形成する場合について説明したが、スリット部や溝部の形成手段はプラズマエッチングに限られることはない。例えば図８（Ａ）において、配線パターンを形成した後の中継基板５´や、プリント配線基板にドリルを当てて研削し、スリット部や溝部を形成しても良い。また、中継基板５´や、プリント配線基板９に金型を押し当てて型抜きし、スリット部や溝部を形成しても良い。さらに、レーザ等を用いてスリット部や溝部を形成しても良い。ドリルや、金型、レーザ等を用いる場合には、図８（Ｂ）に示したような感光性樹脂パターン１９は不要となるので、プラズマエッチングと比べて、スリット部や溝部の形成工程を短縮化することができる。
【図面の簡単な説明】
【図１】実施形態に係る半導体装置１００の構成例を示す概念図。
【図２】バンプ１１の配置例を示す概念図。
【図３】中継基板５の構成例を示す平面図。
【図４】半導体装置１００の構成例を示す平面図。
【図５】半導体装置１００の構成例を示すＸ１−Ｘ２矢視断面図。
【図６】中継基板５の他の例を示す平面図。
【図７】半導体装置１００の他の例（その１）を示す平面図。
【図８】半導体装置１００の製造方法（その１）を示す工程図。
【図９】半導体装置１００の製造方法（その２）を示す工程図
【図１０】半導体装置１００の他の例を示す断面図。
【図１１】従来例に係る半導体装置９０の構成例を示す概念図。
【符号の説明】
１ 半導体素子、３ 樹脂パッケージ、５、５´ 中継基板、７Ａ、７Ｂ、１７ スリット部、７Ａ´、７Ｂ´ 溝部、９ プリント配線基板、１１ バンプ、１３ ボール電極、１５ 配線パターン、１９ 感光性樹脂パターン、１００半導体装置[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device suitable for application to an LSI having an area ray package such as a BGA and a method of manufacturing the same.
[0002]
[Prior art]
In recent years, semiconductor devices mounted on electronic devices such as personal computers have been increasingly integrated. Along with this, the number of pins and the pitch of semiconductor devices have been increasing, and area array packages such as BGA (ball grid array) have become widespread.
[0003]
FIG. 11 is a cross-sectional view illustrating a configuration example of a semiconductor device 90 according to a conventional example. The semiconductor device 90 is a BGA type LSI. In this semiconductor device 90, the element forming surface side of a semiconductor element (not shown) formed of a silicon chip is mounted on a relay substrate 92, and the surface-mounted semiconductor element is sealed with a resin package 93.
The relay board 92 shown in FIG. 11 is formed by stacking a glass epoxy prepreg obtained by impregnating a glass cloth with an epoxy resin and a patterned copper wiring layer in multiple layers. The lowermost surface, which is the uppermost surface of the relay board 92, is a copper wiring layer. The copper wiring layers from the uppermost surface to the lowermost surface are connected as necessary by through holes whose inner wall surfaces are plated. As shown in FIG. 11, the relay board 92 has a plate shape, and its surface is flat.
[0004]
The electrical connection between the copper wiring layer on the uppermost surface of the relay board 92 and the semiconductor elements surface-mounted on the relay board 92 is made by bumps (for example, see Patent Document 1). This bump is made of solder.
In addition, as shown in FIG. 11, the lower surface of the relay board 92 is mounted on a printed wiring board 94 made of glass epoxy prepreg. A plurality of wiring patterns (not shown) are provided on the upper surface of the printed wiring board 94, and the wiring pattern on the upper surface of the printed wiring board 94 and the copper wiring layer on the lowermost surface of the relay board 92 are formed by ball electrodes. (See, for example, Patent Document 1).
[0005]
[Patent Document 1]
JP-A-11-135675 [Patent Document 2]
Japanese Patent Application Laid-Open No. 2000-100866 [Patent Document 3]
JP-A-10-189815 [Patent Document 4]
JP-A-10-150117 [Patent Document 5]
JP-A-6-342966
[Problems to be solved by the invention]
By the way, according to the semiconductor device 90 according to the conventional example, since the semiconductor element is made of a silicon chip and the relay board 92 is made of a glass epoxy prepreg, the matching of the thermal expansion coefficient between the semiconductor element 91 and the relay board 92 is improved. Not taken.
Therefore, in a heating process such as solder reflow for joining the ball electrodes to the wiring pattern on the upper surface of the printed wiring board 94, the semiconductor element 91 and the relay board 92 expand at different expansion rates, and the semiconductor element 91 and the relay board 92 expand. There is a problem that excessive stress is applied to the bumps that electrically connect the electrodes. If the stress applied to the bumps is large, the bumps themselves may be broken, and the reliability of the electrical connection between the semiconductor element 91 and the relay board 92 is reduced.
[0007]
Accordingly, the present invention is to solve such a problem of the prior art, and a semiconductor device and a semiconductor device capable of relaxing a stress generated between a semiconductor element and a wiring substrate due to a difference in thermal expansion coefficient. The purpose is to provide a manufacturing method.
[0008]
[Means for Solving the Problems]
In order to solve the above-described problems, a first semiconductor device according to the present invention includes a semiconductor element having a plurality of terminals on a peripheral portion of an element forming surface, a predetermined wiring pattern, and a semiconductor element forming element. A wiring board supporting the surface side; and a conductive member having one end joined to a terminal portion of the semiconductor element and the other end joined to a wiring pattern of the wiring board facing the semiconductor element. It is characterized in that the corner is sandwiched from the inside and outside in a plan view, and at least one pair of L-shaped grooves or slits is provided along the corner.
[0009]
A second semiconductor device according to the present invention is characterized in that, in the first semiconductor device described above, the conductive member is sandwiched between the inside and the outside by the groove or the slit.
A third semiconductor device according to the present invention is characterized in that, in the first and second semiconductor devices described above, the groove or the slit is R-shaped with respect to a corner of the semiconductor element. .
[0010]
According to a fourth semiconductor device of the present invention, in the first to third semiconductor devices described above, the wiring substrate is a first wiring substrate, the conductive member is a first conductive member, and the groove is Alternatively, when the slit portion is a first groove portion or a slit portion, a second wiring substrate having a predetermined wiring pattern and supporting the opposite side of the surface of the first wiring substrate on which the semiconductor element is mounted; A second conductive member joined to the wiring pattern of the first wiring board, and the other end is joined to the wiring pattern of the second wiring board facing the first wiring board. Is characterized by having an L-shaped second groove or slit along a corner of the first wiring board in plan view.
[0011]
Here, the semiconductor element is usually made of silicon, and the wiring board is usually made of a material other than silicon, such as glass epoxy prepreg or ceramic. For this reason, the semiconductor element and the wiring board have different thermal expansion coefficients, and in a heating step such as solder reflow, the semiconductor element and the wiring board expand at different expansion rates. Further, the semiconductor element is usually formed by dicing a silicon wafer into a rectangular shape. For this reason, a particularly large stress is generated between the semiconductor element and the wiring board at one end on the diagonal line having the largest dimension length of the semiconductor element, that is, around the corner of the semiconductor element.
[0012]
According to the first to fourth semiconductor devices according to the present invention, the corners of the semiconductor element are sandwiched between the inside and the outside in a plan view, and the corners are provided on the wiring board supporting the element forming surface side of the semiconductor element. At least one pair of L-shaped grooves or slits is provided. Therefore, in particular, the stress applied to the corners of the semiconductor element can be reduced, and the reliability of the electrical connection between the semiconductor element and the wiring board can be improved.
[0013]
The method of manufacturing a semiconductor device according to the present invention includes a step of attaching the element forming surface side of a semiconductor element having a plurality of terminal portions on a peripheral edge of the element forming surface to a wiring board having a predetermined wiring pattern; Joining one end of the conductive member to the terminal portion, joining the other end to the wiring pattern of the wiring board facing the semiconductor element, sandwiching the corner of the semiconductor element from inside and outside in plan view, and Forming at least one pair of L-shaped grooves or slits along the wiring board.
[0014]
According to the method of manufacturing a semiconductor device according to the present invention, the stress applied to the semiconductor element can be reduced inside and outside the corner of the semiconductor element, and the reliability of the electrical connection between the semiconductor element and the wiring board can be reduced. Can be improved.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a conceptual diagram showing a configuration example of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 is an LSI having a BGA type package. The semiconductor device 100 includes a semiconductor element having a plurality of pad electrodes on a peripheral portion of an element forming surface, a resin package 3 for sealing the semiconductor element, and a copper wiring layer, which is provided on a side of the element forming surface of the semiconductor element. A supporting relay substrate (interposer) 5 and a bump having one end bonded to a pad electrode which is a terminal portion of the semiconductor element and the other end bonded to a copper wiring layer on the uppermost surface of the relay substrate 5 and facing the pad electrode; It has. The semiconductor device 100 has a printed wiring board 9 and one end bonded to a copper wiring layer on the lowermost surface of the relay board 5, and the other end bonded to a wiring pattern on the upper surface of the printed wiring board 9 facing the relay board 5. Ball electrode.
[0016]
FIG. 2 is a conceptual diagram showing an example of the arrangement of the bumps 11 in the semiconductor element 1. The outline of the solid line in FIG. 2 indicates the outline of the resin package 3. Further, the inner frame of the broken line in FIG. 2 shows the outline of the semiconductor element 1 sealed by the resin package.
The semiconductor element 1 is formed, for example, by forming a large number of integrated circuit elements on the element forming surface side of a silicon wafer and then dicing the silicon wafer into rectangular pieces one by one for each integrated circuit element. The size of the semiconductor element 1 is, for example, about vertical × horizontal × thickness = 8 mm × 8 mm × 100 μm. The size of the resin package 3 is, for example, about length × width × thickness = about 10 mm × 10 mm × 1 mm.
[0017]
Further, a plurality of pad electrodes are provided on the peripheral edge of the element forming surface of the semiconductor element 1. The pad electrode is a terminal portion for extracting a source / drain, a gate electrode, and the like of a MOS transistor included in the integrated circuit element from a protective film for protecting the integrated circuit. The semiconductor element 1 including these pad electrodes is covered with a resin package 3.
[0018]
As shown in FIG. 2, a large number of bumps 11 are provided on the periphery of the semiconductor element 1 on the element forming surface side. One end of each of the bumps 11 is connected to the pad electrode described above, and the other end is slightly exposed from the resin package 3. When the dimension width of the row of the bumps 11 is W BUMP , W BUMP = 1 mm.
FIG. 3 is a plan view showing a configuration example of the relay board 5. The relay board 5 is formed by stacking a glass epoxy prepreg obtained by impregnating a glass cloth with an epoxy resin and a patterned copper wiring layer in multiple layers. For example, the relay board 5 is formed by alternately stacking about 4 to 6 layers of a copper wiring layer having a Line / Space of about 125 μm / 125 μm and a glass epoxy prepreg.
[0019]
Although not shown, a copper wiring layer is provided on the uppermost surface and the lowermost surface of the relay board 5. The copper wiring layers from the uppermost surface to the lowermost surface are connected as necessary by through holes whose inner wall surfaces are plated. A semiconductor element is surface-mounted substantially at the center of the relay board. Hereinafter, the position where the semiconductor element is surface-mounted is also referred to as a semiconductor element mounting position 31.
[0020]
As shown in FIG. 3, the relay board 5 has four pairs of L-shaped slits (through-grooves) 7A and 7B sandwiching the corners of the semiconductor element from the inside and outside in plan view and along the corners. Is provided. The outline of both the slits 7A and 7B is parallel to the edge of the relay board 5, and the corners of the slits 7A and 7B are located on the diagonal line of the relay board 5. Further, the slit portion 7B is provided inside the slit portion 7A.
[0021]
The size of the relay board 5 is, for example, about vertical × horizontal × thickness = 20 mm × 20 mm × 1 mm. Further, the slits 7A and 7B are formed in such a size that the strength required for supporting the semiconductor element is not impaired and the routing of the copper wiring on the relay board 5 is not hindered. For example, when the length and width of the side portions of the slits 7A are set to L A, W A, L A = 5mm, a W A = 1 mm. Each L B the length and width of the side portions of the slit portion 7B, when the W B, L B = 2mm, a W B = 0.4 mm. Further, as shown in FIG. 5, when the separation distance between the side portions of the slit portions 7A and 7B is L AB , L AB = about 3 mm. As shown in FIG. 4, the slit 7A is exposed from the resin package 3, and the slit 7B is covered by the resin package.
[0022]
The printed wiring board 9 has a base made of a glass epoxy prepreg obtained by impregnating a glass cloth with an epoxy resin, and has a wiring pattern (not shown) on the base. As shown in FIG. 4, the printed wiring board 9 is provided with an L-shaped slit portion 17 along a corner of the relay board 5. The contour of the slit 17 is parallel to the edge of the relay board 5. The slit portion is formed in a size that does not impair the strength necessary for supporting the semiconductor element and the relay substrate 5 and does not hinder the routing of the wiring pattern. For example, when the length and width of the side portion of the slit portion 17 are L and W, respectively, L = 10 mm and W = 2 mm. When the distance between the slit 17 and the relay board 5 is L ', L' is about 4 mm.
[0023]
By the way, according to the semiconductor device 100 of the present invention, as shown in FIG. 5, the bumps 11 for electrically connecting the semiconductor element 1 and the relay board 5 are provided with the slits 7A and 7B provided on the relay board 5. Is sandwiched between the inside and outside.
With this structure, even when the semiconductor element 1 and the relay substrate 5 expand at different expansion rates in a heating step such as solder reflow, and a stress that pushes the bump 11 inward or outward occurs, the stress is reduced to the slit portion. Absorbed to some extent by 7A and 7B. Therefore, since the stress applied to the bump 11 can be reduced, the reliability of the electrical connection between the semiconductor element 1 and the relay board 5 can be improved.
[0024]
In the case where the relay board 5 is made of ceramic and the printed wiring board 9 is made of glass epoxy prepreg, the thermal expansion coefficients of both members are different. Stress is generated between them. In this case, this stress is absorbed to some extent by the slit portion 17 (see FIG. 4). Therefore, the stress applied to the ball electrode 13 can be reduced, and the reliability of the electrical connection between the relay board 5 and the printed wiring board 9 can be improved.
[0025]
In this embodiment, the relay board 5 corresponds to the first wiring board of the present invention, and the printed wiring board 9 corresponds to the second wiring board of the present invention. The bump 11 corresponds to a first conductive member of the present invention, and the ball electrode 13 corresponds to a second conductive member of the present invention. Further, the slits 7A and 7B correspond to the first slit of the present invention, and the slit 17 corresponds to the second slit of the present invention.
[0026]
In this embodiment, the case where an organic glass epoxy prepreg is used for the first and second wiring boards of the present invention has been described, but the present invention is not limited to this. One or both of the first and second wiring boards of the present invention may be, for example, an inorganic ceramic wiring board. Also in these cases, the stress applied to the bump 11 can be reduced by the slits 7A and 7B due to the difference in the thermal expansion coefficient between the semiconductor element 1 and the relay board 5.
[0027]
Further, in this embodiment, the case where the slits 7A and 7B are L-shaped in plan view and the corners thereof are on the diagonal of the relay board 5 has been described, but the corners of the slits 7A and 7B are: As shown in FIG. 6, the semiconductor device may be curved in an R-shape with respect to a corner of the semiconductor element mounting position 31. Further, the corners of the slit 17 may be curved in an R shape as shown in FIG. In these cases, since the corners (singular points) of the slits 7A and 7B and the slit 17 are eliminated, the possibility of the relay board 5 and the printed wiring board 9 being cracked can be reduced.
[0028]
Next, a method for manufacturing the semiconductor device 100 according to the embodiment of the present invention will be described.
8 (A) to 8 (C) and FIG. 9 are process diagrams showing a method for manufacturing the semiconductor device 100 (Nos. 1 and 2). Here, the semiconductor device 100 shown in FIG. 1 will be described with reference to FIGS. 8A to 8C and the process chart of FIG. Therefore, in FIGS. 8A to 8C and FIG. 9, the same reference numerals are given to the portions corresponding to FIG.
[0029]
First, as shown in FIG. 8A, a relay board 5 'formed by stacking a glass epoxy prepreg obtained by impregnating a glass cloth with an epoxy resin and a patterned copper wiring layer in multiple layers is prepared. I do. The production of the relay board 5 'is performed by applying a known build-up wiring board technology.
Next, as shown in FIG. 8 (B), a photosensitive resin pattern 19 is formed on the relay substrate 5 'so as to open the areas to be the slits 7A and 7B and cover the other areas. The formation of the photosensitive resin pattern 19 is performed using a photolithography technique.
[0030]
Then, using the photosensitive resin pattern 19 as a mask, the relay substrate 5 is subjected to plasma etching. As a result, as shown in FIG. 8C, slit portions 17A and 17B penetrating through the relay board 5 are formed.
Similarly, a photosensitive resin pattern (not shown) is formed on the printed wiring board so as to open a region to be the slit portion 17 (see FIG. 4). Then, the printed wiring board is subjected to plasma etching using the photosensitive resin pattern as a mask to form a slit portion 17 penetrating the printed wiring board.
[0031]
Thereafter, as shown in FIG. 9, the element forming surface side of the semiconductor element 1 is mounted on the relay substrate 5, and the semiconductor element 1 and the relay substrate 5 are connected by bumps. At this time, it is preferable to confirm the mounting position of the semiconductor element using the slits 7A and 7B as a mark. As a result, it is possible to reduce mistakes in attaching the semiconductor element 1 to the relay board 5. Next, the semiconductor element 1 attached to the relay board 5 is sealed with a resin package.
[0032]
Further, the relay board 5 to which the semiconductor element 1 is mounted is mounted on the printed wiring board 9, and the relay board 5 and the printed wiring board 9 are connected by ball electrodes. At this time, it is preferable to confirm the mounting position of the relay board using the slit portion 17 as a mark. As a result, it is possible to reduce mistakes in attaching the relay board 5 to the printed wiring board 9. Thus, the semiconductor device 100 shown in FIG. 1 is completed.
[0033]
According to the method for manufacturing the semiconductor device 100 according to the present invention, as shown in FIG. 5, the relay substrate 5 is a region corresponding to a corner of the semiconductor element 1 so as to sandwich the bump 11 from inside and outside. The slits 7A and 7B are formed. Therefore, the stress applied to the bump 11 can be reduced on both the inside and the outside of the bump 11, and the reliability of the electrical connection between the semiconductor element 1 and the relay substrate 5 can be improved.
[0034]
In this embodiment, the case where the slit portions 7A and 7B for stress relaxation are formed in the relay board 5 has been described. However, as shown in FIG. The grooves 7A 'and 7B' which do not pass through the groove 5 may be formed. In this case, the grooves 7A 'and 7B' are formed such that the positions and sizes (excluding the depth) of the slits 7A and 7B in the relay board 5 are the same as those of the slits 7A and 7B. As a result, the bump 11 is sandwiched between the inside and the outside by the grooves 7A 'and 7B', so that the stress applied to the bump 11 can be reduced, and the reliability of the electrical connection between the semiconductor element 1 and the relay board 5 can be improved. Can be improved. Further, by forming the grooves 7A 'and 7B' so as to be stopped at the middle layer of the relay board 5, the pattern shape of the copper wiring layer can be determined in the lower layer of the relay board 5 regardless of the position of the groove. . Thus, the semiconductor device 100 can be formed smaller than when the slits 7A and 7B are formed.
[0035]
The groove portions 7A 'and 7B' can be formed, for example, by forming a photosensitive resin pattern 19 on the relay substrate 5 'and using the photosensitive resin pattern 19 as a mask to form the relay substrate 5' in FIG. Half-etch. By setting the etching time of the plasma etching to about half of the etching time for forming the slits 7A and 7B, the grooves 7A 'and 7B' can be formed up to the middle layer portion of the relay substrate 5 '.
[0036]
Similarly, in this embodiment, the case where the slit portion 17 for stress relaxation is formed in the printed wiring board 9 has been described. However, this printed wiring board 9 is not a slit portion, but a groove portion that does not penetrate the printed wiring board 9. May be formed. The stress applied to the ball electrode 13 can be reduced, and the reliability of the electrical connection between the relay board 5 and the printed wiring board 9 can be improved.
[0037]
In this embodiment, the case where the slits 7A and 7B and the grooves 7A 'and 7B' are formed by plasma etching has been described, but the means for forming the slits and grooves is not limited to plasma etching. For example, in FIG. 8A, a slit portion or a groove portion may be formed by applying a drill to the relay board 5 'after forming the wiring pattern or the printed wiring board and grinding the same. Alternatively, a slit may be formed by pressing a die against the relay board 5 ′ or the printed wiring board 9 to form a slit or a groove. Further, a slit or a groove may be formed by using a laser or the like. When a drill, a mold, a laser, or the like is used, the photosensitive resin pattern 19 as shown in FIG. 8B is not necessary, so that the process of forming the slits and grooves is shorter than in the case of plasma etching. Can be
[Brief description of the drawings]
FIG. 1 is a conceptual diagram showing a configuration example of a semiconductor device 100 according to an embodiment.
FIG. 2 is a conceptual diagram showing an example of the arrangement of bumps 11;
FIG. 3 is a plan view showing a configuration example of a relay board 5;
FIG. 4 is a plan view illustrating a configuration example of a semiconductor device 100.
FIG. 5 is a cross-sectional view taken along the line X1-X2 showing a configuration example of the semiconductor device 100.
FIG. 6 is a plan view showing another example of the relay board 5;
FIG. 7 is a plan view showing another example (part 1) of the semiconductor device 100;
FIG. 8 is a process view showing a method (part 1) of manufacturing semiconductor device 100;
FIG. 9 is a process chart showing a manufacturing method (part 2) of the semiconductor device 100. FIG. 10 is a sectional view showing another example of the semiconductor device 100.
FIG. 11 is a conceptual diagram showing a configuration example of a semiconductor device 90 according to a conventional example.
[Explanation of symbols]
Reference Signs List 1 semiconductor element, 3 resin package, 5, 5 'relay board, 7A, 7B, 17 slit section, 7A', 7B 'groove section, 9 printed wiring board, 11 bump, 13 ball electrode, 15 wiring pattern, 19 photosensitive resin Pattern, 100 semiconductor device

Claims (5)

複数の端子部を素子形成面の周縁部に有する半導体素子と、
所定の配線パターンを有し、前記半導体素子の素子形成面側を支持する配線基板と、
一端を前記半導体素子の端子部に接合され、他端を当該半導体素子と向かい合う配線基板の配線パターンに接合された導電部材とを備え、
前記配線基板は、
前記半導体素子の角部を平面視で内側外側から挟み込み、且つその角部に沿ったＬ字状の溝部またはスリット部を少なくとも一対備えていることを特徴とする半導体装置。A semiconductor element having a plurality of terminal portions on a peripheral portion of the element formation surface;
A wiring board having a predetermined wiring pattern and supporting an element forming surface side of the semiconductor element;
A conductive member having one end joined to a terminal portion of the semiconductor element and the other end joined to a wiring pattern of a wiring board facing the semiconductor element;
The wiring board,
A semiconductor device comprising: a semiconductor element having at least one pair of L-shaped grooves or slits sandwiching a corner of the semiconductor element from the inside and outside in a plan view and extending along the corner. 前記導電部材は、
前記溝部またはスリット部によって内側と外側から挟み込まれていることを特徴とする請求項１に記載の半導体装置。The conductive member,
The semiconductor device according to claim 1, wherein the semiconductor device is sandwiched between the inside and the outside by the groove or the slit. 前記溝部またはスリット部は、
前記半導体素子の角部に対してＲ状であることを特徴とする請求項１または２に記載の半導体装置。The groove or slit,
3. The semiconductor device according to claim 1, wherein the semiconductor element has an R shape with respect to a corner. 前記配線基板を第１の配線基板とすると共に、前記導電部材を第１の導電部材とし、さらに前記溝部またはスリット部を第１の溝部またはスリット部としたとき、
所定の配線パターンを有し、前記第１の配線基板の半導体素子が取り付けられた面の反対側を支持する第２の配線基板と、
一端を前記第１の配線基板の配線パターンに接合され、他端を当該第１の配線基板と向かい合う第２の配線基板の配線パターンに接合された第２の導電部材とを備え、
前記第２の配線基板は、
平面視で前記第１の配線基板の角部に沿ったＬ字状の第２の溝部またはスリット部を備えたことを特徴とする請求項１〜３のいずれか一項に記載の半導体装置。When the wiring board is a first wiring board, the conductive member is a first conductive member, and the groove or slit is a first groove or slit.
A second wiring board having a predetermined wiring pattern and supporting the opposite side of the surface of the first wiring board on which the semiconductor element is mounted;
A second conductive member having one end joined to a wiring pattern of the first wiring board and the other end joined to a wiring pattern of a second wiring board facing the first wiring board;
The second wiring board includes:
4. The semiconductor device according to claim 1, further comprising an L-shaped second groove or slit along a corner of the first wiring board in a plan view. 5. 複数の端子部を素子形成面の周縁部に有する半導体素子の該素子形成面側を所定の配線パターンを有する配線基板に取り付ける工程と、
前記半導体素子の端子部に導電部材の一端を接合すると共に、他端を当該半導体素子と向かい合う配線基板の配線パターンに接合する工程と、
前記半導体素子の角部を平面視で内側外側から挟み込み、且つその角部に沿うようなＬ字状の溝部またはスリット部を前記配線基板に少なくとも一対形成する工程、とを有することを特徴とする半導体装置の製造方法。A step of attaching the element forming surface side of a semiconductor element having a plurality of terminal portions on a peripheral portion of the element forming surface to a wiring board having a predetermined wiring pattern;
Joining one end of a conductive member to a terminal portion of the semiconductor element, and joining the other end to a wiring pattern of a wiring board facing the semiconductor element;
Forming at least one pair of L-shaped grooves or slits in the wiring board so as to sandwich the corners of the semiconductor element from the inside and outside in plan view and to extend along the corners. A method for manufacturing a semiconductor device.
JP2003034962A 2003-02-13 2003-02-13 Semiconductor device and manufacturing method therefor Pending JP2004247464A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003034962A JP2004247464A (en) 2003-02-13 2003-02-13 Semiconductor device and manufacturing method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003034962A JP2004247464A (en) 2003-02-13 2003-02-13 Semiconductor device and manufacturing method therefor

Publications (1)

Publication Number Publication Date
JP2004247464A true JP2004247464A (en) 2004-09-02

Family

ID=33020513

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003034962A Pending JP2004247464A (en) 2003-02-13 2003-02-13 Semiconductor device and manufacturing method therefor

Country Status (1)

Country Link
JP (1) JP2004247464A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012086107A1 (en) * 2010-12-24 2012-06-28 パナソニック株式会社 Intermediate for electronic component mounting structure, electronic component mounting structure, and method for manufacturing electronic component mounting structure
JP2013149797A (en) * 2012-01-19 2013-08-01 Denso Corp Semiconductor package
CN108630615A (en) * 2017-03-14 2018-10-09 联发科技股份有限公司 Semiconductor package and board structure
CN112103277A (en) * 2019-06-17 2020-12-18 联发科技股份有限公司 Semiconductor packaging structure
US11171113B2 (en) 2017-03-14 2021-11-09 Mediatek Inc. Semiconductor package structure having an annular frame with truncated corners
US11264337B2 (en) 2017-03-14 2022-03-01 Mediatek Inc. Semiconductor package structure
US11362044B2 (en) 2017-03-14 2022-06-14 Mediatek Inc. Semiconductor package structure
US11387176B2 (en) 2017-03-14 2022-07-12 Mediatek Inc. Semiconductor package structure

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012086107A1 (en) * 2010-12-24 2012-06-28 パナソニック株式会社 Intermediate for electronic component mounting structure, electronic component mounting structure, and method for manufacturing electronic component mounting structure
US9041221B2 (en) 2010-12-24 2015-05-26 Panasonic Intellectual Property Management Co., Ltd. Electronic component implementing structure intermediate body, electronic component implementing structure body and manufacturing method of electronic component implementing structure body
JP2013149797A (en) * 2012-01-19 2013-08-01 Denso Corp Semiconductor package
US11362044B2 (en) 2017-03-14 2022-06-14 Mediatek Inc. Semiconductor package structure
US10784211B2 (en) 2017-03-14 2020-09-22 Mediatek Inc. Semiconductor package structure
US11171113B2 (en) 2017-03-14 2021-11-09 Mediatek Inc. Semiconductor package structure having an annular frame with truncated corners
US11264337B2 (en) 2017-03-14 2022-03-01 Mediatek Inc. Semiconductor package structure
CN108630615A (en) * 2017-03-14 2018-10-09 联发科技股份有限公司 Semiconductor package and board structure
US11387176B2 (en) 2017-03-14 2022-07-12 Mediatek Inc. Semiconductor package structure
US11410936B2 (en) 2017-03-14 2022-08-09 Mediatek Inc. Semiconductor package structure
US11646295B2 (en) 2017-03-14 2023-05-09 Mediatek Inc. Semiconductor package structure having an annular frame with truncated corners
US11862578B2 (en) 2017-03-14 2024-01-02 Mediatek Inc. Semiconductor package structure
US11942439B2 (en) 2017-03-14 2024-03-26 Mediatek Inc. Semiconductor package structure
US11948895B2 (en) 2017-03-14 2024-04-02 Mediatek Inc. Semiconductor package structure
CN112103277A (en) * 2019-06-17 2020-12-18 联发科技股份有限公司 Semiconductor packaging structure
CN112103277B (en) * 2019-06-17 2023-09-01 联发科技股份有限公司 Semiconductor packaging structure

Similar Documents

Publication Publication Date Title
JP5143451B2 (en) Semiconductor device and manufacturing method thereof
US7719104B2 (en) Circuit board structure with embedded semiconductor chip and method for fabricating the same
US20130000955A1 (en) Wiring board and manufacturing method of the same
KR100934269B1 (en) Rigid wave pattern design on chip carrier and printed circuit boards for semiconductor and electronic sub-system packaging
JP2012104790A (en) Semiconductor device
JP5193809B2 (en) Wiring board and manufacturing method thereof
TW200408319A (en) Warpage-preventing circuit board and method for fabricating the same
US7247950B2 (en) Semiconductor device and method of manufacturing the same
TW201312713A (en) Semiconductor device, semiconductor module structure configured by vertically stacking semiconductor devices, and manufacturing method thereof
JP6157998B2 (en) Semiconductor device
JP2005175263A (en) Semiconductor device, manufacturing method therefor, and electronic equipment
JP2004214543A (en) Semiconductor device and manufacturing method thereof
JP3892259B2 (en) Manufacturing method of semiconductor device
JP3291289B2 (en) Electronic component manufacturing method
JP2004247464A (en) Semiconductor device and manufacturing method therefor
WO2011021364A1 (en) Semiconductor device and manufacturing method therefor
JP4556671B2 (en) Semiconductor package and flexible circuit board
JP2004047777A (en) Semiconductor device and its manufacturing method
US7361982B2 (en) Bumpless chip package
JP4894347B2 (en) Semiconductor integrated circuit element mounting substrate and semiconductor device
JP2004165193A (en) Semiconductor device and its manufacturing method
JP2006100666A (en) Semiconductor device and manufacturing method thereof
JP6678196B2 (en) Semiconductor device and wiring structure manufacturing method
JP2004006670A (en) Semiconductor wafer with spacer and manufacturing method thereof, semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
JP2002231761A (en) Electronic component and mounting body thereof