CN100377337C - Semiconductor device, wiring substrate, and method for manufacturing wiring substrate - Google Patents

Semiconductor device, wiring substrate, and method for manufacturing wiring substrate Download PDF

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Publication number
CN100377337C
CN100377337C CNB2003801038650A CN200380103865A CN100377337C CN 100377337 C CN100377337 C CN 100377337C CN B2003801038650 A CNB2003801038650 A CN B2003801038650A CN 200380103865 A CN200380103865 A CN 200380103865A CN 100377337 C CN100377337 C CN 100377337C
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Prior art keywords
wiring layer
base substrate
semiconductor chip
circuit board
chip
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CN1714444A (en
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西山知宏
田子雅基
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Godo Kaisha IP Bridge 1
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NEC Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

The reliabilities of a wiring substrate and a semiconductor apparatus are improved by reducing the internal stress caused by the difference of thermal expansion coefficients between a base substrate and a semiconductor chip. A wiring layer ( 5 ) is provided on one surface of a silicon base ( 3 ). An electrode as the uppermost layer of the wiring layer ( 5 ) is provided with an external bonding bump ( 7 ). A through-electrode ( 4 ) is formed in the base ( 3 ) for electrically connecting the wiring layer ( 5 ) and an electrode terminal. The electrode terminal on the chip mounting surface is bonded to an electrode terminal of a semiconductor chip ( 1 ) by an internal bonding bump ( 6 ). The thermal expansion coefficient of the silicon base ( 3 ) is equivalent to that of the semiconductor chip ( 1 ) and not more than that of the wiring layer ( 5 ).

Description

Semiconductor device, circuit board and circuit board manufacture method
Technical field
The present invention relates to circuit board and the circuit board manufacture method used in semiconductor device, the semiconductor device, particularly as circuit board and the circuit board manufacture method used in the flip-chip type semiconductor device of the mode that faces down, the flip-chip type semiconductor device.
Background technology
In order to prove absolutely the current technical level relevant,,, enroll its all explanation herein with reference to all patents that quote among the application or specially appointed, patent application, patent gazette, scientific paper etc. with the present invention.
In recent years, in order to improve the packing density of semiconductor package part, advancing miniaturization, miniaturization, the multitube pinization of packaging part, as electrode terminal interval, miniaturization, the multitube pinization corresponding technology big with maintenance, regional ground configured electrodes terminal is effective.This is meant in 2 times that connect semiconductor package part and motherboard are installed, by the soft solder projection that on interposer substrate, disposes regionally, make the semiconductor packaging of the ball grid array type that electrode is connected with motherboard, be meant in 1 time that connects semiconductor chip and interposer substrate is installed the same flip-chip interconnection technique that disposes soft solder projection and golden projection etc. regionally and connect on the function face of semiconductor chip.
Fig. 1 is the cutaway view of the structure of the semiconductor device before the expression.Adopted the semiconductor device of such semiconductor packaging and flip-chip interconnection technique to be changed to flip chip ball grid array shown in Figure 1 (FCBGA), to miniaturization, miniaturization, multitube pinization is favourable, in addition, compare with the semiconductor package part of the line bridging type that is connected semiconductor chip and interposer substrate with gold thread, the cloth line resistance is little, be more suitable for high speed motion, thereby be expected that purposes is wider from now on.Also have, the interposer substrate material roughly is divided into resin material and ceramic material, but, has adopted the resin material substrate that is having superiority aspect manufacturing cost and the electrical characteristics mostly.Also have,, open to have provided in the flat 08-167630 communique the spy and form wiring in the polymeric material with low thermal coefficient of expansion close, connect the structure of chip and wiring by through hole with silicon as the example that has used the flip-chip interconnection technique.This structure has also reduced erection space than the line overlap joint, and has shortened the connection distance, and has realized the alleviation of thermal stress owing to the thermal coefficient of expansion close with silicon.
The exploitation of LSI till now is when transistorized size is made 1/k, and the aggregation degree is k 2Doubly, responsiveness is that the doubly such scaling rule of k advances, but, because the carrying out of miniaturization and the requirement of high speed motion, the caused so-called RC of the increase of electric capacity (C) postpones just to become and can not ignore between cloth line resistance (R), wiring, and in order to reduce the cloth line resistance, wiring material is hopeful to adopt copper, in order to reduce electric capacity between wiring, interlayer dielectric is hopeful to adopt low permitivity film (Low-k film).In addition, make LSI at the high-frequency region operating stably, just need be and dispose decoupling capacitor for the stabilisation of supply voltage and high frequency noise countermeasure, so proposed, by silicon monomer or by containing the substrate that silicon insulating film constitutes, or formed the capacitor device of jumbo capacitor on the substrate that constitutes by sapphire and the assembly of capacitor device has been installed with through hole.For example open in the 2002-008942 communique and disclosed this point the spy.
Also have, LSI highly integrated and in 1 chip, make various function element and memory element etc. and the system chip technology that forms system constantly develops, cause the multitube pinization, the electrode zone of having offset flip-chip disposes miniaturization and the miniaturization that is caused, and still there is the tendency of maximization in semiconductor chip.
Yet, in the former technology, in the structure of flip-chip type semiconductor device shown in Figure 1, adopted the occasion of resin substrate at interposer substrate, mainly silicon at room temperature is about 2.6ppm/ ℃ as the linear expansivity of the semiconductor chip of mother metal, resin substrate then be about 15ppm/ ℃, its difference very big, the caused big internal stress of thermal expansion rate variance will be present in the semiconductor device.Be to reinforce at present, keep reliability by potting resin in the gap, junction surface of semiconductor chip and interposer substrate, but, can envision, follow the outside terminal increase from now on and cause semiconductor chip to maximize, directly cause the increase of internal stress, just can not guarantee reliability.Above-mentioned spy opens that semiconductor chip also is connected on the organic layer that has formed capacitor in the semiconductor device structure that discloses in the 2002-8942 communique, and the problem that the caused thermal stress of the difference of the coefficient of expansion is concentrated can not be avoided.Also have, be also included within above-mentioned spy and open the joint construction that discloses among the 08-167630, all exist make thermal coefficient of expansion consistent with silicon interposer substrate on the packaging part installed when motherboard is installed, reduce such problem owing to the caused internal stress of thermal expansion difference makes reliability.
Have again, postpone one of countermeasure and consider that the Low-k film of using is at silica (SiO as RC 2) doped with fluorine, hydrogen, organic substance etc. in the film, by means of the material of porous permittivity is descended, than former interlayer dielectric fragilities such as silicon oxide film, this is known.The tolerable limit that this means the internal stress that produces owing to linear expansivity difference between above-mentioned semiconductor chip and interposer substrate can reduce, and will cause the problem on the reliability when advancing miniaturization, multitube pin from now on.
Have, in recent years, as the caused groundwater pollution countermeasure of lead, the tin/plumbous soft solder that adopts in the solder material before the handlebar was changed to the trend of lead-free solder, also will abolish leaded soft solder fully in each company of person in electronics again.Accompany therewith, make because the tissue of soft solder self changes the tin/plumbous soft solder of the stress relieve effect that the stress that produced at the junction surface reduces different with having, lead-free solder based on tin, the stress relieve effect is very little, internal stress increases as a result, can cause the problem on the reliability when advancing miniaturization, multitube pin from now on.
Summary of the invention
The object of the present invention is to provide the semiconductor device that does not have the problems referred to above point.
Have, the object of the present invention is to provide the caused internal stress of thermal expansion rate variance of circuit board to be lowered, reliability improves, the semiconductor device of corresponding more miniaturization of energy and multitube pinization.
Have, the object of the present invention is to provide does not have the semiconductor device of the problems referred to above point circuit board again.
Have, the object of the present invention is to provide the caused internal stress of thermal expansion rate variance of circuit board to be lowered, reliability improves, the semiconductor device circuit board of corresponding more miniaturization of energy and multitube pinization.
Have again, the object of the present invention is to provide the semiconductor device that the does not have the problems referred to above point manufacture method of circuit board.
Have, the object of the present invention is to provide the caused internal stress of thermal expansion rate variance of circuit board to be lowered, reliability improves, the semiconductor device manufacture method of circuit board of corresponding more miniaturization of energy and multitube pinization.
According to first side of the present invention, a kind of semiconductor device that semiconductor chip has been installed by the flip-chip mode on circuit board is provided, above-mentioned circuit board comprises: base substrate; Have the interlayer dielectric that on the wiring layer formation face of the one side of this base substrate, forms and the wiring layer of wiring; Form the 1st electrode that forms on the chip installed surface at the back side of face at above-mentioned wiring layer as the above-mentioned base substrate of carrying above-mentioned semiconductor chip; Be filled in the conductor inside of the through hole that forms on the above-mentioned base substrate, and the 2nd electrode that on the back side of the face that joins with described base substrate of described wiring layer, forms, described conductor, described the 1st electrode that directly is formed at the described wiring layer on the described wiring layer formation face and be formed on the described chip installed surface is electrically connected, the coefficient of thermal expansion of above-mentioned base substrate is suitable with above-mentioned semiconductor chip, or be below the coefficient of thermal expansion of above-mentioned wiring layer, above-mentioned semiconductor chip faces down and is connected on the said chip installed surface.Have, preferably, the coefficient of thermal expansion of above-mentioned semiconductor chip is lower than the coefficient of thermal expansion of above-mentioned wiring layer again.
According to this formation, semiconductor-chip-mounting thereby can suppress the thermal expansion difference of semiconductor chip and base substrate on the base substrate of circuit board, can improve the connection reliability of semiconductor chip and circuit board.Also have, in the occasion that this formation is installed on the motherboard substrate, the wiring layer of circuit board is facing to motherboard substrate, owing between motherboard substrate and base substrate, have wiring layer, thereby wiring layer can alleviate the caused stress of thermal expansion difference between motherboard substrate and base substrate, can improve reliability of electrical connection.In this explanation, as the substrate that circuit board of the present invention has been installed, motherboard substrate has been described in example, but, be not limited to this, so long as the substrate of circuit board of the present invention has been installed, other substrate outside the above-mentioned base substrate is also passable, in this manual, support substrate is to mean the substrate that circuit board of the present invention has been installed with other substrate outside the above-mentioned base substrate.
The material of above-mentioned base substrate can be made of in silicon, pottery and the photosensitive glass any one.
Can be at least a portion of the peripheral part of the loading position of the above-mentioned semiconductor chip of said chip installed surface bonding stiffening frame.Have, preferably, the coefficient of thermal expansion and the semiconductor chip of stiffening frame are suitable, or are below the coefficient of thermal expansion of wiring layer again.
The thickness of above-mentioned base substrate can be that at least a portion of the peripheral part of the above-mentioned semiconductor-chip-mounting position of said chip installed surface is thicker than the loading position of the above-mentioned semiconductor chip of said chip installed surface.
Can at least 1 side of above-mentioned wiring layer formation face and above-mentioned wiring layer, form function element.
According to second side of the present invention, provide a kind of and the circuit board of semiconductor chip is installed by the flip-chip mode, comprising: base substrate; Have the interlayer dielectric that on the wiring layer formation face of the one side of this base substrate, forms and the wiring layer of wiring; Form the 1st electrode that forms on the chip installed surface at the back side of face at above-mentioned wiring layer as the above-mentioned base substrate of carrying above-mentioned semiconductor chip; Be filled in the conductor inside of the through hole that forms on the above-mentioned base substrate, and the 2nd electrode that on the back side of the face that joins with described base substrate of described wiring layer, forms, described conductor, described the 1st electrode that directly is formed at the described wiring layer on the described wiring layer formation face and be formed on the described chip installed surface is electrically connected, the coefficient of thermal expansion of above-mentioned base substrate is suitable with above-mentioned semiconductor chip, or is below the coefficient of thermal expansion of above-mentioned wiring layer.Have, preferably, the coefficient of thermal expansion of above-mentioned semiconductor chip is lower than the coefficient of thermal expansion of above-mentioned wiring layer again.
According to this formation, can obtain the semiconductor device relevant above-mentioned effect related with first side of the present invention.
The material of above-mentioned base substrate can be made of in silicon, pottery and the photosensitive glass any one.
Can be at least a portion of the peripheral part of the loading position of the above-mentioned semiconductor chip of said chip installed surface bonding stiffening frame.Preferably, the coefficient of thermal expansion and the semiconductor chip of stiffening frame are suitable, or are below the coefficient of thermal expansion of wiring layer.
The thickness of above-mentioned base substrate can be that at least a portion of the peripheral part of the above-mentioned semiconductor-chip-mounting position of said chip installed surface is thicker than the loading position of the above-mentioned semiconductor chip of said chip installed surface.
Can at least 1 side of above-mentioned wiring layer formation face and above-mentioned wiring layer, form function element.
According to the 3rd side of the present invention, a kind of circuit board manufacture method of making circuit board is provided, above-mentioned circuit board is by base substrate and have that wiring layer in the one side of this base substrate forms the interlayer dielectric that forms on the face and the wiring layer of wiring constitutes, by the flip-chip mode semiconductor chip is installed, above-mentioned circuit board manufacture method comprises: form the operation that the face side forms non-through hole from the above-mentioned wiring layer of above-mentioned base substrate; With the above-mentioned non-through hole of conductive material landfill, on above-mentioned wiring layer formation face, form the operation of the 1st electrode; On above-mentioned wiring layer formation face, directly form the operation of above-mentioned wiring layer; And form the above-mentioned base substrate of thinning back side of face from above-mentioned wiring layer, and above-mentioned non-through hole is exposed, form the operation of the 2nd electrode that carries above-mentioned semiconductor chip.
The processing capacity of at least a portion that can comprise the peripheral part of the loading position that makes above-mentioned semiconductor chip again lacks than the processing capacity of the loading position of above-mentioned semiconductor chip, forms step and the operation of the above-mentioned base substrate of attenuate in the above-mentioned at least a portion of the peripheral part of the loading position of above-mentioned semiconductor chip and the above-mentioned loading position of above-mentioned semiconductor chip.
Can in the operation that forms above-mentioned wiring layer, form function element again.
According to the 4th side of the present invention, a kind of circuit board manufacture method of making circuit board is provided, above-mentioned circuit board is by base substrate and form the wiring layer that forms on the face at the wiring layer of the one side of this base substrate and constitute, by the flip-chip mode semiconductor chip is installed, above-mentioned circuit board manufacture method comprises: the operation that directly forms wiring layer on the above-mentioned wiring layer formation face of above-mentioned base substrate; Form the operation of the through hole that only connects above-mentioned base substrate from the rear side of above-mentioned wiring layer formation face; And with the above-mentioned through hole of conductive material landfill, form the operation of the electrode that carries above-mentioned semiconductor chip at the back side that above-mentioned wiring layer forms face.
The processing capacity of at least a portion that can comprise the peripheral part of the loading position that makes above-mentioned semiconductor chip again lacks than the processing capacity of the loading position of above-mentioned semiconductor chip, forms step and the operation of the above-mentioned base substrate of attenuate in the above-mentioned at least a portion of the peripheral part of the loading position of above-mentioned semiconductor chip and the above-mentioned loading position of above-mentioned semiconductor chip.
Can in the operation that forms above-mentioned wiring layer, form function element again.
According to above-mentioned first to fourth side of the present invention, semiconductor device, circuit board and circuit board manufacture method, because the base substrate of the circuit board of the characteristic that semiconductor chip is close with having coefficient of thermal expansion is connected, thereby the caused internal stress of coefficient of thermal expansion mismatch is greatly reduced, have again, semiconductor device also is lowered to the variation of the installation of motherboard and the caused internal stress of variations in temperature under the environment for use, thereby can improve reliability, can overcome the maximization of the semiconductor chip of following outside terminal increase from now on, interlayer dielectric adopts fragile Low-k film, the permissible level of the internal stresss such as stress relieve minimizing of the unleaded caused soft solder of soft solder of environment correspondence reduces.
Have again, in the formation of the wiring layer of circuit board, owing on the high base substrate of rigidity, form, thereby fine wiring pattern shape is formed is favourable, and roughly all semiconductor device manufacturing processes can handle under wafer-level, thereby can enhance productivity, cut down manufacturing cost.
Have again, owing to producing stress at the employed resin material of interlayer dielectric of the most of volume that accounts for the wiring layer that forms at the back side of the chip installed surface of circuit board and the thermal expansion rate variance between the base substrate, but, because bonding stiffening frame at least a portion of the peripheral part of the loading position of the semiconductor chip of chip installed surface, thereby in the occasion of doing the loading position of the semiconductor chip of base substrate extremely thinly, the rigidity that also can keep base substrate, the result just can suppress the warpage of circuit board, improves installation property, reliability.
Have again, owing to producing stress at the employed resin material of interlayer dielectric of the most of volume that accounts for the wiring layer that forms at the back side of the chip installed surface of circuit board and the thermal expansion rate variance between the base substrate, but, owing to thickeied at least a portion of peripheral part of loading position of the semiconductor chip of chip installed surface, thereby in the occasion of doing the loading position of the semiconductor chip of base substrate extremely thinly, the rigidity that also can keep base substrate, the result just can suppress the warpage of circuit board, improve installation property, reliability, and base substrate is being carried out the also formation in the lump of step that attenuate adds the periphery in man-hour, thereby just can simplify technology, cutting down cost.
Have again, owing to made on the wiring layer formation face of base substrate or formed the formation of function element such as capacitor, resistance, inductor on the wiring layer, thereby can improve high frequency characteristics or realize multifunction by function element such as the optimal position configuration capacitor in wiring layer, resistance, inductors, can also reduce erection space, improve design freedom.
Have, stacked wiring layer on the base substrate little at coefficient of thermal expansion, that rigidity is high is compared with the occasion of stacked wiring layer on the resin system base material, can form finer wiring figure again.
Description of drawings
Fig. 1 is the cutaway view of the structure of the semiconductor device before the expression.
Fig. 2 A is the cutaway view of the 1st example of structure of the semiconductor device of expression the 1st execution mode involved in the present invention.
Fig. 2 B is the cutaway view of the 2nd example of structure of the semiconductor device of expression the 1st execution mode involved in the present invention.
Fig. 2 C is the cutaway view of the 3rd example of structure of the semiconductor device of expression the 1st execution mode involved in the present invention.
Fig. 3 A is the cutaway view of the circuit board in each process chart relevant with the manufacture method of the wiring of semiconductor device substrate of the 1st execution mode involved in the present invention to Fig. 3 F.
Fig. 4 is the cutaway view of structure of the semiconductor device of expression the 2nd execution mode involved in the present invention.
Fig. 5 A is the cutaway view of the circuit board in each process chart relevant with the manufacture method of the wiring of semiconductor device substrate of the 3rd execution mode involved in the present invention to Fig. 5 E.
Fig. 6 is the cutaway view of structure of the semiconductor device of expression the 4th execution mode involved in the present invention.
Fig. 7 A is the cutaway view of the semiconductor device in the later assembly process of the flip-chip bond operation of semiconductor device of the 4th execution mode involved in the present invention to Fig. 7 D.
Embodiment
(the 1st execution mode)
Below, describe embodiments of the present invention in detail according to accompanying drawing.Fig. 2 A is the cutaway view of the 1st example of structure of the semiconductor device of expression the 1st execution mode involved in the present invention.Fig. 2 B is the cutaway view of the 2nd example of structure of the semiconductor device of expression the 1st execution mode involved in the present invention.Fig. 2 C is the cutaway view of the 3rd example of structure of the semiconductor device of expression the 1st execution mode involved in the present invention.Fig. 3 A is the cutaway view of the circuit board in each process chart relevant with the manufacture method of the wiring of semiconductor device substrate of the 1st execution mode involved in the present invention to Fig. 3 F.
The 1st execution mode with reference to Fig. 2 A, as circuit board 2, has formed single or multiple lift wiring layer 5 on the one side of the base substrate 3 that is made of silicon, formed outside connection projection 7 on the electrode of the superiors of wiring layer 5.Formed on the base substrate 3 on wiring layer 5 and do not form the through hole 4 that the electrode terminal on the face (hereinafter referred to as the chip installed surface) of the wiring layer 5 of base substrate 3 is electrically connected, the electrode terminal of the electrode terminal of chip installed surface and semiconductor chip 1 is connected projection 6 by tin/inside such as plumbous soft solder and carries out electricity, mechanical connection.
Also have, the coefficient of thermal expansion of the base substrate 3 that is made of silicon is suitable with semiconductor chip 1, and is below the coefficient of thermal expansion of wiring layer 5, and the caused stress of thermal expansion rate variance between semiconductor chip 1 and the base substrate 3 is very little.Therefore, shown in Fig. 2 A, in order to undertake the part of bond strength, to be the gap that sealing resins such as resin come landfill semiconductor chip 1 and circuit board 2 not necessarily with epoxy, but, in order to cut off with surrounding environment, also can be as required, shown in Fig. 2 B, in the scope that junction surface is not applied excessive stress, carry out resin-sealed with sealing resin 8 to the gap of semiconductor chip 1 and circuit board 2, also have, shown in Fig. 2 C, also can be resin-sealed to carrying out around the semiconductor chip 1 with 8 of sealing resins.
Secondly, describe the manufacture method of the circuit board 2 of the 1st execution mode in detail to Fig. 3 F with reference to Fig. 3 A.
As shown in Figure 3A, on the silicon wafer of base substrate 3, form silicon oxide film (SiO as insulating barrier 11a 2Film) after, makes the hole site form figure, make insulating barrier 11a opening, adopt active-ion-etch method (RIE) to form the non-through hole of the degree of depth 110 μ m again by the offset printing operation.In addition, as the aperture of non-through hole, the about 80 μ m of diameter, the about 150 μ m in the interval in hole.RIE is the method for removing oxide-film by the reaction of the activate atom in the reactant gas plasma, and is identical with the dry-etching method, can make it have anisotropic etching and remove effect.
Secondly, shown in Fig. 3 B, using plasma CVD method forms TEOS (Si (OC as insulating barrier 11b successively on the formation face of non-through hole 2H 5) 4) film, adopt sputtering method to form copper (Cu) film (not shown) of plating thin layer.The deep hole as this structure comprehensively on adopt the CVD method to carry out the occasion of film forming, be difficult to film forming according to its shape in the side, hole.Thereby selected the urgent TEOS film that begins to form the good film of spreadability after the film that is connected into as insulating barrier 11b.Secondly, adopt Damascus (ダ マ シ Application) method of plating, the Cu that is used as conductor 12 fills non-through hole, makes the flattening surface of conductor 12 by cmp (CMP).Except the method for Damascus, also can adopt the CVD method to come the filled conductive body, except metal material, electric conductor also can adopt electroconductive resin.
Secondly, shown in Fig. 3 C, adopt etching method to make the Cu film on the upper strata that CMP handled form figure, adopt and carry out repeatedly successively that interlayer dielectric 14 forms, via hole forms, scale removal is handled and connect up 13 forming and the deposition process that forms multiple wiring layer forms wiring layer 5.In addition, in Fig. 3 C, represented that wiring layer 5 is 3 layers a example, but, is not limited to 3 layers.
When wiring layer 5 forms, make function element such as capacitor, resistance, inductor and just can expect raising of high speed motion etc., for example can form as strong dielectric material the part of interlayer dielectric 14, the structure that sandwiches by power line in the wiring layer 5 and earth connection, the capacitor of interior dress parallel plate-type makes it work as decoupling capacitor.After this, cover the electrode 16a part in addition of the superiors' wiring, finish the outside structure that projection forms side that connects with solder resists such as polyimides 15.
Herein, function element such as capacitor, resistance, inductor in wiring layer 5, have been formed, but, also can on the silicon substrate that has formed the path of having filled electric conductor, use thin-film technique to form function element such as capacitor, owing to be on silicon, to form, thereby can continue to use former semiconductor diffusion technology, the precision height, and suppressed costs such as equipment investment, can cost degradation.
Secondly, shown in Fig. 3 D, before the thinning of silicon is handled,, wiring layer covers with support 17 for forming the top layer protection of side.Make the wafer counter-rotating,, the part of the silicon of about 700 μ m is thinned to after about 200 μ m, adopt RIE to be thinned to the about 100 μ m of thickness again, non-through hole is exposed by mechanical lapping.
In the 1st execution mode, consider production cost, production efficiency, adopt the combination of mechanical lapping and RIE method to carry out thinning.On the surface after the mechanical lapping, can form the layer of distortion usually, produce fine fisssure, become the reason of reliability deterioration, because this possibility is arranged, thereby need take into full account conditions such as the amount of removing that mechanical lapping causes and cutting speed with the difference of condition.Also have, reliability is not being brought the scope of influence, can adopt mechanical lapping to carry out thinning entirely.
Secondly, shown in Fig. 3 E, the face after RIE handles is at the through hole exposed division with beyond it, owing to the caused etching speed difference of material difference produces step.To this, the face that RIE has been handled adopts CMP to carry out planarization, removes insulating barrier 11b fully simultaneously, and copper exposed.On it, form the SiO of insulating barrier 11c 2Film adopts photoetching method to form figure.
At last shown in Fig. 3 F, after the peristome of insulating barrier 11c forms the 2nd electrode 16b, form the coverlay 18 of silicon nitride film (SiN film), peel off and remove support 17 and finish circuit board 2.In the 1st execution mode, insulating barrier 11a, 11b, 11c and coverlay 18 have adopted SiO 2, SiN, but, also can adopt SiC, SiOF, SiOC in the film-formable at a lower temperature plasma CVD method.
On the circuit board 2 of the wafer-like that adopts Fig. 3 A to make to the operation shown in Fig. 3 F, face down semiconductor chip 1 is installed, after having reinforced with suitable sealing resin 8, carry out singualtion, form the outside projection 7 that connects, make desired semiconductor device.In this technology, under wafer state, advance operation, up near finishing operation, thereby the production efficiency height, can cut down production, check cost.
Size at semiconductor chip 1 surpasses 10 * 10mm, and outside output subnumber surpasses the occasion of 1000 pins, and it is big that the size of circuit board 2 becomes, and has entered the maximization of so-called 40～50mm.In such occasion, be thinned manufactured silicon substrate and just can't keep intensity, might destroy circuit board 2 when carrying out singualtion, thereby preferably, after the connection electrode of the thinning processing of silicon, semiconductor chip forms, circuit board 2 is carried out before the singualtion operation that bonding girth member 9 cuts off after reinforcing.
Have again,, just can under the state of wafer, carry semiconductor chip 1, carry out singualtion if circuit board manufacturing and semiconductor-chip-mounting can carry out continuously.
Also have, in the present invention, insulating barrier is so long as to alleviate with motherboard substrate be that the material of thermal expansion difference of the support substrate of an example and circuit board is just passable.Preferably, consider that the coefficient of thermal expansion of support substrate and base substrate is selected, more preferably, the coefficient of thermal expansion of insulating barrier is littler than the coefficient of thermal expansion of support substrate, than the big material of the coefficient of thermal expansion of base substrate.
In the 1st execution mode, the base substrate 3 of semiconductor chip 1 and circuit board 2 has adopted silicon, but be not limited to silicon, the coefficient of thermal expansion that base substrate 3 can adopt coefficient of thermal expansion and semiconductor chip 1 quite or be the following material of the coefficient of thermal expansion of wiring layer 5, beyond the silica removal, for example, can adopt pottery maybe can form the photosensitive glass of minute aperture.In the occasion of photosensitive glass having been made base substrate 3, after beginning to have formed through hole rather than non-through hole, the conducting processing and the wiring layer that carry out the glass plate two sides form.Specifically be to place on the photosensitive glass, carry out the development that constitutes by exposure, heat treatment with ultraviolet ray with provision wavelengths composition having the mask that the hole forms figure, with sour remove crystallization part, make base substrate 3 with through hole.
(the 2nd execution mode)
Fig. 4 is the cutaway view of structure of the semiconductor device of expression the 2nd execution mode involved in the present invention.In the 2nd execution mode, except the formation of the 1st execution mode, the girth member 9 as stiffening frame is bonded to around semiconductor chip 1 installed surface of base substrate 3, improved the rigidity of circuit board 2.Because girth member 9 can improve the rigidity of circuit board 2, thereby can attenuate base substrate 3, facilitate the thinning of packaging part thickness, and can utilize girth member 9 that heating panel 10 is bonded in semiconductor chip 1 back side, suitably carry out the consumed power with semiconductor chip 1, the raising cooling property countermeasure that caloric value increases.In addition, the material of girth member 9 is also identical with base substrate 3, preferably, with the coefficient of thermal expansion of semiconductor chip 1 quite or be below the coefficient of thermal expansion of wiring layer 5.
(the 3rd execution mode)
Fig. 5 A is the cutaway view of the circuit board in each process chart relevant with the manufacture method of the wiring of semiconductor device substrate of the 3rd execution mode involved in the present invention to Fig. 5 E.
In the 1st execution mode, on base substrate 3, form non-through hole, with conductor 12 with its landfill after formed wiring layer 5, and in this 3rd execution mode, on base substrate 3, formed after the wiring layer 5 at first, carry out the formation of through hole and backplate, circuit board 2 is finished, this point difference.
At first shown in Fig. 5 A, on the silica-based plinth substrate 3 of the about 700 μ m of thickness, use manufacture method formation insulating barrier 11a, the wiring layer 5 same with the 1st execution mode.
With support 17 cover, protection wiring layer 5 surfaces, with its counter-rotating, from the back side base substrate 3 mechanical lappings behind the about 180 μ m of thickness, central portion is carried out RIE removes, to the about 80 μ m of thickness.Fig. 4 is an enlarged drawing, thereby not expression, but, when RIE removes, the width 8.5mm zone of substrate periphery portion is sheltered, and only further carries out thinning at middle section, makes it to have formed step.The further thickness of attenuate through hole formation portion and can keep the rigidity of base substrate 3 so just.In addition, the profile of circuit board 2 is a mouthful 30mm, and semiconductor chip 1 is about mouthful of 10mm of profile, the about 700 μ m of thickness.Also having, is the through hole formation portion of circuit board 2 and the formation that periphery is made of one with same material in this example, but, also can be as the 2nd execution mode, on level and smooth circuit board 2, keep rigidity by bonding girth member 9 on every side.
Secondly, shown in Fig. 5 B, on the silicon wafer of base substrate 3, form SiO as insulating barrier 11c 2Behind the film, make the hole form the position by photo-mask process and form figure, make insulating barrier 11c opening, adopt RIE to remove the formation through hole, wiring layer 5 undermost wirings are exposed.Secondly, make the side and the surface insulation of through hole with TEOS film as insulating barrier 11b.
After this, shown in Fig. 5 C, adopt Damascus method to fill Cu, make after the flattening surface, shown in Fig. 5 D, form electrode 16b, shown in Fig. 5 E, form SiN coverlay 18 for another example, thereby finish the circuit board 2 of wafer-like by CMP as conductor 12.
(the 4th execution mode)
Fig. 6 is the cutaway view of structure of the semiconductor device of expression the 4th execution mode involved in the present invention.Fig. 7 A is the cutaway view of the semiconductor device in the later assembly process of the flip-chip bond operation of semiconductor device of the 4th execution mode involved in the present invention to Fig. 7 D.
The 4th execution mode with reference to Fig. 6, is provided with step around base substrate 3, the attenuate central portion is installed semiconductor chip 1 by the flip-chip mode, to its carry out resin-sealed after, the back side is unified to grind, just finished thinning as whole semiconductor device.
At first, shown in Fig. 7 A, on the circuit board 2 of the wafer-like of bonding support 17, semiconductor chip 1 is installed by the flip-chip mode.Secondly, shown in Fig. 7 B, supply with sealing resin 8, in the gap of semiconductor chip 1 and base substrate 3, pour into sealing resin 8 and fill, and above sealing resin 8 covering fixing bodies.This damage when alleviating semiconductor chip 1 grinding back surface is carried out, and can suitably carry out the change of resin quantity delivered and the omission of operation in the no problem scope of junction surface and component reliability.
After this, shown in Fig. 7 C, be semiconductor chip 1 grinding back surface about 50 μ m to thickness, the semiconductor device thickness except that outside connection projection 7 is done into about 220 μ m.In addition, wiring layer 5 is made 2 layers of formation.Secondly, shown in Fig. 7 D, adopt scribing processing that wafer is carried out singualtion, peel off support 17.Adopt microballoon lift-launch method to form the outside projection 7 that connects at last, semiconductor device is just accused and is finished.The outside formation method that connects projection 7 also can adopt other methods such as soft solder cream print process, vapour deposition method, electrolysis plating method, and support is peeled off, the order of singualtion operation can be considered the projection method of formationing and productivity and suitably changing.
(the 5th execution mode)
After having formed through hole in the 1st execution mode on the base substrate that is made of silicon, form wiring layer, bonding support carries out attenuate processing from the back side to silicon, the lift-launch of semiconductor chip 1 is showed out, thereby formed circuit board 2.On silicon substrate, form wiring layer 5 in the 3rd execution mode, carry out attenuate processing, after this form through hole, form the lift-launch face of semiconductor chip 1, thereby formed circuit board 2 from its back side to silicon.
In which kind of occasion all is the lift-launch face of last processing semiconductor chip 1, but, in the 5th execution mode, on base substrate 2, adopt RIE to become the path of through hole, implement the dielectric film formation of inwall, the filling of electric conductor, the planarization that CMP carried out successively, be formed for carrying the pad of semiconductor chip 1.Afterwards this face is bonded on the support, appropriate combination is carried out in the mechanical lapping processing, the dry-etching processing that are used for carrying out from the back side silicon slimming, form through electrode.Afterwards, form multiple wiring layer, form outside terminal, make circuit board.According to this method, the electrode forming process of the lift-launch face of semiconductor chip 1, the operation that forms the precision of having relatively high expectations such as operation of function element such as capacitor in addition can be utilized the technology of the diffusing procedure of semiconductor manufacturing before forming support and multiple wiring layer, this is the advantage that is had.
In these execution modes, made 80 μ m connecting path, but, the perforate operation during for the formation path, the heavy caliber of the degree of 150 μ m also is possible.Also will be according to the arrangement pitch of electrode, but, from the viewpoint of densification, preferably the little side of passage diameters adopts below the 50 μ m.By the method that the selection path forms, can be implemented into the degree of 10 μ m.
Consider that also unify to process the occasion of implementing to make the operation that path exposes at the electric conductor of having filled in to silicon and path by the mechanical lapping of silicon, electric conductor stops up the pore of grinding tool easily, it is coarse that machined surface will become, rate of finished products is reduced.Therefore, preferably, path is being below 2% on the area with respect to the silicon wafer of processing, on 8 inches wafers, get the occasion of design of the substrate of 60 4000 pins, the diameter that connects path is the most suitable below the 30 μ m, from the viewpoint of the operation of filled conductive material path, the words of paying attention to fillibility are preferably more than the 10 μ m.
As described above, according to present embodiment, the base substrate 3 of the circuit board 2 of the characteristic that semiconductor chip 1 is close with having coefficient of thermal expansion is connected, thereby the caused internal stress of coefficient of thermal expansion mismatch is greatly reduced, have again, semiconductor device also is lowered to the variation of the installation of motherboard and the caused internal stress of variations in temperature under the environment for use, thereby can improve reliability, can overcome the maximization of the semiconductor chip 1 of following the outside terminal increase from now on, interlayer dielectric adopts fragile Low-k film, the permissible level of the internal stresss such as stress relieve minimizing of the unleaded caused soft solder of soft solder of environment correspondence reduces, and this is the effect that is had.
Have again, according to present embodiment, in the formation of the wiring layer 5 of circuit board 2, owing on the high base substrate 3 of rigidity, form, thereby fine wiring pattern shape is formed is favourable, and roughly all semiconductor device manufacturing processes can handle under wafer-level, thereby can enhance productivity, cut down manufacturing cost, and this is the effect that is had.
Have again, according to present embodiment, owing to producing stress at the employed resin material of interlayer dielectric of the most of volume that accounts for the wiring layer 5 that forms at the back side of the chip installed surface of circuit board 2 and the thermal expansion rate variance between the base substrate, but, because bonding stiffening frame the whole of the peripheral part of the loading position of the semiconductor chip 1 of chip installed surface or its are a part of, thereby in the occasion of doing the loading position of the semiconductor chip 1 of base substrate 3 extremely thinly, the rigidity that also can keep base substrate 3, the result just can suppress the warpage of circuit board 2, improve installation property, reliability, this is the effect that is had.
Have again, according to present embodiment, owing to producing stress at the employed resin material of interlayer dielectric of the most of volume that accounts for the wiring layer 5 that forms at the back side of the chip installed surface of circuit board 2 and the thermal expansion rate variance between the base substrate 3, but, since thickeied the chip installed surface semiconductor chip 1 loading position peripheral part whole or it is a part of, thereby in the occasion of doing the loading position of the semiconductor chip 1 of base substrate 3 extremely thinly, the rigidity that also can keep base substrate 3, the result just can suppress the warpage of circuit board, improve installation property, reliability, and base substrate 3 is being carried out the also formation in the lump of step that attenuate adds the periphery in man-hour, thereby can simplify technology, cutting down cost, this is the effect that is had.
Have again, according to present embodiment, owing to made on the wiring layer formation face of base substrate 3 or formed the formation of function element such as capacitor, resistance, inductor on the wiring layer 5, thereby can improve high frequency characteristics or realize multifunction by function element such as optimal position configuration capacitor, resistance, inductor in wiring layer 5, can also reduce erection space, improve design freedom, this is the effect that is had.
Have, according to present embodiment, stacked wiring layer 5 on the base substrate 3 little at coefficient of thermal expansion, that rigidity is high is compared with the occasion of stacked wiring layer 5 on the resin system base material, can form finer wiring figure again, and this is the effect that is had.
In addition, the present invention is not limited to the respective embodiments described above, and in the scope of technological thought of the present invention, each execution mode can suitably change, and this is tangible.Also have, the quantity of above-mentioned component parts, position, shape etc. are not limited to the respective embodiments described above, can select suitable quantity, position, shape etc. on basis of the present invention.In addition, in each figure, identical constitutive requirements have been paid same-sign.
Industrial applicibility
Circuit board of using in semiconductor device involved in the present invention, the semiconductor device and circuit board manufacture method, so long as the semiconductor device of semiconductor chip is installed by the flip-chip mode on circuit board, can be suitable for for all devices, for the possibility of its utilization without any restriction.
More than with regard to several suitable execution modes and embodiment the present invention has been described, but, be appreciated that these execution modes and embodiment just are used for illustrative example invention is described, and do not mean that it is limited.Read after this specification, for a person skilled in the art, derived numerous variations and displacement is easy by the constitutive requirements of equivalence and technology, this is tangible, but, such change and displacement belong to the real scope and spirit of additional claim item, and this is tangible.

Claims (22)

1. a semiconductor device is the semiconductor device that semiconductor chip has been installed by the flip-chip mode on circuit board, and described circuit board comprises:
Base substrate;
Have the interlayer dielectric that on the wiring layer formation face of the one side of this base substrate, forms and the wiring layer of wiring;
Form the 1st electrode that forms on the chip installed surface at the back side of face at described wiring layer as the described base substrate of carrying described semiconductor chip;
Be filled in the conductor inside of the through hole that forms on the described base substrate; And
The 2nd electrode that on the back side of the face that joins with described base substrate of described wiring layer, forms,
Described conductor is electrically connected described the 1st electrode that directly is formed at the described wiring layer on the described wiring layer formation face and be formed on the described chip installed surface,
The coefficient of thermal expansion of described base substrate is suitable with described semiconductor chip, or is below the coefficient of thermal expansion of described wiring layer,
Described semiconductor chip faces down and is connected on the described chip installed surface.
2. semiconductor device according to claim 1, wherein, the material of described base substrate is made of in silicon, pottery and the photosensitive glass any one.
3. semiconductor device according to claim 1, wherein, bonding stiffening frame at least a portion of the peripheral part of the loading position of the described semiconductor chip of described chip installed surface.
4. semiconductor device according to claim 3, wherein, the coefficient of thermal expansion and the semiconductor chip of described stiffening frame are suitable, or are below the coefficient of thermal expansion of wiring layer.
5. semiconductor device according to claim 1, wherein, the thickness of described base substrate is that at least a portion of the peripheral part of the described semiconductor-chip-mounting position of described chip installed surface is thicker than the loading position of the described semiconductor chip of described chip installed surface.
6. semiconductor device according to claim 1 wherein, has formed function element at least 1 side in described wiring layer formation face and described wiring layer.
7. semiconductor device according to claim 1, wherein, the coefficient of thermal expansion of described semiconductor chip is lower than the coefficient of thermal expansion of described wiring layer.
8. semiconductor device according to claim 1, wherein, the electrode that formed on the semiconductor chip by the correspondence that on described single substrate, formed through hole and be electrically connected with described wiring layer.
9. a circuit board is the circuit board that semiconductor chip is installed by the flip-chip mode, comprising:
Base substrate;
Have the interlayer dielectric that on the wiring layer formation face of the one side of this base substrate, forms and the wiring layer of wiring;
Form the 1st electrode that forms on the chip installed surface at the back side of face at described wiring layer as the described base substrate of carrying described semiconductor chip;
Be filled in the conductor inside of the through hole that forms on the described base substrate; And
The 2nd electrode that on the back side of the face that joins with described base substrate of described wiring layer, forms,
Described conductor is electrically connected described the 1st electrode that directly is formed at the described wiring layer on the described wiring layer formation face and be formed on the described chip installed surface,
The coefficient of thermal expansion of described base substrate is suitable with described semiconductor chip, or is below the coefficient of thermal expansion of described wiring layer.
10. circuit board according to claim 9, wherein, the material of described base substrate is made of in silicon, pottery and the photosensitive glass any one.
11. circuit board according to claim 9, wherein, bonding stiffening frame at least a portion of the peripheral part of the loading position of the described semiconductor chip of described chip installed surface.
12. circuit board according to claim 11, wherein, the coefficient of thermal expansion and the semiconductor chip of described stiffening frame are suitable, or are below the coefficient of thermal expansion of wiring layer.
13. circuit board according to claim 9, wherein, the thickness of described base substrate is that at least a portion of the peripheral part of the described semiconductor-chip-mounting position of described chip installed surface is thicker than the loading position of the described semiconductor chip of described chip installed surface.
14. circuit board according to claim 9 wherein, has formed function element at least 1 side in described wiring layer formation face and described wiring layer.
15. circuit board according to claim 9, wherein, the coefficient of thermal expansion of described semiconductor chip is lower than the coefficient of thermal expansion of described wiring layer.
16. circuit board according to claim 9, wherein, the electrode that formed on the semiconductor chip by the correspondence that on described single substrate, formed through hole and be electrically connected with described wiring layer.
17. circuit board manufacture method of making circuit board, described circuit board is by base substrate and have that wiring layer in the one side of this base substrate forms the interlayer dielectric that forms on the face and the wiring layer of wiring constitutes, by the flip-chip mode semiconductor chip is installed, described circuit board manufacture method comprises: form the operation that the face side forms non-through hole from the described wiring layer of described base substrate; With the described non-through hole of conductive material landfill, on described wiring layer formation face, form the operation of the 1st electrode; On described wiring layer formation face, directly form the operation of described wiring layer; And form the described base substrate of thinning back side of face from described wiring layer, and described non-through hole is exposed, form the operation of the 2nd electrode that carries described semiconductor chip.
18. circuit board manufacture method according to claim 17, wherein, the processing capacity of at least a portion that also comprises the peripheral part of the loading position that makes described semiconductor chip lacks than the processing capacity of the loading position of described semiconductor chip, forms step and the operation of the described base substrate of attenuate in the described at least a portion of the peripheral part of the loading position of described semiconductor chip and the described loading position of described semiconductor chip.
19. circuit board manufacture method according to claim 17 wherein, in the operation that forms described wiring layer, also forms function element.
20. circuit board manufacture method of making circuit board, described circuit board is by base substrate and form the wiring layer that forms on the face at the wiring layer of the one side of this base substrate and constitute, by the flip-chip mode semiconductor chip is installed, described circuit board manufacture method comprises: the operation that directly forms wiring layer on the described wiring layer formation face of described base substrate; Form the operation of the through hole that only connects described base substrate from the rear side of described wiring layer formation face; And with the described through hole of conductive material landfill, form the operation of the electrode that carries described semiconductor chip at the back side that described wiring layer forms face.
21. circuit board manufacture method according to claim 20, wherein, the processing capacity of at least a portion that also comprises the peripheral part of the loading position that makes described semiconductor chip lacks than the processing capacity of the loading position of described semiconductor chip, forms step and the operation of the described base substrate of attenuate in the described at least a portion of the peripheral part of the loading position of described semiconductor chip and the described loading position of described semiconductor chip.
22. circuit board manufacture method according to claim 20 wherein, in the operation that forms described wiring layer, also forms function element.
CNB2003801038650A 2002-11-21 2003-11-21 Semiconductor device, wiring substrate, and method for manufacturing wiring substrate Expired - Lifetime CN100377337C (en)

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Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4865197B2 (en) * 2004-06-30 2012-02-01 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
JP4343044B2 (en) * 2004-06-30 2009-10-14 新光電気工業株式会社 Interposer, manufacturing method thereof, and semiconductor device
DE102006001600B3 (en) * 2006-01-11 2007-08-02 Infineon Technologies Ag Semiconductor component with flip-chip contacts, has flip-chip contacts arranged on contact surfaces of upper metallization layer
US20070246821A1 (en) * 2006-04-20 2007-10-25 Lu Szu W Utra-thin substrate package technology
US7804177B2 (en) * 2006-07-26 2010-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Silicon-based thin substrate and packaging schemes
US8168537B2 (en) * 2006-08-17 2012-05-01 Nxp B.V. Semiconductor component and assumbly with projecting electrode
JP4946262B2 (en) 2006-08-18 2012-06-06 富士通セミコンダクター株式会社 Semiconductor element mounting method and semiconductor device manufacturing method
JP5042591B2 (en) * 2006-10-27 2012-10-03 新光電気工業株式会社 Semiconductor package and stacked semiconductor package
US8030768B2 (en) * 2007-04-24 2011-10-04 United Test And Assembly Center Ltd. Semiconductor package with under bump metallization aligned with open vias
JP2008305833A (en) * 2007-06-05 2008-12-18 Disco Abrasive Syst Ltd Wafer processing method
US7939941B2 (en) * 2007-06-27 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of through via before contact processing
JP4917979B2 (en) * 2007-07-09 2012-04-18 半導体特許株式会社 Semiconductor device and manufacturing method thereof
US8350382B2 (en) * 2007-09-21 2013-01-08 Infineon Technologies Ag Semiconductor device including electronic component coupled to a backside of a chip
US20090135157A1 (en) * 2007-11-27 2009-05-28 Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. Capacitive Sensing Input Device with Reduced Sensitivity to Humidity and Condensation
US8853830B2 (en) 2008-05-14 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. System, structure, and method of manufacturing a semiconductor substrate stack
JP5471268B2 (en) * 2008-12-26 2014-04-16 大日本印刷株式会社 Through electrode substrate and manufacturing method thereof
JP4900508B2 (en) * 2008-12-26 2012-03-21 大日本印刷株式会社 Through electrode substrate and manufacturing method thereof
US8691664B2 (en) * 2009-04-20 2014-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Backside process for a substrate
US7936060B2 (en) * 2009-04-29 2011-05-03 International Business Machines Corporation Reworkable electronic device assembly and method
JP5532744B2 (en) * 2009-08-20 2014-06-25 富士通株式会社 Multi-chip module and method for manufacturing multi-chip module
EP2339627A1 (en) * 2009-12-24 2011-06-29 Imec Window interposed die packaging
TWI419302B (en) * 2010-02-11 2013-12-11 Advanced Semiconductor Eng Package process
CN102194706B (en) * 2010-03-02 2013-08-21 日月光半导体制造股份有限公司 Encapsulation process
US9236278B2 (en) * 2011-09-23 2016-01-12 Stats Chippac Ltd. Integrated circuit packaging system with a substrate embedded dummy-die paddle and method of manufacture thereof
JP5333572B2 (en) * 2011-12-22 2013-11-06 富士通セミコンダクター株式会社 Semiconductor element mounting method and semiconductor device manufacturing method
JP5474127B2 (en) * 2012-05-14 2014-04-16 株式会社野田スクリーン Semiconductor device
CN102800647A (en) * 2012-08-22 2012-11-28 上海宏力半导体制造有限公司 Three-dimensional spiral inductor and forming method thereof
JP2014204004A (en) * 2013-04-05 2014-10-27 Hoya株式会社 Substrate assembly, method of manufacturing substrate assembly, and method of manufacturing chip package
KR101468680B1 (en) * 2013-05-09 2014-12-04 (주)옵토레인 Method for manufacturing through via of interposer and semiconductor package comprising interposer
US9466578B2 (en) 2013-12-20 2016-10-11 Qualcomm Incorporated Substrate comprising improved via pad placement in bump area
KR20150120570A (en) * 2014-04-17 2015-10-28 에스케이하이닉스 주식회사 Semiconductor package and the method for manufacturing of the same
KR20170001060A (en) * 2015-06-25 2017-01-04 에스케이하이닉스 주식회사 Semiconductor package including interposer and manufacturing method for the same
US10340444B2 (en) * 2016-12-28 2019-07-02 Rohm Co., Ltd. Semiconductor element with hall element and sealing resin
US10510603B2 (en) * 2017-08-31 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive vias in semiconductor packages and methods of forming same
JP6446155B1 (en) * 2018-07-17 2018-12-26 株式会社日立パワーソリューションズ Double-sided circuit non-oxide ceramic substrate and manufacturing method thereof
CN109599378A (en) * 2018-12-21 2019-04-09 华进半导体封装先导技术研发中心有限公司 A kind of encapsulating structure and preparation method of chip
CN112309993A (en) * 2020-02-17 2021-02-02 成都华微电子科技有限公司 Packaging structure based on silicon-based packaging substrate
JP7322838B2 (en) 2020-09-03 2023-08-08 株式会社村田製作所 Electronic components and electronic component modules

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08330506A (en) * 1995-06-02 1996-12-13 Tokuyama Corp Circuit board structure
JPH10209216A (en) * 1997-01-24 1998-08-07 Matsushita Electric Ind Co Ltd Chip size package and its production
CN1297253A (en) * 1999-10-05 2001-05-30 日本电气株式会社 Wiring baseboard, semiconductor device with wiring baseboard, and mfg. and installing method thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590349A (en) * 1991-02-07 1993-04-09 Nitto Denko Corp Film with electrode, film carrier, and semiconductor device using them
JPH0864711A (en) * 1994-08-25 1996-03-08 Toshiba Corp Semiconductor package
US5525834A (en) * 1994-10-17 1996-06-11 W. L. Gore & Associates, Inc. Integrated circuit package
JP3683996B2 (en) * 1996-07-30 2005-08-17 株式会社東芝 Semiconductor device and manufacturing method thereof
US5919329A (en) * 1997-10-14 1999-07-06 Gore Enterprise Holdings, Inc. Method for assembling an integrated circuit chip package having at least one semiconductor device
US6316289B1 (en) * 1998-11-12 2001-11-13 Amerasia International Technology Inc. Method of forming fine-pitch interconnections employing a standoff mask

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08330506A (en) * 1995-06-02 1996-12-13 Tokuyama Corp Circuit board structure
JPH10209216A (en) * 1997-01-24 1998-08-07 Matsushita Electric Ind Co Ltd Chip size package and its production
CN1297253A (en) * 1999-10-05 2001-05-30 日本电气株式会社 Wiring baseboard, semiconductor device with wiring baseboard, and mfg. and installing method thereof

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US7728439B2 (en) 2010-06-01

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