JP5333572B2 - Semiconductor element mounting method and semiconductor device manufacturing method - Google Patents

Semiconductor element mounting method and semiconductor device manufacturing method Download PDF

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JP5333572B2
JP5333572B2 JP2011282115A JP2011282115A JP5333572B2 JP 5333572 B2 JP5333572 B2 JP 5333572B2 JP 2011282115 A JP2011282115 A JP 2011282115A JP 2011282115 A JP2011282115 A JP 2011282115A JP 5333572 B2 JP5333572 B2 JP 5333572B2
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semiconductor element
temperature
mounting
solder
wiring board
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JP2012060185A (en
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城次 藤森
誠樹 作山
俊也 赤松
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Fujitsu Semiconductor Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for mounting a semiconductor element on a wiring substrate through a protrusion electrode for an external connection not containing lead (Pb), and for mitigating stress acting on a wiring layer laminated through an interlayer insulating film composed of a Low-K material in the semiconductor element from the wiring substrate during such mounting, thereby an occurrence of an interlayer detachment may be suppressed. <P>SOLUTION: In a method for mounting a semiconductor element 10 on a wiring substrate 20 through a protrusion electrode 9 for an external connection, after a reflow heating process is performed for connecting the protrusion electrode 9 for the external connection of the semiconductor element 10 with the wiring substrate 20, the connected semiconductor element 10 and the wiring substrate 20 are cooled at a cooling rate of about 0.5&deg;C/sec or less. <P>COPYRIGHT: (C)2012,JPO&amp;INPIT

Description

本発明は、半導体素子の実装方法及び半導体装置の製造方法に関し、より具体的には、鉛（Ｐｂ）を含有しない外部接続用突起電極を介して半導体素子を配線基板に実装する方法に関する。   The present invention relates to a method for mounting a semiconductor element and a method for manufacturing a semiconductor device, and more specifically, to a method for mounting a semiconductor element on a wiring board via an external connection protruding electrode that does not contain lead (Pb).

従前より、鉛（Ｐｂ）を含有しない、所謂鉛フリーの半田バンプと称される外部接続用突起電極を介して、半導体素子を配線基板にフェイスダウンでフリップチップ実装してなる半導体装置が知られている。   2. Description of the Related Art Conventionally, there has been known a semiconductor device in which a semiconductor element is flip-chip mounted on a wiring board face-down through an external connection protruding electrode called a so-called lead-free solder bump that does not contain lead (Pb). ing.

このような半導体装置に適用される半導体素子の断面を図１に示し、また、当該図１において点線で囲まれた部分を拡大して図２に示す。   A cross section of a semiconductor element applied to such a semiconductor device is shown in FIG. 1, and a portion surrounded by a dotted line in FIG. 1 is enlarged and shown in FIG.

図１及び図２を参照するに、半導体素子にあっては、シリコン（Ｓｉ）からなる半導体基板１に所謂ウエハープロセスが適用されて、その一方の主面にトランジスタなどの能動素子、及び容量素子などの受動素子が形成され（図示せず）、更に当該半導体基板１の一方の主面上に、酸化シリコン（ＳｉＯ２）層２等の絶縁層を介して多層配線層３が配設されている。 Referring to FIGS. 1 and 2, in a semiconductor element, a so-called wafer process is applied to a semiconductor substrate 1 made of silicon (Si), and an active element such as a transistor and a capacitive element are provided on one main surface thereof. And a multilayer wiring layer 3 is disposed on one main surface of the semiconductor substrate 1 via an insulating layer such as a silicon oxide (SiO 2 ) layer 2. Yes.

かかる多層配線層３は、図２に示すように、アルミニウム（Ａｌ）又は銅（Ｃｕ）等からなる配線層４が層間絶縁膜５を介して複数層積層されて形成されている。そして層間接続部を介して上下の配線層４間が適宜接続されている。   As shown in FIG. 2, the multilayer wiring layer 3 is formed by laminating a plurality of wiring layers 4 made of aluminum (Al), copper (Cu), or the like with an interlayer insulating film 5 interposed therebetween. The upper and lower wiring layers 4 are appropriately connected through interlayer connection portions.

前記層間絶縁膜５を構成する材料としては、例えば、有機樹脂、炭素を添加した酸化シリコン（ＳｉＯＣ）、或いはフッ素がドープされたシリコンガラス（ＦＳＧ：Ｆｌｕｏｒｉｎｅ ｄｏｐｅｄ Ｓｉｌｉｃｏｎ Ｇｌａｓｓ）等の誘電率の低い材料（所謂Ｌｏｗ−Ｋ材料）が用いられ、配線間に形成される電気容量を低減し、電気信号の伝達の高速化が図られる。   Examples of the material constituting the interlayer insulating film 5 include a material having a low dielectric constant, such as organic resin, silicon oxide (SiOC) doped with carbon, or silicon glass doped with fluorine (FSG: Fluorine doped Silicon Glass). (A so-called Low-K material) is used, and the electric capacity formed between the wirings can be reduced, and the transmission of electric signals can be speeded up.

半導体基板１に形成された能動素子、受動素子等の機能素子は、当該多層配線層３を介して相互に接続され、所望の機能を有する電子回路が形成される。   Functional elements such as active elements and passive elements formed on the semiconductor substrate 1 are connected to each other via the multilayer wiring layer 3 to form an electronic circuit having a desired function.

当該多層配線層３の上部には、アルミニウム（Ａｌ）からなる電極パッド１１が複数個選択的に配設され、多層配線層３を構成する配線４と適宜接続されている。   A plurality of electrode pads 11 made of aluminum (Al) are selectively disposed above the multilayer wiring layer 3 and are appropriately connected to the wiring 4 constituting the multilayer wiring layer 3.

また当該多層配線層３上には、前記電極パッド１１の中央部を表出するよう選択的に開口を有して、例えば酸化シリコン（ＳｉＯ２）或いは窒化シリコン（ＳｉＮ）等の無機絶縁材料からなるパッシベーション層６が選択的に配設されている。 In addition, an opening is selectively formed on the multilayer wiring layer 3 so as to expose the central portion of the electrode pad 11, and for example, an inorganic insulating material such as silicon oxide (SiO 2 ) or silicon nitride (SiN) is used. A passivation layer 6 is selectively provided.

更に、半導体素子の表面の保護を図るべく、前記無機絶縁層６の上面及び電極パッド１１の上に於ける無機絶縁層６の端面を覆って有機絶縁膜７が配設されている。   Further, in order to protect the surface of the semiconductor element, an organic insulating film 7 is disposed so as to cover the upper surface of the inorganic insulating layer 6 and the end surface of the inorganic insulating layer 6 on the electrode pad 11.

当該有機絶縁膜７の材料は、例えば、ポリイミド、ベンゾシクロブテン、フェノール樹脂、又はポリベンゾオキサゾール等の有機絶縁性材料から選択される。   The material of the organic insulating film 7 is selected from organic insulating materials such as polyimide, benzocyclobutene, phenol resin, or polybenzoxazole.

電極パッド１１の上面であって、無機絶縁層６及び有機絶縁膜７が設けられていない箇所から鉛直方向に、例えば、チタン（Ｔｉ）／銅（Ｃｕ）から成るバンプ下地金属（ＵＢＭ：Ｕｎｄｅｒ−Ｂｕｍｐ Ｍｅｔａｌｌｉｚａｔｉｏｎ）８が、有機絶縁膜７の上面よりも僅かに上方に至るまで、当該有機絶縁膜７の端面を覆って配設されている。   A bump base metal (UBM: Under-) made of, for example, titanium (Ti) / copper (Cu) in a vertical direction from a position on the upper surface of the electrode pad 11 where the inorganic insulating layer 6 and the organic insulating film 7 are not provided. A bump metallization 8 is provided so as to cover the end surface of the organic insulating film 7 until it is slightly above the upper surface of the organic insulating film 7.

バンプ下地金属８の上面には、略球状の外部接続用突起電極９が配設されている。当該外部接続用突起電極９は、錫（Ｓｎ）−銀（Ａｇ）、又は銅（Ｃｕ）を含む錫（Ｓｎ）−銀（Ａｇ）等、鉛（Ｐｂ）を含有しない半田から構成され、半田バンプとも称される。   On the upper surface of the bump base metal 8, a substantially spherical external connection protruding electrode 9 is provided. The external connection protruding electrode 9 is composed of a solder not containing lead (Pb), such as tin (Sn) -silver (Ag) or tin (Sn) -silver (Ag) containing copper (Cu). Also called a bump.

上述の構造を有する半導体素子１０を配線基板にフリップチップ実装した状態を図３に示す。   FIG. 3 shows a state where the semiconductor element 10 having the above structure is flip-chip mounted on a wiring board.

図３を参照するに、半導体素子１０は、配線基板２０に対しフェイスダウンでフリップチップ方式にて実装されている。   Referring to FIG. 3, the semiconductor element 10 is mounted on the wiring board 20 by face-down flip-chip method.

配線基板２０は、ガラスエポキシ材，ポリイミドテープ等から成る有機ビルドアップ基板である。配線基板２０の上面には、電極パッド２１が複数個選択的に配設され、当該電極パッド２１の中央部を表出するよう選択的に開口を有するソルダーレジスト２２が配設されている。   The wiring board 20 is an organic build-up board made of glass epoxy material, polyimide tape or the like. A plurality of electrode pads 21 are selectively disposed on the upper surface of the wiring board 20, and a solder resist 22 having an opening is selectively disposed so as to expose the central portion of the electrode pad 21.

配線基板２０上に配設された電極パッド２１に対して半導体素子１０の外部接続用突起電極９が接続されている。また、半導体素子１０と配線基板２０との間には、所謂アンダーフィル材２３が配設されている。配線基板２０の下面には、半田から成る外部接続用突起電極２４が配設されている。   The external connection protruding electrode 9 of the semiconductor element 10 is connected to the electrode pad 21 disposed on the wiring board 20. A so-called underfill material 23 is disposed between the semiconductor element 10 and the wiring board 20. An external connection protruding electrode 24 made of solder is disposed on the lower surface of the wiring board 20.

このような構造を有する半導体装置は、以下の工程を経て完成される。   A semiconductor device having such a structure is completed through the following steps.

即ち、半導体素子１０を配線基板２０に対しフリップチップ（フェイスダウン）方式にて搭載した後に、リフロー加熱処理により、外部接続用突起電極９と予め配線基板２０の電極パッド２１上に設けられ鉛（Ｐｂ）を含有しない予備半田（半田プリコート・図示を省略）とを溶融して、半導体素子１０の外部接続用突起電極９と配線基板２０とを接続する。   That is, after the semiconductor element 10 is mounted on the wiring substrate 20 by a flip chip (face-down) method, lead (which is provided on the external connection protrusion electrode 9 and the electrode pad 21 of the wiring substrate 20 in advance by reflow heat treatment) Preliminary solder (solder precoat, not shown) not containing Pb) is melted to connect the external connection protruding electrode 9 of the semiconductor element 10 and the wiring board 20.

しかる後、半導体素子１０と配線基板２０との間にアンダーフィル材２３を充填し、硬化せしめる。   Thereafter, an underfill material 23 is filled between the semiconductor element 10 and the wiring board 20 and cured.

最後に、配線基板２０の下面に半田ボールを搭載し、リフロー加熱工程及び冷却工程を経て、外部接続用突起電極２４を接続する。   Finally, solder balls are mounted on the lower surface of the wiring board 20 and the external connection protruding electrodes 24 are connected through a reflow heating process and a cooling process.

なお、下地金属上の錫（Ｓｎ）めっき皮膜を室温で酸化又は水酸化処理して、錫めっき皮膜表面に酸化物又は水酸化物の表面層を形成して、錫ウイスカの成長を抑制する電子部品が提案されている（例えば、特許文献１参照。）。   In addition, the tin (Sn) plating film on the base metal is oxidized or hydroxylated at room temperature to form an oxide or hydroxide surface layer on the surface of the tin plating film, thereby suppressing the growth of tin whiskers. Parts have been proposed (see, for example, Patent Document 1).

また、ビスマス（Ｂｉ）を含有する鉛（Ｐｂ）フリーはんだを用いて電子部品と回路基板とを接続する電子回路基板の製造方法であって、はんだを約１０〜２０℃／秒の冷却速度で冷却して電子部品と該回路基板と接続する電子回路基板の製造方法が提案されている（例えば、特許文献２参照。）。   The present invention also relates to a method of manufacturing an electronic circuit board that connects an electronic component and a circuit board using lead (Pb) -free solder containing bismuth (Bi), the solder being cooled at a cooling rate of about 10 to 20 ° C./second. An electronic circuit board manufacturing method that cools and connects an electronic component and the circuit board has been proposed (see, for example, Patent Document 2).

更に、半導体チップがフリップチップ実装される配線基板のベース基板の配線層形成面に形成された配線層とチップ装着面に形成された電極とを電気的に接続する貫通孔が当該配線基板に設けられ、前記ベース基板の熱膨張率が、半導体チップと同等又は配線層の熱膨張率以下である半導体装置が提案されている（例えば、特許文献３参照。）。   Furthermore, a through hole is provided in the wiring substrate for electrically connecting the wiring layer formed on the wiring layer forming surface of the base substrate of the wiring substrate on which the semiconductor chip is flip-chip mounted and the electrode formed on the chip mounting surface. There has been proposed a semiconductor device in which the thermal expansion coefficient of the base substrate is equal to or lower than that of the semiconductor chip (for example, see Patent Document 3).

特開２００６−１１１８９８号公報JP 2006-111898 A 特開平１１−３５４９１９号公報Japanese Patent Laid-Open No. 11-354919 国際公開第２００４／０４７１６７号パンフレットInternational Publication No. 2004/047167 Pamphlet

前述の如く、鉛（Ｐｂ）を含有しない外部続用突起電極９を介して、半導体素子１０を配線基板２０にフリップチップ実装する半導体装置の製造にあっては、リフロー加熱工程により、外部接続用突起電極９及び予め配線基板２０の電極パッド２１上に設けられ鉛（Ｐｂ）を含有しない予備半田（半田プリコート・図示を省略）を溶融して、半導体素子１０の外部接続用突起電極９と配線基板２０とを接続し、しかる後冷却し固化している。   As described above, in the manufacture of a semiconductor device in which the semiconductor element 10 is flip-chip mounted on the wiring board 20 via the external connection protruding electrode 9 that does not contain lead (Pb), a reflow heating process is used for external connection. Preliminary solder (solder precoat, not shown) provided on the electrode pads 21 and the electrode pads 21 of the wiring board 20 in advance and not containing lead (Pb) is melted, and the external connection protruding electrodes 9 of the semiconductor element 10 and the wiring The substrate 20 is connected and then cooled and solidified.

当該半導体素子１０に於けるシリコン基板の熱膨張係数は約３乃至４ｐｐｍ／℃であり、一方有機材料基板からなる配線基板２０の熱膨張係数は約１０乃至１７ｐｐｍ／℃であって、配線基板２０の熱膨張係数は半導体素子１０の熱膨張係数よりも大きい。   The thermal expansion coefficient of the silicon substrate in the semiconductor element 10 is about 3 to 4 ppm / ° C., while the thermal expansion coefficient of the wiring substrate 20 made of an organic material substrate is about 10 to 17 ppm / ° C. Is larger than the thermal expansion coefficient of the semiconductor element 10.

また、外部接続用突起電極９及び前記予備半田は、鉛（Ｐｂ）を含有しない半田から構成されるが、例えば、錫（Ｓｎ）−銀（Ａｇ）からなる半田、或いは錫（Ｓｎ）−銀（Ａｇ）−銅（Ｃｕ）からなる半田から構成される場合、当該半田の融点は２１７〜２２０℃である。   The external connection protruding electrode 9 and the preliminary solder are composed of solder not containing lead (Pb). For example, solder composed of tin (Sn) -silver (Ag), or tin (Sn) -silver. In the case where the solder is made of (Ag) -copper (Cu), the melting point of the solder is 217 to 220 ° C.

従って、当該半田が融点以上の温度例えば２５０℃に加熱されている状態では、当該半田は溶融しているため、当該半田は半導体素子１０或いは配線基板２０の熱膨張に伴う変形に追従することができる。   Therefore, in a state where the solder is heated to a temperature equal to or higher than the melting point, for example, 250 ° C., the solder is melted, so that the solder can follow the deformation accompanying the thermal expansion of the semiconductor element 10 or the wiring board 20. it can.

リフロー加熱工程に於いては、半導体素子１０が載置された配線基板２０は、それぞれヒータが設けられ直列状に配設された複数個の加熱領域（ブロック）を具備するリフロー処理装置内を移動して処理されるが、その際リフロー装置内の加熱領域毎のヒータの温度が制御されて、加熱処理並びに降温・冷却処理がなされる。   In the reflow heating process, the wiring board 20 on which the semiconductor element 10 is mounted moves in a reflow processing apparatus including a plurality of heating regions (blocks) each provided with a heater and arranged in series. At that time, the temperature of the heater for each heating region in the reflow apparatus is controlled, and the heating process and the temperature lowering / cooling process are performed.

図４は、かかるリフロー処理装置に於いて実施されるところの、半導体素子１０の外部接続用突起電極９と配線基板２０との接続のためのリフロー加熱工程、及び当該リフロー加熱工程後の降温・冷却工程を示す。横軸は時間（秒）を、縦軸は温度（℃）を示す。   FIG. 4 shows a reflow heating process for connection between the external connection protruding electrode 9 of the semiconductor element 10 and the wiring substrate 20, and a temperature drop and temperature drop after the reflow heating process, which are performed in such a reflow processing apparatus. A cooling process is shown. The horizontal axis represents time (seconds), and the vertical axis represents temperature (° C.).

即ち、リフロー加熱工程にあっては、１５０℃程に加熱された状態で所定時間保持し、フラックスを活性化して外部接続用突起電極９及び予備半田（半田プリコート）の表面に於ける酸化膜を除去し、しかる後半田の融点以上の温度例えば２５０℃迄昇温・加熱する。   That is, in the reflow heating process, the oxide film on the surface of the external connection protrusion electrode 9 and the preliminary solder (solder precoat) is activated by holding the flux in a heated state at about 150 ° C. for a predetermined time and activating the flux. Then, the temperature is raised and heated to a temperature equal to or higher than the melting point of the solder, for example, 250 ° C.

半田の溶融後、加熱を停止或いは加熱温度を低下させて、当該半田の融点（２１７〜２２０℃）以下の温度とし、半田を固化せしめる。当該半田が固化した後、半田の融点から常温近傍の温度まで漸次冷却（徐冷）する。   After the solder is melted, the heating is stopped or the heating temperature is lowered to a temperature below the melting point (217 to 220 ° C.) of the solder to solidify the solder. After the solder is solidified, it is gradually cooled (slow cooling) from the melting point of the solder to a temperature close to room temperature.

製造工程の効率化の為に、従来技術にあってはかかる冷却時の速度として０．７℃／秒程が適用されていた。前述の如く、鉛（Ｐｂ）を含有しない半田は、鉛（Ｐｂ）を含有する半田に比してその融点が高い。従って常温近傍の温度に迄効率よく冷却するために、０．７℃／秒程という冷却条件が選択されていた。   In order to increase the efficiency of the manufacturing process, in the prior art, about 0.7 ° C./second has been applied as the cooling rate. As described above, the solder not containing lead (Pb) has a higher melting point than the solder containing lead (Pb). Therefore, a cooling condition of about 0.7 ° C./second has been selected in order to efficiently cool to a temperature close to room temperature.

ところが、０．７℃／秒程の冷却速度で半導体装置が冷却されると、半導体素子１０の熱膨張係数と配線基板２０の熱膨張係数の差に基づき、歪み応力が顕著に発生する。即ち、配線基板２０の熱膨張係数が半導体素子１０の熱膨張係数よりも大きいため、かかる該冷却処理時に、温度変化による伸縮が大きい配線基板２０から、半導体素子１０に対し応力が作用する。   However, when the semiconductor device is cooled at a cooling rate of about 0.7 ° C./second, strain stress is remarkably generated based on the difference between the thermal expansion coefficient of the semiconductor element 10 and the thermal expansion coefficient of the wiring board 20. That is, since the thermal expansion coefficient of the wiring board 20 is larger than the thermal expansion coefficient of the semiconductor element 10, stress acts on the semiconductor element 10 from the wiring board 20 that is greatly expanded and contracted due to a temperature change during the cooling process.

かかる状態は、半田（外部接続用突起電極９及び予備半田）が固化した状態に於いて生ずる為、配線基板２０から半導体素子１０に作用する応力を当該半田によって吸収することができない。従って、配線基板２０から半導体素子１０に作用する応力は、多層配線層３に於ける所謂Ｌｏｗ−Ｋ材料から構成される層間絶縁膜５部分に作用してしまう。   Since this state occurs when the solder (external connection protruding electrode 9 and preliminary solder) is solidified, the stress acting on the semiconductor element 10 from the wiring board 20 cannot be absorbed by the solder. Therefore, the stress acting on the semiconductor element 10 from the wiring board 20 acts on the interlayer insulating film 5 portion made of a so-called Low-K material in the multilayer wiring layer 3.

その結果、当該層間絶縁膜５を介して積層されている配線層４の層間剥離が発生し、半導体装置に電気的不良を生じてしまう。   As a result, delamination of the wiring layer 4 laminated via the interlayer insulating film 5 occurs, resulting in an electrical failure in the semiconductor device.

本発明は、鉛（Ｐｂ）を含有しない外部接続用突起電極を介して半導体素子を配線基板に実装する際に、配線基板から半導体素子のＬｏｗ−Ｋ材料から構成される層間絶縁膜を含む多層配線部に作用する応力を緩和し、層間剥離の発生を防止することができる半導体素子の実装方法及び半導体装置の製造方法を提供することを目的とする。   The present invention provides a multilayer including an interlayer insulating film composed of a Low-K material of a semiconductor element from the wiring board when the semiconductor element is mounted on the wiring board via the external connection protruding electrode not containing lead (Pb). It is an object of the present invention to provide a method for mounting a semiconductor element and a method for manufacturing a semiconductor device, which can relieve stress acting on a wiring portion and prevent occurrence of delamination.

本発明の一観点によれば、Ｌｏｗ−Ｋ材料を含む層間絶縁膜を含む多層配線部を有する半導体素子を、鉛を含有しない外部接続用突起電極を介して、配線基板に実装する方法であって、前記半導体素子の前記外部接続用突起電極を加熱処理により溶融させ、前記半導体素子と前記配線基板とを接続し、接続された前記半導体素子及び前記配線基板の第一の冷却工程を行い、前記半導体素子及び前記配線基板が前記第一の冷却工程により、第一の所定の温度に達すると、一定時間、前記第一の所定の温度の保持を行い、前記一定時間経過後に、引き続き前記半導体素子及び前記配線基板の第二の冷却工程を行い、前記第一の所定の温度は８０℃以上１５０℃以下の範囲の温度であることを特徴とする半導体素子の実装方法が提供される。

According to one aspect of the present invention, there is provided a method of mounting a semiconductor element having a multilayer wiring portion including an interlayer insulating film containing a Low-K material on a wiring board via an external connection protruding electrode that does not contain lead. Te, wherein the protruding electrode for external connection of the semiconductor element is melted by heating, and connecting the wiring substrate and the semiconductor element, makes a connection to said semiconductor element and the first cooling step of the wiring substrate, by the semiconductor element and the wiring board is the first cooling step, it reaches the first predetermined temperature, a predetermined time, performed the retention of the first predetermined temperature, after a lapse of the predetermined time, continuing the semiconductor There second row cooling step of the device and the wiring board, a mounting method of a semiconductor device, wherein said first predetermined temperature is a temperature in the range of 80 ° C. or higher 0.99 ° C. or less is provided.

本発明によれば、配線基板上に、鉛（Ｐｂ）を含有しない外部接続用突起電極を介して半導体素子を配線基板に実装する方法に於いて、当該実装の際に、配線基板から半導体素子に於けるＬｏｗ−Ｋ材料から構成される層間絶縁膜を含む多層配線部に作用する応力を緩和させて、層間剥離の発生を防止することができ、半導体装置の製造歩留りを高めることができる。   According to the present invention, in a method of mounting a semiconductor element on a wiring board via an external connection protruding electrode not containing lead (Pb) on the wiring board, the semiconductor element is mounted from the wiring board during the mounting. The stress acting on the multilayer wiring portion including the interlayer insulating film made of the Low-K material can be relaxed to prevent delamination, and the manufacturing yield of the semiconductor device can be increased.

本発明の実施の形態について、図５乃至図８を参照して説明する。   An embodiment of the present invention will be described with reference to FIGS.

本発明の実施の形態は、図１乃至図３を参照して述べた、鉛（Ｐｂ）を含有しない所謂鉛フリーの半田からなる外部接続用突起電極９を介して配線基板２０に半導体素子１０をフリップチップ（フェイスダウン）式で実装する方法に於いて、特に、半導体素子１０を配線基板２０に対しフリップチップ方式にて載置した後に、半導体素子１０の外部接続用突起電極９と配線基板２０とを接続するためのリフロー加熱工程、及びその後の冷却工程に関する。   In the embodiment of the present invention, the semiconductor element 10 is connected to the wiring substrate 20 via the external connection protruding electrode 9 made of so-called lead-free solder not containing lead (Pb), as described with reference to FIGS. Is mounted in a flip-chip (face-down) manner, and in particular, after the semiconductor element 10 is mounted on the wiring board 20 by the flip-chip method, the external connection protruding electrode 9 of the semiconductor element 10 and the wiring board are mounted. The present invention relates to a reflow heating process for connecting the power supply 20 and a subsequent cooling process.

より具体的には、リフロー加熱工程により、外部接続用突起電極９及び予め配線基板２０の電極パッド２１上に設けられ鉛（Ｐｂ）を含有しない予備半田（半田プリコート・図示を省略）を溶融して両者を接続した後、当該半田を冷却固化し更に半導体装置を常温近傍の温度まで冷却する際に、冷却の方法として後述する第１の実施態様、或いは第２の実施態様を適用する。   More specifically, the reflow heating process melts the external connection protruding electrode 9 and the preliminary solder (solder precoat, not shown) which is provided in advance on the electrode pad 21 of the wiring board 20 and does not contain lead (Pb). After the two are connected, the solder is cooled and solidified, and when the semiconductor device is cooled to a temperature near room temperature, the first embodiment or the second embodiment described later is applied as a cooling method.

このような手段により、リフロー加熱工程の後、冷却処理に因り半田が固化され、更に半導体装置を常温近傍の温度まで冷却されても、半導体素子１０の熱膨張係数と配線基板２０の熱膨張係数の差に基づき発生する応力、即ち、配線基板２０から半導体素子１０に於ける多層配線層３部分等に作用する応力の発生を抑制して、当該多層配線層３部分に於ける層間剥離等の発生を防止する。   By such means, even after the reflow heating process, the solder is solidified due to the cooling process, and even if the semiconductor device is cooled to a temperature near room temperature, the thermal expansion coefficient of the semiconductor element 10 and the thermal expansion coefficient of the wiring board 20 The generation of stress generated based on the difference between the two, that is, the stress acting on the multilayer wiring layer 3 portion in the semiconductor element 10 from the wiring substrate 20 is suppressed, and the delamination in the multilayer wiring layer 3 portion is suppressed. Prevent occurrence.

なお、半導体素子１０及び配線基板２０の構造については、図１乃至図３を参照して行った説明が適用可能であることから、以下では省略する。   In addition, about the structure of the semiconductor element 10 and the wiring board 20, since the description performed with reference to FIG. 1 thru | or FIG. 3 is applicable, it abbreviate | omits below.

本発明の発明者は、当該冷却速度を徐冷化、即ち、冷却速度を低下させる（所定の冷却温度に達する時間を遅くする）ことにより、この様な題を解消できることを見出した。   The inventor of the present invention has found that such a problem can be solved by gradually cooling the cooling rate, that is, reducing the cooling rate (slowing the time to reach a predetermined cooling temperature).

［第１の実施態様］
本実施態様にあっては、漸次冷却（徐冷）速度を、従来（約０．７℃／秒）よりも遅い約０．５℃／秒に設定して冷却を行う。 [First Embodiment]
In this embodiment, cooling is performed by setting the gradual cooling (gradual cooling) rate to about 0.5 ° C./second, which is slower than the conventional (about 0.7 ° C./second).

図５は、リフロー処理装置に於いて実施されるところの、半導体素子１０の外部接続用突起電極９と配線基板２０との接続のためのリフロー加熱工程、及び当該リフロー加熱工程後の降温・冷却工程を示す。横軸は時間（秒）を、縦軸は温度（℃）を示す。   FIG. 5 shows a reflow heating process for connection between the external connection protruding electrode 9 of the semiconductor element 10 and the wiring board 20, and temperature lowering / cooling after the reflow heating process, which is performed in the reflow processing apparatus. A process is shown. The horizontal axis represents time (seconds), and the vertical axis represents temperature (° C.).

即ち、リフロー加熱工程にあっては、１５０℃程に加熱された状態で所定時間保持し、フラックスを活性化して外部接続用突起電極９及び予備半田（半田プリコート）の表面に於ける酸化膜を除去し、しかる後半田の融点以上の温度例えば２５０℃迄昇温・加熱する。   That is, in the reflow heating process, the oxide film on the surface of the external connection protrusion electrode 9 and the preliminary solder (solder precoat) is activated by holding the flux in a heated state at about 150 ° C. for a predetermined time and activating the flux. Then, the temperature is raised and heated to a temperature equal to or higher than the melting point of the solder, for example, 250 ° C.

リフロー加熱工程の開始後約２４０秒経過すると、２５０℃に達する。このとき、当該半田は溶融している。半田の溶融後、加熱を停止或いは加熱温度を低下させて、当該半田の融点（２１７〜２２０℃）以下の温度とし、半田を固化せしめる。当該半田が固化した後、半田の融点から常温近傍の温度まで漸次冷却（徐冷）する。   After about 240 seconds have elapsed since the start of the reflow heating process, the temperature reaches 250 ° C. At this time, the solder is melted. After the solder is melted, the heating is stopped or the heating temperature is lowered to a temperature below the melting point (217 to 220 ° C.) of the solder to solidify the solder. After the solder is solidified, it is gradually cooled (slow cooling) from the melting point of the solder to a temperature close to room temperature.

本実施の態様にあっては、かかる冷却時の速度として０．５℃／秒を適用した。   In this embodiment, 0.5 ° C./sec was applied as the cooling rate.

この結果、図５に示される様に、リフロー加熱工程開始後約６５０秒経過した時点で、約５０℃に冷却される。   As a result, as shown in FIG. 5, when about 650 seconds have elapsed after the start of the reflow heating process, it is cooled to about 50 ° C.

温度が５０℃程に達した後、配線基板２０に接続された半導体素子１０をリフロー処理装置の外に搬出し自然冷却する。   After the temperature reaches about 50 ° C., the semiconductor element 10 connected to the wiring board 20 is taken out of the reflow processing apparatus and naturally cooled.

しかる後、半導体素子１０と配線基板２０との間にアンダーフィル材２３を充填し硬化させ、更に配線基板２０の下面に、半田ボールを配設し、リフロー加熱工程及び冷却工程を経て外部接続用突起電極２４を形成する。   After that, the underfill material 23 is filled between the semiconductor element 10 and the wiring board 20 and cured, and solder balls are disposed on the lower surface of the wiring board 20, and are used for external connection through a reflow heating process and a cooling process. The protruding electrode 24 is formed.

［第２の実施態様］
本実施態様にあっては、漸次冷却（徐冷）速度を、従来（約０．７℃／秒）よりも遅い約０．３℃／秒に設定して冷却を行う。 [Second Embodiment]
In this embodiment, cooling is performed by setting the gradual cooling (slow cooling) rate to about 0.3 ° C./second, which is slower than the conventional (about 0.7 ° C./second).

図６は、リフロー処理装置に於いて実施されるところの、半導体素子１０の外部接続用突起電極９と配線基板２０との接続のためのリフロー加熱工程、及び当該リフロー加熱工程後の降温・冷却工程を示す。横軸は時間（秒）を、縦軸は温度（℃）を示す。   FIG. 6 shows a reflow heating process for connection between the external connection protruding electrode 9 of the semiconductor element 10 and the wiring board 20, and temperature lowering / cooling after the reflow heating process, which is performed in the reflow processing apparatus. A process is shown. The horizontal axis represents time (seconds), and the vertical axis represents temperature (° C.).

即ち、リフロー加熱工程にあっては、１５０℃程に加熱された状態で所定時間保持し、フラックスを活性化して外部接続用突起電極９及び予備半田（半田プリコート）の表面に於ける酸化膜を除去し、しかる後半田の融点以上の温度例えば２５０℃迄昇温・加熱する。   That is, in the reflow heating process, the oxide film on the surface of the external connection protrusion electrode 9 and the preliminary solder (solder precoat) is activated by holding the flux in a heated state at about 150 ° C. for a predetermined time and activating the flux. Then, the temperature is raised and heated to a temperature equal to or higher than the melting point of the solder, for example, 250 ° C.

リフロー加熱工程の開始後約２４０秒経過すると、２５０℃に達する。このとき、当該半田は溶融している。半田の溶融後、加熱を停止或いは加熱温度を低下させて、当該半田の融点（２１７〜２２０℃）以下の温度とし、半田を固化せしめる。   After about 240 seconds have elapsed since the start of the reflow heating process, the temperature reaches 250 ° C. At this time, the solder is melted. After the solder is melted, the heating is stopped or the heating temperature is lowered to a temperature below the melting point (217 to 220 ° C.) of the solder to solidify the solder.

当該半田が固化した後、半田の融点から常温近傍の温度まで漸次冷却（徐冷）する。   After the solder is solidified, it is gradually cooled (slow cooling) from the melting point of the solder to a temperature close to room temperature.

本実施の態様にあっては、かかる冷却時の速度として０．３℃／秒を適用した。   In this embodiment, 0.3 ° C./second was applied as the cooling speed.

この結果、図６に示される様に、リフロー加熱工程開始後約８８０秒経過した時点で、約５０℃に冷却される。   As a result, as shown in FIG. 6, when about 880 seconds have elapsed after the start of the reflow heating process, it is cooled to about 50 ° C.

温度が５０℃程に達した後、配線基板２０に接続された半導体素子１０をリフロー処理装置の外に搬出し自然冷却する。   After the temperature reaches about 50 ° C., the semiconductor element 10 connected to the wiring board 20 is taken out of the reflow processing apparatus and naturally cooled.

しかる後、半導体素子１０と配線基板２０との間にアンダーフィル材２３を充填し硬化させ、更に配線基板２０の下面に、半田ボールを配設し、リフロー加熱工程及び冷却工程を経て外部接続用突起電極２４を形成する。   After that, the underfill material 23 is filled between the semiconductor element 10 and the wiring board 20 and cured, and solder balls are disposed on the lower surface of the wiring board 20, and are used for external connection through a reflow heating process and a cooling process. The protruding electrode 24 is formed.

発明者は、これら二つの実施態様に従って製造された半導体装置について、半導体素子１０の多層配線層３を確認したところ、Ｌｏｗ−Ｋ材料から構成される層間絶縁膜５を介して積層されている配線層４に於いて、層間剥離等の破壊は発生していないことを確認した。   The inventor has confirmed the multilayer wiring layer 3 of the semiconductor element 10 in the semiconductor device manufactured according to these two embodiments. As a result, the wiring stacked through the interlayer insulating film 5 made of a Low-K material. In layer 4, it was confirmed that no breakage such as delamination occurred.

発明者は、更にＪＥＤＥＣ（Ｊｏｉｎｔ Ｅｌｅｃｔｒｏｎ Ｄｅｖｉｃｅ Ｅｎｇｉｎｅｅｒｉｎｇ Ｃｏｕｎｃｉｌ）−Ｌｅｖｅｌ３に規定されている条件下での吸湿、３回のリフロー試験及び、環境試験として１０００サイクルの温度衝撃試験を行い、Ｌｏｗ−Ｋ材料から構成される層間絶縁膜５を介して積層されている配線層４に応力が作用して生じる層間剥離等の破壊が発生していないことを確認した。   The inventor further performs moisture absorption under the conditions specified in JEDEC (Joint Electron Engineering Engineering) -Level 3, three reflow tests, and 1000 cycles of thermal shock tests as environmental tests. It was confirmed that there was no breakdown such as delamination caused by stress acting on the wiring layer 4 laminated via the interlayer insulating film 5 constituted.

このように、冷却速度を、従来（０．７℃／秒）よりも遅い０．５℃／秒或いは０．３℃／秒に設定することにより、冷却に伴う半導体素子１０及び配線基板２０の収縮・変形に対して、配線基板２０から半導体素子１０に作用する前記応力の発生を抑制することができる。   Thus, by setting the cooling rate to 0.5 ° C./second or 0.3 ° C./second, which is slower than the conventional (0.7 ° C./second), the semiconductor element 10 and the wiring board 20 that accompany the cooling are used. The generation of the stress acting on the semiconductor element 10 from the wiring board 20 can be suppressed against the shrinkage / deformation.

従って、配線基板２０から、半導体素子１０のＬｏｗ−Ｋ材料から構成される層間絶縁膜５を介して積層されている配線層４に作用する応力は緩和され、層間剥離等の破壊の発生を防止することができる。   Accordingly, the stress acting on the wiring layer 4 laminated from the wiring substrate 20 via the interlayer insulating film 5 made of the Low-K material of the semiconductor element 10 is relaxed, and the occurrence of destruction such as delamination is prevented. can do.

［第３の実施態様］
前記二つの実施態様にあっては、リフロー加熱工程後の冷却工程において、冷却速度をより遅くすることにより、配線基板２０から半導体素子１０の多層配線層３中の強度が弱く脆弱な所謂Ｌｏｗ−Ｋ材料から構成される層間絶縁膜５に応力が作用して層間剥離等が発生することを防止している。 [Third Embodiment]
In the two embodiments, in the cooling step after the reflow heating step, by lowering the cooling rate, the strength in the multilayer wiring layer 3 of the semiconductor element 10 from the wiring substrate 20 is weak and weak, so-called Low- It prevents the stress from acting on the interlayer insulating film 5 made of the K material and causing delamination.

しかしながら、この様な態様にあっては、冷却速度をより遅くすれば、冷却に要する時間が長くなり、半導体装置の製造コストが上昇してしまう一因となる。   However, in such an aspect, if the cooling rate is made slower, the time required for cooling becomes longer, which contributes to an increase in the manufacturing cost of the semiconductor device.

そこで、本実施態様にあっては、冷却速度を段階的（ステップ状）に変えることにより、急激な温度変化を来さず、且つ冷却処理に要する時間の短縮化を図る。急激な温度変化を生じないことにより、半導体素子１０のＬｏｗ−Ｋ材料から構成される層間絶縁膜５を介して積層されている配線層４に作用する応力は緩和され、層間剥離・破壊の発生を抑制するともに、冷却時間の長時間化を抑制する。   Therefore, in this embodiment, by changing the cooling rate stepwise (stepped), a rapid temperature change does not occur and the time required for the cooling process is shortened. By not causing an abrupt temperature change, the stress acting on the wiring layer 4 laminated via the interlayer insulating film 5 made of the Low-K material of the semiconductor element 10 is relaxed, and delamination / breakage occurs. As well as a longer cooling time.

具体的には、リフロー加熱工程後の冷却工程中に、一定時間、所定の温度を保持し、その後再度温度を降下させる。冷却工程に於いて、これを少なくとも１回行い、５０℃程まで冷却する。   Specifically, during the cooling process after the reflow heating process, a predetermined temperature is maintained for a certain time, and then the temperature is decreased again. In the cooling step, this is performed at least once and cooled to about 50 ° C.

図７は、本実施の態様に於いて、リフロー処理装置に於いて実施されるところの、半導体素子１０の外部接続用突起電極９と配線基板２０との接続のためのリフロー加熱工程、及び当該リフロー加熱工程後の降温・冷却工程を示す。横軸は時間（秒）を、縦軸は温度（℃）を示す。   FIG. 7 shows a reflow heating process for connection between the external connection protruding electrode 9 of the semiconductor element 10 and the wiring board 20, which is performed in the reflow processing apparatus in the present embodiment, and The temperature lowering / cooling process after the reflow heating process is shown. The horizontal axis represents time (seconds), and the vertical axis represents temperature (° C.).

即ち、リフロー加熱工程にあっては、１５０℃程に加熱された状態で所定時間保持し、フラックスを活性化して外部接続用突起電極９及び予備半田（半田プリコート）の表面に於ける酸化膜を除去し、しかる後半田の融点以上の温度例えば２５０℃迄昇温・加熱する。   That is, in the reflow heating process, the oxide film on the surface of the external connection protrusion electrode 9 and the preliminary solder (solder precoat) is activated by holding the flux in a heated state at about 150 ° C. for a predetermined time and activating the flux. Then, the temperature is raised and heated to a temperature equal to or higher than the melting point of the solder, for example, 250 ° C.

リフロー加熱工程の開始後約２４０秒経過すると、２５０℃に達する。このとき、当該半田は溶融している。半田の溶融後、加熱を停止或いは加熱温度を低下させて、当該半田の融点（２１７〜２２０℃）以下の温度とし、半田を固化せしめる。   After about 240 seconds have elapsed since the start of the reflow heating process, the temperature reaches 250 ° C. At this time, the solder is melted. After the solder is melted, the heating is stopped or the heating temperature is lowered to a temperature below the melting point (217 to 220 ° C.) of the solder to solidify the solder.

当該半田が固化した後、半田の融点から常温近傍の温度まで漸次冷却（徐冷）する。   After the solder is solidified, it is gradually cooled (slow cooling) from the melting point of the solder to a temperature close to room temperature.

本実施の態様にあっては、当初の冷却速度を約０．７℃／秒に設定して冷却を行い、リフロー加熱工程の開始後約４１０秒経過して温度が約１５０℃になった時点で、約３００秒間当該温度約１５０℃を維持する。   In this embodiment, when the initial cooling rate is set to about 0.7 ° C./second, cooling is performed, and when the temperature reaches about 150 ° C. after about 410 seconds from the start of the reflow heating process. Then, the temperature is maintained at about 150 ° C. for about 300 seconds.

その後、再び冷却速度を約０．７℃／秒に設定して、５０℃程になるまで冷却する。   Thereafter, the cooling rate is set again to about 0.7 ° C./second, and cooling is performed until it reaches about 50 ° C.

この結果、図７に示される様に、リフロー加熱工程開始後約８１０秒経過した時点で、約５０℃に冷却される。   As a result, as shown in FIG. 7, when about 810 seconds have elapsed after the start of the reflow heating process, it is cooled to about 50 ° C.

温度が５０℃程に達した後、配線基板２０に接続された半導体素子１０をリフロー処理装置の外に搬出し自然冷却する。   After the temperature reaches about 50 ° C., the semiconductor element 10 connected to the wiring board 20 is taken out of the reflow processing apparatus and naturally cooled.

しかる後、半導体素子１０と配線基板２０との間にアンダーフィル材２３を充填し硬化させ、更に配線基板２０の下面に、半田ボールを配設し、リフロー加熱工程及び冷却工程を経て外部接続用突起電極２４を形成する。   After that, the underfill material 23 is filled between the semiconductor element 10 and the wiring board 20 and cured, and solder balls are disposed on the lower surface of the wiring board 20, and are used for external connection through a reflow heating process and a cooling process. The protruding electrode 24 is formed.

［第４の実施態様］
前記実施の態様７と同様に、リフロー加熱工程後の冷却工程中に、一定時間、所定の温度を保持し、その後再度温度を降下させる。冷却工程に於いて、これを少なくとも１回行い、５０℃程に冷却する。 [Fourth Embodiment]
As in the seventh embodiment, during the cooling step after the reflow heating step, a predetermined temperature is maintained for a certain time, and then the temperature is lowered again. In the cooling step, this is performed at least once and cooled to about 50 ° C.

図８は、本実施の態様に於いて、リフロー処理装置に於いて実施されるところの、半導体素子１０の外部接続用突起電極９と配線基板２０との接続のためのリフロー加熱工程、及び当該リフロー加熱工程後の降温・冷却工程を示す。横軸は時間（秒）を、縦軸は温度（℃）を示す。   FIG. 8 shows a reflow heating process for connection between the external connection protruding electrode 9 of the semiconductor element 10 and the wiring board 20, which is performed in the reflow processing apparatus in the present embodiment, and The temperature lowering / cooling process after the reflow heating process is shown. The horizontal axis represents time (seconds), and the vertical axis represents temperature (° C.).

即ち、リフロー加熱工程にあっては、１５０℃程に加熱された状態で所定時間保持し、フラックスを活性化して外部接続用突起電極９及び予備半田（半田プリコート）の表面に於ける酸化膜を除去し、しかる後半田の融点以上の温度例えば２５０℃迄昇温・加熱する。   That is, in the reflow heating process, the oxide film on the surface of the external connection protrusion electrode 9 and the preliminary solder (solder precoat) is activated by holding the flux in a heated state at about 150 ° C. for a predetermined time and activating the flux. Then, the temperature is raised and heated to a temperature equal to or higher than the melting point of the solder, for example, 250 ° C.

リフロー加熱工程の開始後約２４０秒経過すると、２５０℃に達する。このとき、当該半田は溶融している。半田の溶融後、加熱を停止或いは加熱温度を低下させて、当該半田の融点（２１７〜２２０℃）以下の温度とし、半田を固化せしめる。   After about 240 seconds have elapsed since the start of the reflow heating process, the temperature reaches 250 ° C. At this time, the solder is melted. After the solder is melted, the heating is stopped or the heating temperature is lowered to a temperature below the melting point (217 to 220 ° C.) of the solder to solidify the solder.

当該半田が固化した後、半田の融点から常温近傍の温度まで漸次冷却（徐冷）する。   After the solder is solidified, it is gradually cooled (slow cooling) from the melting point of the solder to a temperature close to room temperature.

本実施の態様にあっては、当初の冷却速度を約０．７℃／秒に設定して冷却を行い、リフロー加熱工程の開始後約４６０秒経過して温度が約１２０℃になった時点で、約３００秒間当該温度１２０℃を維持する。   In this embodiment, when the initial cooling rate is set to about 0.7 ° C./second, cooling is performed, and when the temperature reaches about 120 ° C. after about 460 seconds from the start of the reflow heating process. The temperature is maintained at 120 ° C. for about 300 seconds.

その後、再び、冷却速度を約０．７℃／秒に設定して、約５０℃になるまで冷却する。   Thereafter, the cooling rate is set again at about 0.7 ° C./second, and cooling is performed until it reaches about 50 ° C.

この結果、図８に示される様に、リフロー加熱工程開始後約８６０秒経過した時点で、約５０℃に冷却される。   As a result, as shown in FIG. 8, when about 860 seconds have elapsed after the start of the reflow heating process, the temperature is cooled to about 50 ° C.

温度が５０℃程に達した後、配線基板２０に接続された半導体素子１０をリフロー処理装置の外に搬出し自然冷却する。   After the temperature reaches about 50 ° C., the semiconductor element 10 connected to the wiring board 20 is taken out of the reflow processing apparatus and naturally cooled.

しかる後、半導体素子１０と配線基板２０との間にアンダーフィル材２３を充填し硬化させ、更に配線基板２０の下面に、半田ボールを配設し、リフロー加熱工程及び冷却工程を経て外部接続用突起電極２４を形成する。   After that, the underfill material 23 is filled between the semiconductor element 10 and the wiring board 20 and cured, and solder balls are disposed on the lower surface of the wiring board 20, and are used for external connection through a reflow heating process and a cooling process. The protruding electrode 24 is formed.

この様な、図７及び図８に示す実施の態様にあっては、所定の温度（図７に示す例では１５０℃、図８に示す例では１２０℃）の保持は、リフロー装置内で行われているが、本発明はかかる例に限定されない。   In the embodiment shown in FIGS. 7 and 8, the predetermined temperature (150 ° C. in the example shown in FIG. 7, 120 ° C. in the example shown in FIG. 8) is maintained in the reflow apparatus. However, the present invention is not limited to such an example.

例えば、かかる保持する温度となった時点で、半導体素子１０及び配線基板２０をリフロー処理装置から恒温槽に移動せしめ、当該恒温槽に於いて保持温度に維持する態様であってもよい。   For example, the semiconductor element 10 and the wiring board 20 may be moved from the reflow processing apparatus to a thermostat when the temperature is held and maintained at the hold temperature in the thermostat.

なお、この場合も、一定時間保持した後に冷却し、温度が約５０℃に達した後は、配線基板２０に接続された半導体素子１０を恒温槽の外に搬出し自然冷却する。   In this case as well, the semiconductor element 10 connected to the wiring board 20 is taken out of the thermostatic bath and naturally cooled after the temperature has reached about 50 ° C. after being held for a certain time.

発明者は、外部接続用突起電極２４を接続した後に、半導体素子１０の多層配線層３を確認したところ、Ｌｏｗ−Ｋ材料から構成される層間絶縁膜５を介して積層されている配線層４に応力が作用して生じる層間剥離・破壊は発生していないことを確認した。   The inventor has confirmed the multilayer wiring layer 3 of the semiconductor element 10 after connecting the external connection protruding electrode 24, and found that the wiring layer 4 is laminated via the interlayer insulating film 5 made of a Low-K material. It was confirmed that there was no delamination / breakage caused by stress.

更に、本発明の発明者は、ＪＥＤＥＣ（Ｊｏｉｎｔ Ｅｌｅｃｔｒｏｎ Ｄｅｖｉｃｅ Ｅｎｇｉｎｅｅｒｉｎｇ Ｃｏｕｎｃｉｌ）−Ｌｅｖｅｌ３に規定されている条件下での吸湿、３回のリフロー試験及び、環境試験として１０００サイクルの温度衝撃試験を行って確認したところ、Ｌｏｗ−Ｋ材料から構成される層間絶縁膜５を介して積層されている配線層４に応力が作用して生じる層間剥離・破壊は発生していないことを確認した。   Furthermore, the inventor of the present invention performs confirmation by performing moisture absorption under the conditions specified in JEDEC (Joint Electron Engineering Engineering) -Level3, three reflow tests, and 1000 cycles of temperature shock tests as environmental tests. As a result, it was confirmed that there was no delamination / breakage caused by stress acting on the wiring layer 4 laminated via the interlayer insulating film 5 made of Low-K material.

一般に、応力の作用により一定の歪みが与えられ、この歪みを保持している場合、クリープ現象により、当該応力は緩和される。   In general, a certain strain is given by the action of stress, and when this strain is maintained, the stress is relaxed by a creep phenomenon.

本例は、このようなクリープ現象を考慮し、リフロー加熱工程後の冷却工程中に、一定時間、所定の温度を保持して応力を緩和し、その後、再度温度を降下させるというように、冷却速度をステップ状に変えている。   In this example, in consideration of such a creep phenomenon, during the cooling process after the reflow heating process, the stress is relieved by holding a predetermined temperature for a certain time, and then the temperature is lowered again. The speed is changed in steps.

従って、冷却に伴う半導体素子１０及び配線基板２０の収縮変形に、当該半田は追従することができ、配線基板２０から半導体素子１０に作用する前記応力を吸収することができる。よって、配線基板２０から半導体素子１０のＬｏｗ−Ｋ材料から構成される層間絶縁膜５を介して積層されている配線層４に作用する応力は緩和され、層間剥離・破壊の発生を抑制することができる。   Accordingly, the solder can follow the shrinkage deformation of the semiconductor element 10 and the wiring board 20 accompanying cooling, and the stress acting on the semiconductor element 10 from the wiring board 20 can be absorbed. Therefore, the stress acting on the wiring layer 4 laminated from the wiring substrate 20 via the interlayer insulating film 5 made of the Low-K material of the semiconductor element 10 is relaxed, and the occurrence of delamination / breakage is suppressed. Can do.

また、第１或いは第２の実施の態様にあっては、冷却速度を遅くすることにより、冷却時間が長くなり、製造コストが上昇してしまう恐れがあるが、第３の実施の態様では、冷却速度を遅くする必要はないため、処理時間の短縮化を図ることができる。   Further, in the first or second embodiment, the cooling time may be increased by slowing down the cooling rate, which may increase the manufacturing cost. In the third embodiment, Since it is not necessary to slow down the cooling rate, the processing time can be shortened.

尚、保持する温度として、８０℃乃至１５０℃の範囲の所定の温度を設定することが望ましい。   It is desirable to set a predetermined temperature in the range of 80 ° C. to 150 ° C. as the temperature to be held.

発明者は、保持する温度が８０℃よりも低い場合は、保持する時点ですでに層間絶縁膜５を介して積層されている配線層４に応力が作用し、層間剥離が発生していることを確認している。   The inventor has found that when the holding temperature is lower than 80 ° C., stress is applied to the wiring layer 4 already laminated via the interlayer insulating film 5 at the time of holding, and delamination occurs. Have confirmed.

また、保持する温度が１５０℃よりも高い場合は、仮に、温度が１５０℃よりも高い温度のときの層間剥離を防ぐことができても、冷却により再度半田が変形し、配線基板２０から半導体素子１０に作用する前記応力を吸収することができないため、層間剥離を防ぐことはできない。従って、結果として、１５０℃以下の温度において冷却速度をステップ状に変えることが必要になってしまう。   In addition, when the temperature to be held is higher than 150 ° C., even if the delamination can be prevented when the temperature is higher than 150 ° C., the solder is deformed again by cooling, and the semiconductor is separated from the wiring substrate 20. Since the stress acting on the element 10 cannot be absorbed, delamination cannot be prevented. Therefore, as a result, it becomes necessary to change the cooling rate stepwise at a temperature of 150 ° C. or lower.

従って、保持する温度として、例えば、８０℃乃至１５０℃の範囲の所定の温度を設定することが望ましい。   Therefore, it is desirable to set a predetermined temperature in the range of 80 ° C. to 150 ° C., for example, as the temperature to be held.

また、所定の温度に保持する時間は、当該温度に拘わらず、１２０秒以上であることが望ましい。   Moreover, it is desirable that the time for holding at the predetermined temperature is 120 seconds or more regardless of the temperature.

所定の温度に保持する時間が、１２０秒よりも短ければ、前記クリープ現象に基づいて応力が緩和する前に、冷却が進行してしまい、半田は、配線基板２０から半導体素子１０に作用する前記応力を吸収することができず、層間剥離を防ぐことはできない。   If the time for holding at the predetermined temperature is shorter than 120 seconds, the cooling proceeds before the stress is relaxed based on the creep phenomenon, and the solder acts on the semiconductor element 10 from the wiring board 20. Stress cannot be absorbed and delamination cannot be prevented.

一方、所定の温度に保持する時間が、１２０秒以上であれば、配線基板２０から半導体素子１０に作用する前記応力を十分に緩和することができ、冷却に伴う半導体素子１０及び配線基板２０の収縮変形に当該半田は追従して、配線基板２０から半導体素子１０に作用する前記応力を吸収することができる。よって、配線基板２０から半導体素子１０のＬｏｗ−Ｋ材料から構成される層間絶縁膜５を介して積層されている配線層４に作用する応力は緩和され、層間剥離・破壊の発生を抑制できる。   On the other hand, if the time for holding at the predetermined temperature is 120 seconds or more, the stress acting on the semiconductor element 10 from the wiring board 20 can be sufficiently relaxed, and the semiconductor element 10 and the wiring board 20 that are cooled are cooled. The solder follows the contraction deformation and can absorb the stress acting on the semiconductor element 10 from the wiring board 20. Therefore, the stress acting on the wiring layer 4 laminated from the wiring substrate 20 via the interlayer insulating film 5 made of the Low-K material of the semiconductor element 10 is alleviated, and generation of delamination / breakage can be suppressed.

従って、層間剥離・破壊の発生を抑制するという観点からは、所定の温度に保持する時間は長ければ長い方が良いが、当該保持する時間が長すぎれば、工程時間が長くなり、その結果、製造コストが上昇してしまう恐れがある。保持する時間の上限は、工程時間の上限に基づき適宜設定される。   Therefore, from the viewpoint of suppressing the occurrence of delamination / breakage, it is better if the time for holding at a predetermined temperature is long, but if the holding time is too long, the process time becomes long. Manufacturing costs may increase. The upper limit of the time to hold | maintain is suitably set based on the upper limit of process time.

また、ステップ数、即ち、所定の温度を一定時間保持し、その後、再度温度を降下させる回数は、本例のように１回に限らず、複数回としてもよい。なお、層間剥離・破壊の発生を抑制するという観点からは、ステップ数は多ければ多いほど良いが、当該ステップ数が多ければ、全体として工程時間が長くなり、その結果、製造コストが上昇してしまうおそれがある。従って、ステップ数の上限は、工程時間の上限に基づき適宜設定される。   Further, the number of steps, that is, the number of times of holding the predetermined temperature for a certain time and then lowering the temperature again is not limited to once as in this example, but may be multiple times. In addition, from the viewpoint of suppressing the occurrence of delamination / breakage, the larger the number of steps, the better. However, the larger the number of steps, the longer the process time, resulting in an increase in manufacturing cost. There is a risk that. Therefore, the upper limit of the number of steps is appropriately set based on the upper limit of the process time.

このように、第３の実施の態様によれば、冷却速度をステップ状に変えることにより、第１、第２の実施の態様と同様に、配線基板２０から半導体素子１０のＬｏｗ−Ｋ材料から構成される層間絶縁膜５を介して積層されている配線層４に作用する応力を緩和して、層間剥離・破壊の発生を抑制することができるとともに、工程時間の短縮化を図ることができる。   As described above, according to the third embodiment, by changing the cooling rate stepwise, from the wiring substrate 20 to the Low-K material of the semiconductor element 10 as in the first and second embodiments. It is possible to relieve stress acting on the wiring layer 4 laminated via the constituted interlayer insulating film 5 and to suppress the occurrence of delamination / breakage and to shorten the process time. .

以上説明したように、本発明によれば、鉛（Ｐｂ）を含有しない外部接続用突起電極を介して配線基板に半導体素子を実装する方法であって、当該実装の際に、配線基板から、当該半導体装置のＬｏｗ−Ｋ材料から構成される層間絶縁膜を介して積層されている配線層に作用する応力を緩和させて、層間剥離の発生を抑制することができる。   As described above, according to the present invention, there is provided a method for mounting a semiconductor element on a wiring board via an external connection protruding electrode that does not contain lead (Pb). Generation of delamination can be suppressed by relieving stress acting on a wiring layer stacked via an interlayer insulating film made of a Low-K material of the semiconductor device.

また、本発明によれば、配線基板として、安価な有機ビルドアップ基板を使用することができるため、製造コストのコストダウンを図ることができる。   In addition, according to the present invention, since an inexpensive organic build-up substrate can be used as the wiring substrate, the manufacturing cost can be reduced.

更に、本発明によれば、配線基板に半導体素子を実装する際に上述の層間剥離の発生することを抑制する目的で特殊な構造を半導体素子並びに配線基板に持たせる必要がなく、また、特別な実装装置を用いる必要もない。従って、当該実装の際に、半導体素子において層間剥離が発生してしまうことを容易に抑制することができる。   Furthermore, according to the present invention, there is no need to provide the semiconductor element and the wiring board with a special structure for the purpose of suppressing the occurrence of delamination described above when mounting the semiconductor element on the wiring board. It is not necessary to use a simple mounting device. Therefore, it is possible to easily suppress delamination in the semiconductor element during the mounting.

尚、本発明は前述の如き、特定の実施形態に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内において、種々の変形及び変更が可能である。

以上の説明に関し、更に以下の項を開示する。
（付記１） 半導体素子を、鉛（Ｐｂ）を含有しない外部接続用突起電極を介して配線基板に実装する方法であって、
前記半導体素子の外部接続用突起電極と前記配線基板とを接続するリフロー加熱処理を施した後に、
接続された前記半導体素子及び前記配線基板を、０．５℃／秒以下の冷却速度で冷却することを特徴とする半導体素子の実装方法。
（付記２） 付記１記載の半導体素子の実装方法であって、
前記冷却速度は、０．３℃／秒であることを特徴とする半導体素子の実装方法。
（付記３） 付記１又は２記載の半導体素子の実装方法であって、
前記外部接続用突起電極は、鉛を含有しない半田から構成されることを特徴とする半導体素子の実装方法。
（付記４） 付記１乃至３いずれか一項記載の半導体素子の実装方法であって、
前記配線基板は有機材料からなることを特徴とする半導体装置の実装方法。
（付記５） 付記４記載の半導体素子の実装方法であって、
前記半導体装置は、低誘電率材料から構成される層間絶縁膜を介して配線層が積層された多層配線構造を有することを特徴とする半導体装置の実装方法。
（付記６） 半導体素子を外部接続用突起電極を介して配線基板に実装する方法であって、
前記半導体素子の前記外部接続用突起電極と前記配線基板とを接続するためにリフロー加熱処理を施した後に、
接続された前記半導体素子及び前記配線基板を冷却して温度を降下させ、所定の温度に達すると、一定時間、当該所定の温度を保持し、前記一定時間経過後に、前記半導体素子及び前記配線基板を再度冷却して温度を降下させる、というステップ冷却が施されることを特徴とする半導体素子の実装方法。
（付記７） 付記６記載の半導体素子の実装方法であって、
前記ステップ冷却を１回以上施すことを特徴とする半導体素子の実装方法。
（付記８） 付記６又は７記載の半導体素子の実装方法であって、
前記所定の温度は８０℃以上１５０℃以下の範囲の温度であることを特徴とする半導体素子の実装方法。
（付記９） 付記６乃至８いずれか一項記載の半導体素子の実装方法であって、
前記一定の時間は、１２０秒以上であることを特徴とする半導体素子の実装方法。
（付記１０） 付記９記載の半導体素子の実装方法であって、
前記一定の時間は、約３００秒以上であることを特徴とする半導体素子の実装方法。
（付記１１） 付記６乃至１０いずれか一項記載の半導体素子の実装方法であって、
前記外部接続用突起電極は、鉛を含有しない半田から構成されることを特徴とする半導体素子の実装方法。
（付記１２） 付記６乃至１１いずれか一項記載の半導体素子の実装方法であって、
前記配線基板は有機材料からなることを特徴とする半導体素子の実装方法。
（付記１３） 付記１２記載の半導体素子の実装方法であって、
前記半導体素子は、低誘電率材料から構成される層間絶縁膜を介して配線層が積層された多層配線構造を有することを特徴とする半導体素子の実装方法。
（付記１４） 半導体素子の鉛（Ｐｂ）を含有しない外部接続用突起電極と配線基板とを接続するリフロー加熱処理を施した後に、
接続された前記半導体素子及び前記配線基板を、０．５℃／秒以下の冷却速度で冷却することを特徴とする半導体装置の製造方法。
（付記１５） 半導体素子の外部接続用突起電極と配線基板とを接続するためにリフロー加熱処理を施した後に、接続された前記半導体素子及び前記配線基板を冷却して温度を降下させ、
所定の温度に達すると、一定時間、当該所定の温度を保持し、
前記一定時間経過後に、前記半導体素子及び前記配線基板を再度冷却して温度を降下させる、というステップ冷却が施されることを特徴とする半導体装置の製造方法。 The present invention is not limited to the specific embodiments as described above, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims.

Regarding the above description, the following items are further disclosed.
(Supplementary Note 1) A method of mounting a semiconductor element on a wiring board via a protruding electrode for external connection that does not contain lead (Pb),
After performing a reflow heat treatment for connecting the protruding electrode for external connection of the semiconductor element and the wiring board,
A method of mounting a semiconductor element, comprising cooling the connected semiconductor element and the wiring board at a cooling rate of 0.5 ° C./second or less.
(Additional remark 2) It is the mounting method of the semiconductor element of Additional remark 1, Comprising:
The method for mounting a semiconductor element, wherein the cooling rate is 0.3 ° C./second.
(Additional remark 3) It is the mounting method of the semiconductor element of Additional remark 1 or 2, Comprising:
The semiconductor element mounting method, wherein the external connection protruding electrode is made of solder not containing lead.
(Additional remark 4) It is the mounting method of the semiconductor element as described in any one of additional remark 1 thru | or 3, Comprising:
The method of mounting a semiconductor device, wherein the wiring board is made of an organic material.
(Additional remark 5) It is the mounting method of the semiconductor element of Additional remark 4, Comprising:
The semiconductor device has a multi-layer wiring structure in which wiring layers are stacked with an interlayer insulating film made of a low dielectric constant material.
(Supplementary Note 6) A method of mounting a semiconductor element on a wiring board via a protruding electrode for external connection,
After performing a reflow heat treatment to connect the protruding electrode for external connection of the semiconductor element and the wiring board,
The connected semiconductor element and the wiring board are cooled to lower the temperature, and when the predetermined temperature is reached, the predetermined temperature is maintained for a predetermined time, and after the predetermined time has elapsed, the semiconductor element and the wiring board A method for mounting a semiconductor element, wherein step cooling is performed in which the temperature is lowered by cooling again.
(Appendix 7) A method for mounting a semiconductor element according to appendix 6,
A method for mounting a semiconductor element, wherein the step cooling is performed at least once.
(Additional remark 8) It is the mounting method of the semiconductor element of Additional remark 6 or 7,
The semiconductor element mounting method, wherein the predetermined temperature is in a range of 80 ° C. or higher and 150 ° C. or lower.
(Supplementary note 9) The method for mounting a semiconductor element according to any one of supplementary notes 6 to 8, comprising:
The semiconductor element mounting method, wherein the predetermined time is 120 seconds or more.
(Additional remark 10) It is the mounting method of the semiconductor element of Additional remark 9, Comprising:
The method of mounting a semiconductor element, wherein the predetermined time is about 300 seconds or more.
(Additional remark 11) It is the mounting method of the semiconductor element as described in any one of additional marks 6 thru | or 10, Comprising:
The semiconductor element mounting method, wherein the external connection protruding electrode is made of solder not containing lead.
(Additional remark 12) It is the mounting method of the semiconductor element of any one of Additional remarks 6 thru | or 11, Comprising:
The method of mounting a semiconductor element, wherein the wiring board is made of an organic material.
(Additional remark 13) It is the mounting method of the semiconductor element of Additional remark 12, Comprising:
The semiconductor device has a multilayer wiring structure in which wiring layers are laminated via an interlayer insulating film made of a low dielectric constant material.
(Additional remark 14) After performing the reflow heat processing which connects the projection electrode for external connection which does not contain lead (Pb) of a semiconductor element, and a wiring board,
A method of manufacturing a semiconductor device, wherein the connected semiconductor element and the wiring board are cooled at a cooling rate of 0.5 ° C./second or less.
(Supplementary Note 15) After performing the reflow heat treatment to connect the protruding electrode for external connection of the semiconductor element and the wiring board, the connected semiconductor element and the wiring board are cooled to lower the temperature,
When the predetermined temperature is reached, the predetermined temperature is maintained for a certain period of time,
A method of manufacturing a semiconductor device, comprising: step cooling in which the semiconductor element and the wiring board are cooled again and the temperature is lowered after the predetermined time has elapsed.

半導体素子の構造を示す断面図である。It is sectional drawing which shows the structure of a semiconductor element. 図１において点線で囲まれた箇所の拡大図である。FIG. 2 is an enlarged view of a portion surrounded by a dotted line in FIG. 1. 図１に示す半導体素子を配線基板にフリップチップ実装した状態を示す図である。It is a figure which shows the state which carried out the flip chip mounting of the semiconductor element shown in FIG. 図３に示す半導体装置のリフロー加熱工程及びリフロー加熱工程後の冷却工程（冷却速度は約０．７℃／秒）における半導体装置の温度変化を示すグラフである。It is a graph which shows the temperature change of the semiconductor device in the cooling process (cooling rate is about 0.7 degree-C / sec) after the reflow heating process of the semiconductor device shown in FIG. 3, and a reflow heating process. 図３に示す半導体装置のリフロー加熱工程及びリフロー加熱工程後の冷却工程（冷却速度は約０．５℃／秒）における半導体装置の温度変化を示すグラフである。It is a graph which shows the temperature change of the semiconductor device in the cooling process (cooling rate is about 0.5 degree-C / sec) after the reflow heating process and reflow heating process of the semiconductor device shown in FIG. 図３に示す半導体装置のリフロー加熱工程及びリフロー加熱工程後の冷却工程（冷却速度は約０．３℃／秒）における半導体装置の温度変化を示すグラフである。It is a graph which shows the temperature change of the semiconductor device in the cooling process (cooling rate is about 0.3 degree-C / sec) after the reflow heating process of the semiconductor device shown in FIG. 3, and a reflow heating process. 図３に示す半導体装置のリフロー加熱工程及びリフロー加熱工程後の冷却工程（ステップ冷却その１）における半導体装置の温度変化を示すグラフである。It is a graph which shows the temperature change of the semiconductor device in the reflow heating process of the semiconductor device shown in FIG. 3, and the cooling process (step cooling 1) after a reflow heating process. 図３に示す半導体装置のリフロー加熱工程及びリフロー加熱工程後の冷却工程（ステップ冷却その２）における半導体装置の温度変化を示すグラフである。It is a graph which shows the temperature change of the semiconductor device in the reflow heating process of the semiconductor device shown in FIG. 3, and the cooling process (step cooling 2) after a reflow heating process.

３ 多層配線層
４ 配線層
５ 層間絶縁膜
９ 外部接続用突起電極
１０ 半導体素子
２０ 配線基板 3 Multilayer Wiring Layer 4 Wiring Layer 5 Interlayer Insulating Film 9 Protruding Electrode for External Connection 10 Semiconductor Element 20 Wiring Board

Claims (6)

Ｌｏｗ−Ｋ材料を含む層間絶縁膜を含む多層配線部を有する半導体素子を、鉛を含有しない外部接続用突起電極を介して、配線基板に実装する方法であって、
前記半導体素子の前記外部接続用突起電極を加熱処理により溶融させ、前記半導体素子と前記配線基板とを接続し、
接続された前記半導体素子及び前記配線基板の第一の冷却工程を行い、前記半導体素子及び前記配線基板が前記第一の冷却工程により、第一の所定の温度に達すると、一定時間、前記第一の所定の温度の保持を行い、前記一定時間経過後に、引き続き前記半導体素子及び前記配線基板の第二の冷却工程を行い、
前記第一の所定の温度は８０℃以上１５０℃以下の範囲の温度であることを特徴とする半導体素子の実装方法。 A method of mounting a semiconductor element having a multilayer wiring portion including an interlayer insulating film containing a Low-K material on a wiring board via an external connection protruding electrode not containing lead ,
Wherein the protruding electrode for external connection of the semiconductor element is melted by heating, and connecting the wiring substrate and the semiconductor element,
A first cooling step of the connected semiconductor element and the wiring substrate is performed, and when the semiconductor element and the wiring substrate reach a first predetermined temperature by the first cooling step, the first cooling step is performed for a predetermined time . It performs holding of one given temperature, after the lapse of the predetermined time, have continued to line the second cooling step of the semiconductor element and the wiring substrate,
The method of mounting a semiconductor element, wherein the first predetermined temperature is a temperature in a range of 80 ° C. or higher and 150 ° C. or lower . 請求項１に記載の半導体素子の実装方法であって、
前記一定の時間は、１２０秒以上であることを特徴とする半導体素子の実装方法。 A method for mounting a semiconductor device according to claim 1 ,
The semiconductor element mounting method, wherein the predetermined time is 120 seconds or more. 請求項１又は２に記載の半導体素子の実装方法であって、
前記外部接続用突起電極は、鉛を含有しない半田から構成されることを特徴とする半導体素子の実装方法。 A method of mounting a semiconductor element according to claim 1 or 2 ,
The semiconductor element mounting method, wherein the external connection protruding electrode is made of solder not containing lead. 前記第一の冷却工程、前記温度の保持、及び前記第二の冷却工程は、それぞれリフロー装置のヒータの温度制御により行われることを特徴とする請求項１乃至３のいずれか一項に記載の半導体素子の実装方法。 The said 1st cooling process , the said temperature maintenance, and said 2nd cooling process are each performed by temperature control of the heater of a reflow apparatus, Each of Claim 1 thru | or 3 characterized by the above-mentioned. A method for mounting a semiconductor element. 請求項１に記載の半導体素子の実装方法であって、
前記第二の冷却工程により、前記半導体素子及び前記配線基板が前記第一の所定の温度より低い第二の所定の温度に達すると、前記第二の所定の温度の保持を行い、前記第二の所定の温度での保持を行った後、引き続き前記半導体素子及び前記配線基板の第三の冷却工程を行うことを特徴とする半導体素子の実装方法。 A method for mounting a semiconductor device according to claim 1,
More to the second cooling step, the when the semiconductor element and the wiring substrate reaches the lower than the first predetermined temperature a second predetermined temperature, performs holding of the second predetermined temperature, said first A method for mounting a semiconductor element, comprising: performing a third cooling step of the semiconductor element and the wiring board after holding at a predetermined temperature . Ｌｏｗ−Ｋ材料を含む層間絶縁膜を含む多層配線部を有する半導体素子に形成された、鉛を含有しない外部接続用突起電極を加熱処理により溶融させ、前記半導体素子と配線基板とを接続し、接続された前記半導体素子及び前記配線基板の第一の冷却工程を行い、
前記半導体素子及び前記配線基板が前記第一の冷却工程によって所定の温度に達すると、一定時間、前記所定の温度の保持を行い、
前記一定時間経過後に、引き続き前記半導体素子及び前記配線基板の第二の冷却工程を行い、
前記所定の温度は８０℃以上１５０℃以下の範囲の温度であることを特徴とする半導体装置の製造方法。 Low-K material formed on a semiconductor device having a multilayer wiring section including an interlayer insulating film including, melted by heating the external connection protruding electrodes not containing lead, and connects the semiconductor element and the wiring substrate, Performing a first cooling step of the connected semiconductor element and the wiring board;
Wherein the semiconductor element and the wiring substrate reaches a predetermined temperature by the first cooling step, a predetermined time, performed the retention of the predetermined temperature,
After lapse of the predetermined time, it has continued to the second row of the cooling step of the semiconductor element and the wiring substrate,
The method of manufacturing a semiconductor device, wherein the predetermined temperature is a temperature in a range of 80 ° C. to 150 ° C.
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