JP2014138017A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of manufacturing the same capable of suppressing generation of warpage.SOLUTION: A semiconductor device has a package substrate 10 and a semiconductor chip 20. The semiconductor chip 20 is mounted on the package substrate 10 with an element formation surface down. A thermal expansion coefficient adjustment member 23 is provided on an opposite side to the element formation surface of the semiconductor chip 20. This thermal expansion coefficient adjustment member 23 is formed by filling a material having a thermal expansion coefficient different from that of the semiconductor chip 20 into a hole or a groove formed to the semiconductor chip 20.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In recent years, as the performance of semiconductor devices increases, the number of input / output terminals of the semiconductor devices has increased remarkably. For this reason, the conventional package using wire bonding cannot cope with the increase in input / output terminals, and a flip chip package has been adopted instead of the package using wire bonding.

  In a flip chip package semiconductor device, solder balls are formed on the electrode surface of the semiconductor chip. Then, a semiconductor chip is arranged so that solder balls are placed on the electrodes of the package substrate, and a heat treatment called reflow is performed. The solder balls are melted by this heat treatment, and the electrodes of the semiconductor chip and the electrodes of the package substrate are electrically and mechanically connected via the solder.

JP 2006-66522 A JP 2010-103270 A

  An object of the present invention is to provide a semiconductor device capable of suppressing the occurrence of warpage and a manufacturing method thereof.

  According to one aspect of the disclosed technology, a package substrate, a semiconductor chip mounted on the package substrate, and a semiconductor chip embedded on the opposite side of the element formation surface of the semiconductor chip, the thermal expansion coefficient of the semiconductor chip is determined as the package. There is provided a semiconductor device having a thermal expansion coefficient adjusting member that approximates the thermal expansion coefficient of a substrate.

  According to another aspect of the disclosed technology, a step of forming a hole or a groove on the side opposite to the element formation surface of the semiconductor chip, and a substance having a thermal expansion coefficient different from that of the semiconductor chip in the hole or groove are provided. A method for manufacturing a semiconductor device is provided, which includes a step of filling and forming a thermal expansion coefficient adjusting member and a step of bonding the semiconductor chip to a package substrate.

  According to the semiconductor device and the manufacturing method according to the above aspect, the difference in thermal expansion coefficient between the package substrate and the semiconductor chip is reduced by the thermal expansion coefficient adjusting member embedded in the semiconductor chip, and the occurrence of warpage can be suppressed.

FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment. FIG. 2 is a diagram illustrating a result obtained by performing simulation calculation on the warpage of the semiconductor device according to the embodiment and the semiconductor device according to the comparative example. FIG. 3 is a cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the embodiment. FIG. 4 is a cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the embodiment. FIG. 5 is a schematic diagram showing an example in which the via density of the semiconductor chip is partially adjusted according to the density of the copper wiring provided on the package substrate. FIG. 6 is a schematic diagram illustrating an example in which a groove is formed on the back surface of the semiconductor chip and a material different from the semiconductor chip is embedded in the groove to form a thermal expansion coefficient adjusting member.

  As described above, in the semiconductor device of the flip chip package, the solder ball is reflowed to connect the semiconductor chip and the package substrate. However, since the thermal expansion coefficients of the semiconductor chip and the package substrate are different, warpage occurs with cooling after reflow.

  As a result, a large stress is applied to the element formed on the semiconductor chip to change the characteristics, and in an extreme case, the semiconductor chip may be damaged. Further, due to the warp, it becomes difficult to join the semiconductor device and the circuit board (secondary mounting board), and connection failure may occur.

  In the following embodiments, a semiconductor device capable of suppressing the occurrence of warpage and a manufacturing method thereof will be described.

(Embodiment)
FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment.

  As shown in FIG. 1, the semiconductor device according to the present embodiment includes a package substrate 10 and a semiconductor chip 20 mounted on the package substrate 10.

  A large number of electrodes 11 are arranged on the upper surface of the package substrate 10 with a relatively small pitch, and a large number of electrodes 12 are arranged on the lower surface with a relatively large pitch. These electrodes 11 and 12 are electrically connected via multilayer wiring (not shown) formed in the package substrate 10. A solder ball 13 for connecting to a circuit board (secondary mounting board) is connected under the electrode 12 of the package board 10.

  On the other hand, the semiconductor chip 20 is mounted on the package substrate 10 with the surface on which the element is formed (hereinafter referred to as the surface) facing down. A large number of electrodes 21 are arranged on the surface of the semiconductor chip 20, and these electrodes 21 are electrically connected to elements (not shown) such as transistors formed on the semiconductor chip 20.

  The electrode 11 of the package substrate 10 is formed at a position corresponding to the electrode 21 of the semiconductor chip 20. A solder ball 22 is formed under the electrode 21, and the electrode 21 and the electrode 11 of the package substrate 10 are electrically and mechanically connected via the solder ball 22.

  On the back surface (upper surface in FIG. 1) side of the semiconductor chip 20, a number of Cu vias 23 formed by embedding Cu (copper) in holes provided in the semiconductor chip 20 are provided. The Cu via 23 is an example of a thermal expansion coefficient adjusting member.

  In the present embodiment, Cu is embedded in the hole of the semiconductor chip 20 to form the via 23, but the material embedded in the hole may be any material having a larger thermal expansion coefficient than the main material (silicon) of the semiconductor chip 20, It is not limited. For example, W (tungsten) may be embedded in the hole to form the via 23.

  However, when the thermal expansion coefficient of the package substrate 10 is smaller than the thermal expansion coefficient of the main material of the semiconductor chip 20, a substance having a smaller thermal expansion coefficient than that of the main material of the semiconductor chip 20 is embedded in the holes.

  FIG. 2 is a diagram showing a result of examining the warpage of the semiconductor device according to the present embodiment by simulation calculation. FIG. 2 also shows, as a comparative example, the result of simulation calculation of the warpage of the semiconductor device similar to that of the embodiment except that the via 23 is not provided in the semiconductor chip.

  Here, the size of the semiconductor chip 20 is 52 mm (vertical) × 52 mm (horizontal) × 0.55 mm (thickness). The size of the package substrate 10 is 72 mm (vertical) × 72 mm (horizontal) × 1.45 mm (thickness).

  In FIG. 2, the horizontal axis indicates the position in the horizontal direction with the center of the package substrate 10 as the origin, and the vertical axis indicates the amount of shift in the vertical direction of the package substrate 10 at each position in the horizontal direction. Here, the amount of vertical displacement at the end of the package substrate 10 is defined as the amount of warpage.

  In the simulation, the thermal expansion coefficient of silicon, which is the main material of the semiconductor chip 20, is 3.6 ppm / K, and the thermal expansion coefficient of the package substrate 10 is 10.8 ppm / K. Further, the melting temperature of the solder ball 22 is 459 K (186 ° C.), and at the time of reflow, the semiconductor chip 20 and the package substrate 10 are heated to this temperature and then cooled to room temperature (298 K).

  Further, the Cu vias 23 have a diameter of 100 μm and a length of 275 μm, and are arranged at a pitch of 0.15 mm on the entire back surface of the semiconductor chip 20. Furthermore, the thermal expansion coefficient of the copper embedded in the via 23 is 17.2 ppm / K.

  As can be seen from FIG. 2, in the semiconductor device of the comparative example without the Cu via 23, warpage of 0.48 mm occurs on the package substrate. On the other hand, in the semiconductor device of the embodiment, the warpage of the package substrate 10 is as extremely small as 0.012 mm.

  In the present embodiment, since many Cu vias 23 are provided on the back side of the semiconductor chip 20, the thermal expansion coefficient of the semiconductor chip 20 approaches the thermal expansion coefficient of the package substrate 10. As a result, the occurrence of warpage due to the difference in thermal expansion coefficient is suppressed, and the manufacturing yield and reliability of the semiconductor device are improved.

  3 to 4 are cross-sectional views showing the method of manufacturing the semiconductor device according to this embodiment in the order of steps.

  First, transistors, other elements, wiring layers, and the like are formed on the surface side of the semiconductor substrate (wafer) 31 by a known method. Thereafter, the semiconductor substrate 31 is inverted, and a photoresist is applied to the back surface of the semiconductor substrate 31 as shown in FIG.

  Next, the photoresist film 32 is exposed using an exposure mask (not shown) provided with a predetermined pattern, and then development processing is performed. As shown in FIG. An opening 32 a is formed at a predetermined position of 32. The diameter of the opening 32a is, for example, 100 μm.

  Thereafter, using the photoresist film 32 as a mask, the semiconductor substrate 31 is etched to, for example, about half of its thickness to form a hole 31a as shown in FIG.

  Next, after removing the photoresist film 32, as shown in FIG. 4A, for example, a Ti (titanium) film or a Ta (tantalum) film is formed on the back surface of the semiconductor substrate 31 as a barrier metal 33 by sputtering or the like. It is formed to a thickness of 30 nm, and the wall surface of the hole 31 a is covered with a barrier metal 33. Thereafter, a Cu film, for example, is formed to a thickness of 200 nm as the seed layer 34 on the barrier metal 33 by sputtering or the like.

  The barrier metal 33 has an effect of improving the adhesion between the base and the seed layer 34 and an effect of preventing Cu oxidation and diffusion.

  Next, as shown in FIG. 4B, Cu is electroplated on the seed layer 34 to form a Cu film 35, and the hole 31a is filled with Cu.

  Next, the Cu film 35, the seed layer 34, and the barrier metal 33 are polished by CMP (Chemical Mechanical Polishing) or the like until the semiconductor substrate 31 is exposed as shown in FIG. Cu remaining in the hole 31 a after polishing becomes the Cu via 23.

  Next, the semiconductor substrate 31 is cut by a dicing apparatus and separated into individual semiconductor chips. Thereafter, the semiconductor chip is placed on the package substrate and reflow processing is performed. In this way, the semiconductor device having the structure shown in FIG. 1 is completed.

  Note that the diameter, depth, arrangement pitch, and the like of the Cu via 23 are determined in advance by performing a simulation calculation such as a finite element method so that the warp becomes a desired value (for example, 0.01 mm) or less. preferable.

  Further, in the above-described manufacturing method, the case where the Cu via is formed after forming the element such as the transistor and the wiring layer on the semiconductor substrate has been described. However, after the Cu via is formed on the semiconductor substrate, the element and the wiring such as the transistor are formed. A layer or the like may be formed.

(Other embodiments)
In the above-described embodiment, the case where the Cu vias are uniformly arranged on the back surface side of the semiconductor chip has been described. However, the Cu via density of the semiconductor chip is partially adjusted according to the density of the copper wiring provided on the package substrate. It is preferable.

  FIG. 5 is a schematic diagram showing an example in which the via density of the semiconductor chip is partially adjusted according to the density of the copper wiring provided on the package substrate.

  As shown in FIG. 5, Cu vias 23 are arranged at a high density in the region of the semiconductor chip 20 corresponding to a place where the density of the copper wiring 15 of the package substrate 10 is high. In addition, Cu vias 23 are arranged at a low density in the region of the semiconductor chip 20 corresponding to a place where the density of the copper wiring 15 of the package substrate 10 is low. Thereby, the curvature resulting from the difference in a thermal expansion coefficient can be reduced further.

  In the above-described embodiment, a hole is formed on the back surface of the semiconductor chip, and a material different from the semiconductor chip is embedded in the hole to form a thermal expansion coefficient adjusting member (via 23). However, for example, as shown in FIG. 6, a groove 20b may be formed on the back surface of the semiconductor chip 20, and a material different from the semiconductor chip 20 may be embedded in the groove 20b to form a thermal expansion coefficient adjusting member.

  The following additional notes are disclosed with respect to the above embodiments.

(Appendix 1) a package substrate;
A semiconductor chip mounted on the package substrate;
A semiconductor device comprising: a thermal expansion coefficient adjusting member embedded on the side opposite to the element formation surface of the semiconductor chip and configured to approximate the thermal expansion coefficient of the semiconductor chip to the thermal expansion coefficient of the package substrate.

  (Appendix 2) The appendix 1 is characterized in that the thermal expansion coefficient adjusting member is formed by embedding a substance different from a main material of the semiconductor chip in a hole or a groove formed in the semiconductor chip. Semiconductor device.

  (Supplementary note 3) The semiconductor device according to supplementary note 2, wherein the substance different from the main material is copper.

  (Supplementary note 4) The semiconductor device according to any one of supplementary notes 1 to 3, wherein a density of the thermal expansion coefficient adjusting member is set in accordance with a wiring density of the package substrate.

(Additional remark 5) The process of forming a hole or a groove | channel on the opposite side to the element formation surface of a semiconductor chip,
Filling the hole or groove with a material having a different thermal expansion coefficient from the semiconductor chip to form a thermal expansion coefficient adjusting member;
Bonding the semiconductor chip to a package substrate. A method for manufacturing a semiconductor device, comprising:

  (Supplementary note 6) The semiconductor device manufacturing method according to supplementary note 5, wherein the substances having different thermal expansion coefficients are copper.

  (Additional remark 7) The manufacturing method of the semiconductor device of Additional remark 5 or 6 characterized by setting the density of the hole or groove | channel formed in the said semiconductor chip according to the wiring density of the said package substrate.

  DESCRIPTION OF SYMBOLS 10 ... Package substrate, 11, 12 ... Electrode, 13 ... Solder ball, 15 ... Copper wiring, 20 ... Semiconductor chip, 20b ... Groove, 21 ... Electrode, 22 ... Solder ball, 23 ... Cu via (thermal expansion coefficient adjusting member) 31 ... Semiconductor substrate, 31a ... Hole, 32 ... Photoresist film, 33 ... Barrier metal, 34 ... Seed layer, 35 ... Cu film.

Claims (5)

A package substrate;
A semiconductor chip mounted on the package substrate;
A semiconductor device comprising: a thermal expansion coefficient adjusting member embedded on the side opposite to the element formation surface of the semiconductor chip and configured to approximate the thermal expansion coefficient of the semiconductor chip to the thermal expansion coefficient of the package substrate.   2. The semiconductor device according to claim 1, wherein the thermal expansion coefficient adjusting member is formed by embedding a substance different from a main material of the semiconductor chip in a hole or a groove formed in the semiconductor chip. .   3. The semiconductor device according to claim 1, wherein a density of the thermal expansion coefficient adjusting member is set according to a wiring density of the package substrate. Forming a hole or groove on the side opposite to the element formation surface of the semiconductor chip;
Filling the hole or groove with a material having a different thermal expansion coefficient from the semiconductor chip to form a thermal expansion coefficient adjusting member;
Bonding the semiconductor chip to a package substrate. A method for manufacturing a semiconductor device, comprising:   5. The method of manufacturing a semiconductor device according to claim 4, wherein the substances having different thermal expansion coefficients are copper.

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