JP2018182273A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device.SOLUTION: A semiconductor device has a wiring board CB and a semiconductor chip CP mounted on the wiring board CP. The semiconductor chip CP has a pad PD, an insulation film PA having an opening OP3 exposing part of the pad PD and a pillar electrode PL formed on the pad PD exposed from the opening OP3. The wiring board CB has a terminal TE and a resist layer SR1 having an opening OP1 exposing part of the terminal TE. The pillar electrode PL of the semiconductor chip CP and the terminal TE of the wiring board CB are connected via a solder layer SD. A thickness hof the pillar electrode PL from a top face PA2a of the insulation film PA is not less than half a thickness hof the solder layer SD from a top face SR1a of the resist layer SR1 and not more than the thickness h.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a semiconductor device, and can be suitably used, for example, in a semiconductor device in which a semiconductor chip is flip-chip connected to a wiring substrate.

  A semiconductor device can be manufactured by flip chip connection of a semiconductor chip on a wiring substrate.

  Japanese Patent Application Laid-Open No. 2013-211511 (Patent Document 1) describes a technology related to a semiconductor device in which a Cu pillar formed on an electrode pad of a semiconductor chip and a connection terminal of a wiring substrate are connected via solder. It is done.

  Non-Patent Document 1 describes a technique related to electromigration of a solder joint.

JP, 2013-211511, A

P. Liu, A. Overson, and D. Goyal, “Key Parameters for Fast Ni Dissolution during Electromigration of Sn 0.7 Cu Solder Joint” 2015 Electronic Components & Technology Conference, pp. 99-105, 2015.

  In a semiconductor device in which a semiconductor chip is flip-chip connected to a wiring substrate, it is desirable to improve the reliability.

  Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

  According to one embodiment, a semiconductor device includes a wiring substrate and a semiconductor chip mounted on the wiring substrate. The semiconductor chip includes a first insulating film, a pad formed on the first insulating film, a second insulating film having a first opening that exposes a part of the pad, and the first opening. And a pillar electrode formed on the exposed pad. The wiring substrate includes a terminal and a third insulating film having a second opening that exposes a part of the terminal. The pillar electrode of the semiconductor chip and the terminal of the wiring substrate are connected via a solder layer. The first thickness of the pillar electrode from the first main surface of the second insulating film is half or more of the second thickness of the solder layer from the second main surface of the third insulating film, and 2 or less thickness.

  According to one embodiment, the reliability of the semiconductor device can be improved.

FIG. 1 is an overall plan view of a semiconductor chip of an embodiment; 1 is a cross-sectional view of a semiconductor chip of an embodiment. FIG. 1 is an overall plan view of a semiconductor chip of an embodiment; FIG. 1 is a top view of a semiconductor device of an embodiment. FIG. 5 is a bottom view of the semiconductor device of FIG. 4; FIG. 5 is a cross-sectional view of the semiconductor device of FIG. 4; It is principal part sectional drawing of the semiconductor device of FIG. FIG. 5 is a top view of a wiring board used in the semiconductor device of FIG. 4; It is a top view of the wiring board of FIG. It is sectional drawing of the wiring board of FIG. It is principal part sectional drawing of the wiring board of FIG. FIG. 4 is a top view of a wiring board when the semiconductor chip of FIG. 3 is mounted. FIG. 7 is a process flow diagram showing a manufacturing process of the semiconductor device of the embodiment. FIG. 7 is a cross-sectional view showing the semiconductor device of the embodiment in the manufacturing process; FIG. 15 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 14; FIG. 16 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 15; FIG. 17 is a partial enlarged cross-sectional view showing a part of FIG. 16 in an enlarged manner. FIG. 17 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 16; FIG. 19 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 18; It is principal part sectional drawing of the semiconductor chip of one Embodiment. It is a principal part top view of the semiconductor chip of one embodiment. It is principal part sectional drawing of the semiconductor chip of one Embodiment. It is principal part sectional drawing in the manufacturing process of the semiconductor chip of one Embodiment. FIG. 24 is an essential part cross sectional view of the semiconductor chip during a manufacturing step following FIG. 23; FIG. 25 is an essential part cross sectional view of the semiconductor chip during a manufacturing step following FIG. 24; FIG. 26 is an essential part cross sectional view of the semiconductor chip during a manufacturing step following FIG. 25; FIG. 27 is an essential part cross sectional view of the semiconductor chip during a manufacturing step following FIG. 26; FIG. 28 is an essential part cross sectional view of the semiconductor chip during a manufacturing step following FIG. 27; FIG. 29 is an essential part cross sectional view of the semiconductor chip during a manufacturing step following FIG. 28; FIG. 30 is a cross-sectional view of the essential part in the manufacturing process of the semiconductor chip subsequent to FIG. 29; FIG. 31 is an essential part cross sectional view of the semiconductor chip during a manufacturing step following FIG. 30; FIG. 32 is an essential part cross sectional view of the semiconductor chip during a manufacturing step following FIG. 31; FIG. 33 is an essential part cross sectional view of the semiconductor chip during a manufacturing step following FIG. 32; FIG. 34 is an essential part cross sectional view of the semiconductor chip during a manufacturing step following FIG. 33; FIG. 35 is an essential part cross sectional view of the semiconductor chip during a manufacturing step following FIG. 34; FIG. 36 is an essential part cross sectional view of the same manufacturing step of the semiconductor chip as FIG. 35; It is a graph which shows the result of having investigated the correlation with the thickness of a pillar electrode, and the stress added to an interlayer insulation film from a pillar electrode by simulation. It is a graph which shows the result of having investigated the correlation of the diameter of a pillar electrode, and the stress added to an interlayer insulation film from a pillar electrode by simulation. FIG. 5 is a plan view of relevant parts of the semiconductor device of FIG. 4; It is a graph which shows the result of having investigated the correlation with the thickness of a semiconductor substrate, and the stress added to an interlayer insulation film from a pillar electrode by simulation. It is principal part sectional drawing of the semiconductor device of a 1st modification. It is a principal part top view of the semiconductor device of the 1st modification. It is an explanatory view for explaining an effect of a semiconductor device of the 1st modification. It is a principal part top view of the semiconductor device of the 2nd modification.

  In the following embodiments, when it is necessary for the sake of convenience, it will be described by dividing into a plurality of sections or embodiments, but they are not unrelated to each other unless specifically stated otherwise, one is the other And some or all of the variations, details, and supplementary explanations. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), it is particularly pronounced and clearly limited to a specific number in principle. It is not limited to the specific number except for the number, and may be more or less than the specific number. Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily essential unless explicitly stated or considered to be obviously essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships and the like of components etc., the shapes thereof are substantially the same unless particularly clearly stated and where it is apparently clearly not so in principle. It is assumed that it includes things that are similar or similar to etc. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments will be described in detail based on the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repetitive description thereof will be omitted. Further, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly required.

  In the drawings used in the embodiments, hatching may be omitted to make the drawing easy to see even if it is a sectional view. Further, even a plan view may be hatched to make it easy to see the drawing.

Embodiment
<About the whole structure of the semiconductor chip>
FIG. 1 is an overall plan view of a semiconductor chip CP of the present embodiment, showing an example of the layout of pillar electrodes PL in the semiconductor chip CP. FIG. 2 is a conceptual cross-sectional view of the semiconductor chip CP. The cross-sectional view of the semiconductor chip CP taken along line A1-A1 of FIG. 1 substantially corresponds to FIG.

  The semiconductor chip CP of the present embodiment has an upper surface which is one main surface, and a back surface (lower surface) which is the main surface opposite to the upper surface. In FIG. 1, the upper surface of the semiconductor chip CP It is shown. In the semiconductor chip CP, the main surface on the pad PD or the side on which the pillar electrode PL is formed on the pad PD is called the upper surface of the semiconductor chip CP, and the main surface on the opposite side to the upper surface is the back surface of the semiconductor chip CP. It shall be called.

  As shown in FIGS. 1 and 2, the semiconductor chip CP has a plurality of pads (pad electrodes, electrode pads, bonding pads) PD on the upper surface side, and a plurality of pillar electrodes formed respectively on the plurality of pads PD. (Cu pillar, columnar electrode) PL is provided. Each pillar electrode PL protrudes from the top surface of the semiconductor chip CP. Therefore, the pillar electrode PL can also be regarded as a protruding electrode.

  Since the plurality of pillar electrodes PL are respectively formed on the plurality of pads PD of the semiconductor chip CP, the arrangement of the pads PD and the arrangement of the pillar electrodes PL in the semiconductor chip CP are the same in plan view. That is, the pad PD and the pillar electrode PL formed thereon are paired. The pad PD and the pillar electrode PL formed thereon function as an external connection terminal of the semiconductor chip CP. A solder layer SD1 described later is formed on the tip end surface (upper surface) of each pillar electrode PL, but the solder layer SD1 is not shown in FIG. In the pillar electrode PL, the surface (main surface) opposite to the side connected to the pad PD is the tip surface (upper surface) of the pillar electrode PL.

  In another embodiment, the plurality of pads PD of the semiconductor chip CP include not only pads (PD) on which the pillar electrodes PL are formed but also pads (PD) on which the pillar electrodes PL are not formed. possible. In this case, the pad (PD) on which the pillar electrode PL is not formed is entirely covered with an insulating film PA described later. That is, according to the electrical characteristics (ground characteristics and the like), a part of the plurality of pads PD of the semiconductor chip CP is covered with an insulating film PA to be described later, whereby a wiring board CB to be described later is provided. It is also possible to use a pad which is not electrically connected to the terminal TE.

  The planar shape of the semiconductor chip CP is a quadrangle, more specifically, a rectangle, but the corners of the rectangle may be rounded. In the case of FIG. 1, the plurality of pillar electrodes PL are arranged in an array (in a matrix) on the upper surface (substantially the entire upper surface) of the semiconductor chip CP. That is, in the case of FIG. 1, the plurality of pillar electrodes PL are provided in an area array arrangement on the upper surface of the semiconductor chip CP.

  Further, in the arrangement of the pillar electrodes PL (array arrangement), the plurality of pillar electrodes PL can be arranged in a so-called staggered arrangement by shifting the arrangement by 1⁄2 pitch for each row. The sequence case is shown in FIG. Similarly to FIG. 1, FIG. 3 is also a whole plan view of the semiconductor chip CP, and shows another layout example of the pillar electrode PL in the semiconductor chip CP.

<Structure of Semiconductor Device>
4 and 5 are plan views showing the semiconductor device PKG of the present embodiment, FIG. 4 shows a top view of the semiconductor device PKG, and FIG. 5 shows a bottom view of the semiconductor device PKG. There is. FIG. 6 is a cross-sectional view showing the semiconductor device PKG of the present embodiment, and the cross-sectional view of the semiconductor device PKG taken along line A2-A2 in FIGS. 4 and 5 substantially corresponds to FIG. FIG. 7 is a cross-sectional view of main parts of the semiconductor device PKG of the present embodiment, and an enlarged view of a region RG1 surrounded by a dotted line in FIG. 6 is shown. That is, FIG. 7 corresponds to an enlarged view of a region in the vicinity of a bonding portion between the pillar electrode PL of the semiconductor chip CP and the terminal TE of the wiring substrate CB. 8 is a top view of the wiring board CB used in the semiconductor device PKG, FIG. 9 is a bottom view of the wiring board CB, FIG. 10 is a cross-sectional view of the wiring board CB, and FIG. FIG. 7 is a cross-sectional view of main parts of the wiring board CB. A cross-sectional view of the wiring board CB taken along line A3-A3 in FIGS. 8 and 9 substantially corresponds to FIG. In FIG. 8, a region CY indicated by a dotted line corresponds to a region (chip mounting region) in which the semiconductor chip CP is mounted. 11 corresponds to an enlarged view of a region RG2 surrounded by a dotted line in FIG. 6 and FIG. 10 are the same cross sections, and FIG. 7 and FIG. 11 are the same cross sections.

  The semiconductor device PKG of the present embodiment shown in FIGS. 4 to 7 is a semiconductor device in the form of a semiconductor package provided with a semiconductor chip CP.

  As shown in FIGS. 4 to 7, the semiconductor device (semiconductor package) PKG of the present embodiment includes a wiring board CB, a semiconductor chip CP mounted (arranged) on the upper surface CBa of the wiring board CB, and a semiconductor There is a resin part (underfill resin) UFR that fills the gap between the chip CP and the wiring board CB, and a plurality of solder balls (external terminals, bump electrodes, solder bumps) BL provided on the lower surface CBb of the wiring board CB. doing.

  In the semiconductor device PKG, the semiconductor chip CP is flip-chip mounted on the upper surface CBa of the wiring substrate CB. That is, in the semiconductor chip CP, the back surface side of the semiconductor chip CP is directed upward, and the top surface of the semiconductor chip CP faces the top surface CBa of the wiring substrate CB, with the plurality of pillar electrodes PL interposed therebetween. It is mounted (implemented) on top. Therefore, the semiconductor chip CP is face-down bonded to the upper surface CBa of the wiring substrate CB.

  The plurality of pillar electrodes PL on the upper surface of the semiconductor chip CP are respectively solder layers (solders) on the plurality of terminals (land, conductive land, bonding lead, bonding finger, substrate side terminal, electrode) TE on the upper surface CBa of the wiring substrate CB. Material, solder part) SD is joined. That is, the solder layer SD made of solder (solder material) is interposed between the pillar electrode PL and the terminal TE, and the pillar electrode PL and the terminal TE are joined by the solder layer SD and electrically connected. It is done. Therefore, the plurality of pillar electrodes PL on the upper surface of the semiconductor chip CP are electrically and mechanically connected to the plurality of terminals TE on the upper surface CBa of the wiring substrate CB via the solder layers SD. Accordingly, the plurality of pads PD of the semiconductor chip CP are electrically connected to the plurality of terminals TE of the upper surface CBa of the wiring substrate CB via the pillar electrode PL and the solder layer SD. Thus, the semiconductor integrated circuit formed in the semiconductor chip CP is electrically connected to the terminal TE on the upper surface CBa of the wiring substrate CB via the pad PD and the pillar electrode PL.

  In the present application, the term "solder" or "solder material" is not limited to an alloy containing tin and lead, and includes lead-free solder (lead-free solder). As the lead-free solder (lead-free solder) used for flip chip bonding, an alloy containing one or more elements of silver, zinc, copper, nickel, bismuth, and antimony with respect to tin is preferably used.

  In the semiconductor device PKG, a resin portion UFR as an underfill resin is filled between the semiconductor chip CP and the upper surface CBa of the wiring substrate CB. The resin portion UFR can seal and protect the connection portion between the pillar electrode PL of the semiconductor chip CP and the terminal TE of the wiring board CB. Further, the resin portion UFR can buffer that a load due to the difference in the thermal expansion coefficient between the semiconductor chip CP and the wiring substrate CB is applied to the connection portion between the pillar electrode PL and the terminal TE. Thereby, the reliability of the semiconductor device PKG can be improved. The resin part UFR is made of, for example, a resin material such as an epoxy resin or a silicone resin (for example, a thermosetting resin material), and can also contain a filler (such as silica).

  The wiring substrate (package substrate) CB has a rectangular (square) planar shape intersecting with the thickness, and has the upper surface CBa which is one main surface and the lower surface CBb which is the main surface opposite to the upper surface CBa. doing. In the chip mounting region (the region for mounting the semiconductor chip CP) on the upper surface CBa of the wiring substrate CB, the plurality of terminals TE are arranged in an arrangement corresponding to the arrangement of the pillar electrodes PL on the upper surface of the semiconductor chip CP. . That is, when the semiconductor chip CP is mounted on the chip mounting region (CY) of the upper surface CBa of the wiring substrate CB, the plurality of pillar electrodes PL of the semiconductor chip CP and the plurality of terminals TE of the wiring substrate CB face each other. A plurality of terminals TE are arranged in the chip mounting area of the upper surface CBa of the wiring board CB.

  Therefore, the arrangement of the terminals TE in the chip mounting region (CY) of the upper surface CBa of the wiring substrate CB is the same as the arrangement of the pillar electrodes PL in the upper surface of the semiconductor chip CP. Therefore, as shown in FIG. 1, when the plurality of pillar electrodes PL are arranged in an array on the upper surface of the semiconductor chip CP, the chip mounting region of the upper surface CBa of the wiring substrate CB (FIG. 8) In CY), the plurality of terminals TE are arranged in an array. Further, as shown in FIG. 3, when the plurality of pillar electrodes PL are arranged in a staggered arrangement on the upper surface of the semiconductor chip CP, the chip mounting region (CY) of the upper surface CBa of the wiring substrate CB is ), The plurality of terminals TE are also arranged in a staggered arrangement. Similarly to FIG. 8, FIG. 12 is also a top view of the wiring board, and shows a layout example of the terminals TE in the wiring board CB when the semiconductor chip of FIG. 3 is mounted.

  The chip mounting area on the upper surface CBa of the wiring substrate CB means the region on the upper surface CBa of the wiring substrate CB on which the semiconductor chip CP is mounted, at the stage after mounting the semiconductor chip CP on the upper surface CBa of the wiring substrate CB. That is, it corresponds to a region of the upper surface CBa of the wiring substrate CB overlapping with the semiconductor chip CP in plan view. Further, the chip mounting area on the upper surface CBa of the wiring substrate CB means that the semiconductor chip CP is mounted later on the upper surface CBa of the wiring substrate CB at a stage before mounting the semiconductor chip CP on the upper surface CBa of the wiring substrate CB. It corresponds to the area to be planned (the chip mounting planned area). Therefore, the chip mounting area on the upper surface CBa of the wiring board CB refers to the same area before and after mounting the semiconductor chip CP. That is, in the upper surface CBa of the wiring substrate CB, the area overlapping with the semiconductor chip CP in plan view when the semiconductor chip CP is mounted is the chip mounting area regardless of whether the semiconductor chip CP is mounted or not. Here, the term “plan view” refers to the case of viewing in a plane parallel to the upper surface CBa of the wiring board CB.

  Further, FIG. 14 described later shows a wiring board CB used for manufacturing the semiconductor device PKG. In the wiring board CB shown in FIG. 14 described later, the solder layer SD2 is formed on the terminal TE on the upper surface CBa of the wiring board CB, but in the manufactured semiconductor device PKG shown in FIGS. The solder layer SD2 on the terminal TE of the substrate CB and the solder layer SD1 formed on the pillar electrode PL of the semiconductor chip CP before mounting are integrated by melting and resolidification to form a solder layer SD. . In the semiconductor device PKG, the pillar electrode PL of the semiconductor chip CP is bonded and fixed to the terminal TE of the wiring substrate CB via the solder layer SD.

  In the semiconductor device PKG, a plurality of conductive lands (electrodes, pads, terminals) LA for connecting the solder balls BL are formed on the lower surface CBb of the wiring board CB.

  The wiring board CB is, for example, a multilayer wiring board (multilayer board) in which a plurality of insulator layers (dielectric layers) and a plurality of conductor layers (wiring layers, conductor pattern layers) are laminated and integrated. The terminal TE on the upper surface CBa of the wiring board CB is electrically connected to the land LA on the lower surface CBb of the wiring board CB via the wiring of the wiring board CB or the via wiring formed inside the via of the wiring board CB. ing.

  In FIGS. 6, 7 and 10, for simplification of the drawings, the terminal TE on the upper surface CBa of the wiring board CB and the land LA on the lower surface CBb of the wiring board CB and the resist on the upper surface CBa side of the wiring board CB. Base layer (base layer (base layer) except for the layer SR1 and the resist layer SR2 on the lower surface CBb side of the wiring substrate CB, without dividing the plurality of insulator layers and the wiring layers constituting the wiring substrate CB into individual layers. ) Shown as BS. For this reason, in FIG. 6, FIG. 7 and FIG. 10, the terminal TE is formed on the upper surface of the base layer BS constituting the wiring substrate CB, and the land LA is formed on the lower surface of the base layer BS. The base material layer BS actually has a laminated structure including a plurality of insulator layers and a wiring layer interposed between the plurality of insulator layers. That is, although the wiring board CB has a plurality of conductor layers (wiring layer, conductor pattern layer), a plurality of terminals TE are formed on the uppermost conductor layer of the plurality of conductor layers, A plurality of lands LA are formed in the lowermost conductor layer of the plurality of conductor layers.

  A resist layer (solder resist layer, solder resist layer) SR1 which is an insulating film (insulation layer) is formed on the uppermost layer of the wiring board CB, and the terminal TE is exposed from the opening OP1 of the resist layer SR1. There is. That is, the resist layer SR1 is a film (insulating film) of the uppermost layer of the wiring board CB. In the lowermost layer of the wiring board CB, a resist layer (solder resist layer, solder resist layer) SR2 which is an insulating film (insulation layer) is formed, and the land LA is exposed from the opening OP2 of the resist layer SR2. It is done. The resist layers SR1 and SR2 are both insulating films that function as solder resist layers.

  That is, a conductor layer including a plurality of terminals TE is formed on the upper surface of base material layer BS constituting wiring substrate CB, and resist layer SR1 is formed on the upper surface of base material layer BS to cover the conductor layer. The resist layer SR1 is formed and constitutes the uppermost layer of the wiring board CB, but each terminal TE is exposed from the opening OP1 of the resist layer SR1. In plan view, the opening OP1 is included in the terminal TE, and the plane dimension (plane area) of the opening OP1 is smaller than the plane dimension (plane area) of the terminal TE. Therefore, the outer peripheral portion of each terminal TE is covered with the resist layer SR1, and the vicinity of the center of each terminal TE is exposed from the opening OP1 of the resist layer SR1 without being covered with the resist layer SR1.

  The upper surface CBa of the wiring board CB is mainly constituted by the upper surface SR1a of the resist layer SR1 of the wiring board CB. The upper surface SR1a of the resist layer SR1 is a surface (main surface) opposite to the base material layer BS. Therefore, the upper surface SR1a of the resist layer SR1 is a main surface on the side facing the semiconductor chip CP in a state where the semiconductor chip CP is mounted on the wiring substrate CB.

  The terminal TE is formed of a laminated film of a copper (Cu) layer TE1 and a nickel (Ni) layer TE2 on the copper layer TE1. The nickel layer TE2 is a plating layer (nickel plating layer) formed by a plating method, and is formed on the copper layer TE1 in a portion exposed from the opening OP1 of the resist layer SR1. This is to form a nickel plating layer to be a nickel layer TE2 on the copper layer TE1 of the portion exposed from the opening OP1 after forming the resist layer SR1 having the opening OP1 in manufacturing the wiring substrate CB Because Therefore, in each terminal TE, the nickel layer TE2 is not formed over the entire top surface of the copper layer TE1, but is formed over the copper layer TE1 in a portion exposed from the opening OP1, and the resist layer SR1. The nickel layer TE2 is not formed on the copper layer TE1 of the portion covered with For this reason, each terminal TE is not covered with the resist layer SR1, and the portion exposed from the opening OP1 has a laminated structure of the copper layer TE1 and the nickel layer TE2 thereon, but the resist layer The portion covered with SR1 consists of a copper layer TE1.

  Further, a conductor layer including a plurality of lands LA is formed on the lower surface of the base layer BS constituting the wiring substrate CB, and a resist layer SR2 is formed on the lower surface of the base layer BS so as to cover the conductor layer. Although the resist layer SR2 is formed and constitutes the lowermost layer of the wiring substrate CB, each land LA is exposed from the opening OP2 of the resist layer SR2. In plan view, the opening OP2 is included in the land LA, and the planar dimension (planar area) of the opening OP2 is smaller than the planar dimension (planar area) of the land LA. Therefore, the outer peripheral portion of each land LA is covered with the resist layer SR2, and the vicinity of the center of each land LA is exposed from the opening OP2 of the resist layer SR2 without being covered with the resist layer SR2.

  In the wiring substrate CB, the openings OP1 of the resist layer SR1 are provided in the chip mounting region in the same arrangement as the arrangement of the terminals TE, and thus in the same arrangement as the arrangement of the terminals TE of the semiconductor chip CP. Therefore, a plurality of openings OP1 of the resist layer SR1 are formed in the chip mounting region of the wiring substrate CB, and one terminal TE is exposed from one opening OP1.

  On the lower surface CBb of the wiring board CB, the lands LA are arranged in an array (area array). Solder balls BL are connected (formed) to the lands LA as protruding electrodes. Therefore, in the semiconductor device PKG, the plurality of solder balls BL are arranged in an array on the lower surface CBb of the wiring board CB, and the plurality of solder balls BL are external terminals of the semiconductor device PKG (external It can function as a connection terminal).

  Each pillar electrode PL of the semiconductor chip CP is electrically connected to each terminal TE of the upper surface CBa of the wiring board CB via the solder layer SD, and further, the wiring board CB via wiring or via wiring of the wiring board CB. Are electrically connected to the land LA of the lower surface CBb and the solder ball BL connected to the land LA. In addition, the plurality of solder balls BL disposed on the lower surface CBb of the wiring board CB may include solder balls not electrically connected to the pillar electrodes PL of the semiconductor chip CP, and may be used for heat dissipation it can.

<About the manufacturing process of the semiconductor device>
Next, the manufacturing process of the semiconductor device PKG of the present embodiment will be described. FIG. 13 is a process flow diagram showing a manufacturing process of the semiconductor device PKG of the present embodiment. 14 to 19 are cross-sectional views showing the manufacturing process of the semiconductor device of the present embodiment. 14 to 16, 18 and 19 show cross sections corresponding to FIG. FIG. 17 is a partial enlarged cross-sectional view showing a part of FIG. 16 in an enlarged manner, and an enlarged view of a region RG3 surrounded by a dotted line in FIG. 17 is shown.

  In order to manufacture the semiconductor device PKG, first, the semiconductor chip CP and the wiring board CB are prepared (prepared) (steps S1 and S2 in FIG. 13).

  The semiconductor chip CP is shown in FIGS. 1 to 3 above, and as described above, the semiconductor chip CP includes a plurality of pads PD and a plurality of pillar electrodes PL respectively formed on a plurality of pads PD. Have.

  The wiring board CB is shown in FIGS. 8 to 11, and as described above, the wiring board CB is formed on the plurality of terminals TE formed in the chip mounting area of the upper surface CBa and the lower surface CBb. And a plurality of lands LA.

  The wiring board CB can be manufactured by various manufacturing methods. For example, the wiring board CB can be manufactured using a build-up method, a subtractive method, a printing method, a sheet lamination method, a semi-additive method, an additive method, or the like.

  Even if the semiconductor chip CP is prepared in step S1 first and then the wiring board CB is prepared in step S2, or even if the wiring board CB is prepared in step S2 first and then the semiconductor chip CP is prepared in step S1, Alternatively, step S1 and step S2 may be performed simultaneously to prepare the wiring board CB and the semiconductor chip CP simultaneously.

  In the wiring board CB used for manufacturing the semiconductor device PKG, as shown in FIG. 14, a solder layer (solder material, solder portion) SD2 made of solder (solder material) on the terminal TE on the upper surface CBa of the wiring board CB. Is formed. That is, the wiring board CB in which the solder layer SD2 is formed on the terminal TE is prepared (manufactured) in step S2.

  As another mode, after preparing the wiring board CB in which the solder layer SD2 is not formed on the terminals TE in step S2, and before performing the flip chip mounting process of step S3 described later, the terminals TE of the wiring board CB. The solder layer SD2 can also be formed thereon.

  The solder layer SD2 is formed on the terminal TE in a portion exposed from the opening OP1 of the resist layer SR1, and thus is formed on the nickel layer TE2 that constitutes the terminal TE. The solder layer SD2 can be formed, for example, using a plating method.

  Further, in the semiconductor chip CP used for manufacturing the semiconductor device PKG, as also shown in FIG. 15, FIG. 20, FIG. 22, FIG. 35 and FIG. 36 described later, each of the plurality of pillar electrodes PL of the semiconductor chip CP. The solder layer SD1 is formed on the tip surface. That is, the semiconductor chip CP in which the solder layer SD1 is formed on the pillar electrode PL is prepared (manufactured) in step S1.

  Next, a flip chip connection process is performed (step S3 in FIG. 13). Specifically, step S3 can be performed as follows.

  That is, as shown in FIG. 15, with a tool (not shown) above the chip mounting planned area of the upper surface CBa of the upper surface CBa of the upper surface CBa in a direction in which the upper surface of the semiconductor chip CP faces the upper surface CBa of the wiring substrate CB. The held semiconductor chip CP is disposed. Then, the semiconductor chip CP held by the tool is brought close to the upper surface CBa of the wiring substrate CB, and the solder layer SD1 on the tip surface of the pillar electrode PL of the semiconductor chip CP is brought into contact with the solder layer SD2 on the terminal TE of the wiring substrate CB. At this time, the semiconductor chip CP is aligned with the wiring substrate CB such that the plurality of pillar electrodes PL of the semiconductor chip CP respectively face the plurality of terminals TE of the wiring substrate CB. At this time, at least one of the solder layer SD1 and the solder layer SD2 may be heated in advance to have a hardness that causes deformation after contact.

  Next, the solder layer SD1 and the solder layer SD2 are heated to the melting point or more. In the case of heating with the solder material layer D1 and the solder layer SD2 in contact with each other, if the semiconductor chip CP is heated, the solder layer SD2 can also be heated by heat transfer from the solder layer SD1. When the solder layer SD1 and the solder layer SD2 respectively melt, the solder material forming the solder layer SD1 and the solder material forming the solder layer SD2 melt and integrate. Thereafter, the molten solder is cooled and solidified to form a solder layer SD connecting the pillar electrode PL and the terminal TE. The solder layer SD is composed of the melted and re-solidified solder layers SD1, SD2. The solder layer SD intervenes between the pillar electrode PL of the semiconductor chip CP and the terminal TE of the wiring substrate CB to electrically and mechanically connect the pillar electrode PL of the semiconductor chip CP and the terminal TE of the wiring substrate CB. Do. This stage is shown in FIG.

  Further, when the solder layer SD1 and the solder layer SD2 are melted and integrated, the integrated molten solder is deformed to have a physically stable shape by surface tension, that is, it has a shape similar to a spherical shape. Become. Therefore, the solder layer SD formed by solidifying the molten solder has a shape similar to a spherical shape at the height position between the resist layer SR1 of the wiring substrate CB and the tip surface of the pillar electrode PL ( See Figure 17).

  Thus, the flip chip connection process is performed, and the semiconductor chip CP is mounted on the upper surface CBa of the wiring substrate CB, and the plurality of pillar electrodes PL of the semiconductor chip CP are connected to the plurality of terminals TE of the wiring substrate CB. Each is joined via the solder layer SD. Thus, the semiconductor chip CP is fixed to the wiring board CB.

  In addition, at the time of flip chip connection, a flux can be suitably used for removing the metal oxide film of the connection portion. For example, before mounting the semiconductor chip CP on the wiring board CB, flux is supplied onto the upper surface CBa (especially, on the terminal TE) of the wiring board CB. Thereafter, the semiconductor chip CP is disposed on the wiring substrate CB, and then a solder reflow process (a heating process of melting the solder layers SD1 and SD2 to form the solder layer SD) may be performed, and then the cleaning process may be performed.

  Next, as shown in FIG. 18, a resin portion UFR is formed as an underfill resin that fills the space between the semiconductor chip CP and the wiring board CB (step S4 in FIG. 13). Step S4 can be performed, for example, as follows.

  That is, a liquid or paste resin material is supplied (filled, injected) between the semiconductor chip CP and the upper surface CBa of the wiring substrate CB. This resin material contains a thermosetting resin material and can further contain a filler (such as silica particles). The resin material supplied between the semiconductor chip CP and the upper surface CBa of the wiring substrate CB spreads in the space between the semiconductor chip CP and the upper surface CBa of the wiring substrate CB by capillary action. Then, by curing the resin material by heating or the like, a resin portion UFR made of the cured resin material can be formed.

  As another mode, before placing the semiconductor chip CP on the wiring board CB (that is, before performing the above step S3), the liquid or paste resin material is previously formed on the chip mounting planned area of the upper surface CBa of the wiring board CB. Alternatively, after the pillar electrode PL of the semiconductor chip CP is connected to the terminal TE of the wiring substrate CB by flip chip connection, the resin material may be cured to form the resin portion UFR. In that case, there is no need to carry out the step of supplying the resin material between the semiconductor chip CP and the upper surface CBa of the wiring substrate CB in step S4, and the process already exists between the semiconductor chip CP and the upper surface CBa of the wiring substrate CB. The step of curing the resin material by heating is performed.

  Next, as shown in FIG. 19, solder balls BL are connected (joined and formed) to the lands LA on the lower surface CBb of the wiring board CB (step S5 in FIG. 13).

  In the solder ball BL connecting step of step S5, for example, the lower surface CBb of the wiring board CB is directed upward, and the solder balls BL are arranged (mounted) on the plurality of lands LA of the lower surface CBb of the wiring board CB. Temporary fixing and reflow processing (solder reflow processing, heat treatment) can be performed to melt the solder, and the solder balls BL and the lands LA on the lower surface CBb of the wiring substrate CB can be joined. Thereafter, if necessary, a cleaning process may be performed to remove the flux or the like attached to the surface of the solder ball BL. Thus, the solder balls BL as external terminals (terminals for external connection) of the semiconductor device PKG are joined (formed).

  In the present embodiment, the case where solder balls BL are joined as external terminals of semiconductor device PKG has been described, but the present invention is not limited to this. For example, instead of solder balls BL, lands LA may be formed by printing. Alternatively, solder may be supplied to form external terminals (bump electrodes, solder bumps) made of the solder of the semiconductor device PKG. In this case, solder is supplied onto the plurality of lands LA on the lower surface CBb of the wiring board CB, and then solder reflow processing is performed, and external terminals (bump electrodes, solder bumps) made of solder on the plurality of lands LA. Can be formed. Alternatively, external terminals (bump electrodes) can be formed on the lands LA by plating or the like.

  Thus, in step S5, external connection terminals (here, solder balls BL) are formed on the plurality of lands LA on the lower surface CBb of the wiring board CB.

  Thus, the semiconductor device PKG is manufactured.

  In addition, as another embodiment, a multi-piece wiring board can be used as a wiring board used for manufacturing the semiconductor device PKG. In this case, in step S2, a wiring board matrix in which a plurality of the wiring boards CB are integrally connected in an array is prepared as a multi-piece wiring board. The wiring board matrix has a plurality of semiconductor device regions, and each semiconductor device region corresponds to a region from which one semiconductor device PKG is obtained. Then, in the step S3, the flip chip connection process is performed on the plurality of semiconductor device regions of the wiring substrate matrix, and in the step S4, the resin portion UFR forming process is performed on the plurality of semiconductor device regions of the wiring substrate matrix In the step S5, a connection process of solder balls is performed on a plurality of semiconductor device regions of the wiring substrate matrix. Thereafter, the wiring substrate matrix is cut and divided into semiconductor device regions, whereby semiconductor devices PKG can be manufactured from the individual semiconductor device regions.

<About the structure of the semiconductor chip>
FIG. 20 is a cross-sectional view of essential parts of the semiconductor chip CP of the present embodiment, and shows a cross section across the pad PD and the pillar electrode PL formed thereon. FIG. 21 is a plan view of relevant parts of the semiconductor chip CP of the present embodiment, and is a plan view in the vicinity of the pad PD formation region. FIG. 21 shows the planar positions of the pad PD, the pillar electrode PL, the opening OP3a, the opening OP3b, and the opening SH. FIG. 20 substantially corresponds to the cross-sectional view at the position of line A4-A4 in FIG. Further, FIG. 22 described later substantially corresponds to the cross-sectional view at the position of line A5-A5 in FIG. Although the structure below the interlayer insulating film IL6 is not shown in FIG. 20, the structure below the interlayer insulating film IL6 is also shown in FIG. 22 described later.

  As shown in FIG. 20, the pad PD is formed on the interlayer insulating film IL6, and the insulating film PA is formed on the interlayer insulating film IL6 so as to cover a part of the pad PD. A part of PD is exposed from an opening OP3 provided in the insulating film PA. That is, although pad PD is exposed from opening OP3, pad PD of a portion which does not overlap opening OP3 by plane view is covered with insulating film PA. Specifically, the central part of the pad PD is not covered with the insulating film PA, and the outer peripheral part of the pad PD is covered with the insulating film PA.

  The insulating film PA is a film (insulating film) of the uppermost layer of the semiconductor chip CP, and in particular, the resin film PA2 constituting the insulating film PA is a film (insulating film) of the CP uppermost layer of the semiconductor chip. The insulating film PA can function as a surface protective film of the semiconductor chip CP. The insulating film PA (particularly, the insulating film PA1) can also be regarded as a passivation film.

  The insulating film PA is formed of a laminated film of an insulating film PA1 and a resin film (organic insulating film) PA2 over the insulating film PA1. The insulating film PA1 is an insulating film that functions as a passivation film, and is made of an inorganic insulating film. As the insulating film PA, a silicon nitride film or a silicon oxynitride film can be suitably used. Since the silicon nitride film or the silicon oxynitride film is an insulating film having low hygroscopicity, the moisture resistance of the semiconductor chip CP can be improved by using a silicon nitride film or a silicon oxynitride film as the insulating film PA1. The resin film PA2 is preferably a polyimide film (polyimide resin film). A polyimide (polyimide) film is a polymer containing an imide bond in the repeating unit, and is a type of organic insulating film. By using the resin film PA2 as the film of the uppermost layer (uppermost surface) of the semiconductor chip CP, advantages such as easy handling of the semiconductor chip CP (and easy handling) can be obtained.

  Since the insulating film PA1 and the resin film PA2 are respectively insulating films, the insulating film PA is a stacked insulating film in which a plurality of insulating films (specifically, two insulating films of the insulating film PA1 and the resin film PA2) are stacked. It can also be regarded as a membrane. In the present application, the laminated insulating film means a laminated film in which a plurality of insulating films are laminated.

  The insulating film PA has an opening OP3 that exposes at least a part of the pad PD. However, since the insulating film PA is a laminated film of the insulating film PA1 and the resin film PA2, the opening of the insulating film PA OP3 is formed by the opening OP3b of the resin film PA2 and the opening OP3a of the insulating film PA1.

  The opening OP3a penetrates the insulating film PA1, and is included in the pad PD in a plan view. Therefore, the planar dimension (planar area) of the opening OP3a is smaller than the planar dimension (planar area) of the pad PD, and the pad PD has a region overlapping the opening OP3a and a region not overlapping the opening OP3a. Specifically, the central part of the pad PD is not covered with the insulating film PA1 and exposed from the opening OP3a of the insulating film PA1, but the outer peripheral part of the pad PD is the insulating film PA1. It is covered.

  The opening OP3b penetrates the resin film PA2, and is included in the pad PD in a plan view. Therefore, the planar dimension (planar area) of the opening OP3b is smaller than the planar dimension (planar area) of the pad PD, and the pad PD has a region overlapping the opening OP3b and a region not overlapping the opening OP3b. Specifically, the central part of the pad PD is not covered with the resin film PA2, and is exposed from the opening OP3b of the resin film PA2, but the outer peripheral part of the pad PD is the resin film PA2. It is covered.

  In plan view, the opening OP3a and the opening OP3b at least partially overlap, and the overlapping region of the opening OP3a and the opening OP3b is located on the pad PD, and the opening OP3a and the opening The pad PD is exposed from the overlapping region with the OP 3 b.

  The opening OP3b of the resin film PA2 is preferably included in the opening OP3a of the insulating film PA1 in plan view. In this case, the planar dimension (planar area) of the opening OP3b is smaller than the planar dimension (planar area) of the opening OP3a, and the entire opening OP3b overlaps the opening OP3a in plan view, but the opening OP3a Has a region overlapping with the opening OP3b and a region not overlapping the opening OP3b.

  When the opening OP3b is included in the opening OP3a in plan view, the opening OP3 of the insulating film PA substantially matches the opening OP3b of the resin film PA2, and the inner wall of the opening OP3 of the insulating film PA The (side wall) is formed by the inner wall (side wall) of the opening OP3 b of the resin film PA2. If the opening OP3b is included in the opening OP3a in plan view, neither the insulating film PA1 nor the resin film PA2 is formed on the pad PD in the region inside the opening OP3b in plan view. The upper surface of the pad PD is exposed. If the opening OP3b is included in the opening OP3a in a plan view, the insulating film PA1 is not formed on the pad PD in the region inside the opening OP3a and outside the opening OP3b. The resin film PA2 is formed, and in the region outside the opening OP3a, the laminated film of the insulating film PA1 and the resin film PA2 over the insulating film PA1 is formed over the pad PD. It has become.

  The reason why the opening OP3b is preferably included in the opening OP3a in a plan view is as follows.

  That is, if the opening OP3b is included in the opening OP3a in plan view, the inner wall of the opening OP3 of the insulating film PA is formed by the inner wall of the opening OP3b of the resin film PA2, the pillar electrode PL is Although it is in contact with the resin film PA2, it is not in contact with the insulating film PA1. The insulating film PA1 is relatively hard in hardness, but the resin film PA2 is softer than the insulating film PA1. Although the pillar electrode PL is formed on the pad PD, application of the pillar electrode PL to the pillar electrode PL is performed by causing the soft resin film PA2 to be in contact and not to be in contact with the hard insulating film PA1. The soft (applied) stress can be easily relieved by the soft resin film PA2. Since the stress can be relaxed by the resin film PA2, the stress applied (acted) to the pillar electrode PL can be suppressed from being applied to the interlayer insulating film (IL1 to IL6) below the pillar electrode PL. Therefore, if the opening OP3b is included in the opening OP3a in plan view, stress applied to the interlayer insulating film (IL1 to IL6) below the pillar electrode PL from the pillar electrode PL can be reduced.

  In the manufactured semiconductor device PKG, the semiconductor chip CP is mounted on the upper surface CBa of the wiring substrate CB in a direction in which the upper surface of the semiconductor chip CP faces the upper surface CBa of the wiring substrate CB, that is, face down. There is. However, when referring to a component (for example, an interlayer insulating film or the like) in the semiconductor chip CP, the upper surface side of the semiconductor chip CP is directed upward regardless of whether the semiconductor chip CP is mounted on the wiring substrate CB or not. The back surface side of the semiconductor chip CP is described as the lower side. Therefore, the interlayer insulating films (IL to IL6) of the semiconductor chip CP are formed of the pillar electrodes PL before mounting the semiconductor chip CP on the wiring substrate CB and also after mounting the semiconductor chip CP on the wiring substrate CB. It can be said that it is located below the pillar electrode PL, not above.

  The planar shape of each of the openings OP3a and OP3b is preferably circular. In addition, although the planar shape of the pad PD is, for example, a quadrangular shape (more specifically, a rectangular shape), as another embodiment, the planar shape of the pad PD may be circular. The pad PD is preferably an aluminum pad mainly composed of aluminum.

  As the aluminum film used for the aluminum pad, not only a pure aluminum film but also a compound film or alloy film of Al (aluminum) and Si (silicon), or Al (aluminum) and Cu (copper) A compound film or alloy film, or a compound film or alloy film of Al (aluminum), Si (silicon) and Cu (copper), or the like can be suitably used. The composition ratio (content ratio) of Al (aluminum) in the aluminum film used for the aluminum pad is more preferably 50 atomic% or more (that is, Al rich) is 98 atomic% or more.

  The pillar electrode PL is formed on the pad PD exposed from the opening OP3 of the insulating film PA (that is, the opening OP3b of the resin film PA2).

  As shown in FIG. 35, the pillar electrode PL includes a seed layer SE and a copper (Cu) layer CL on the seed layer SE. The thickness of the seed layer SE is thinner than the thickness of the copper (Cu) layer CL, and the pillar electrode PL is mainly formed of the copper (Cu) layer CL. In addition, as shown in FIG. 36 described later, the pillar electrode PL includes the seed layer SE, the copper (Cu) layer CL on the seed layer SE, and the nickel (Ni) layer NL on the copper (Cu) layer CL. There is also a possibility. The seed layer SE is formed of a single layer or a plurality of metal layers, for example, a laminated film of a chromium (Cr) layer and a copper (Cu) layer on the chromium (Cr) layer.

  The solder layer SD1 is formed on the tip surface (upper surface) of the pillar electrode PL. The tip surface (upper surface) of the pillar electrode PL corresponds to the surface on the opposite side to the pad PD.

  In plan view, the planar dimension (planar area) of the pillar electrode PL is larger than the planar dimension (planar area) of the opening OP3 of the insulating film PA (that is, the opening OP3b of the resin film PA2). The opening OP3 of the film PA (that is, the opening OP3b of the resin film PA2) is included in a plan view (see FIG. 21). For this reason, in plan view, a part (peripheral part) of the pillar electrode PL overlaps the insulating film PA (resin film PA2). That is, although the pillar electrode PL is formed on the pad PD exposed from the opening OP3 of the insulating film PA (that is, the opening OP3b of the resin film PA2), a part (peripheral portion) of the pillar electrode PL is insulated It is located on (is over) the film PA (resin film PA2).

  The pillar electrode PL is a columnar electrode provided with a columnar solid shape. In the present embodiment, the planar shape of the pillar electrode PL is circular, and the pillar electrode PL has a cylindrical shape.

  The tip surface (upper surface) of the pillar electrode PL is substantially flat. The tip end surface (upper surface) of the pillar electrode PL is substantially parallel to the upper surface of the pad PD, and the tip end surface (upper surface) of the pillar electrode PL and the upper surface of the pad PD are of the semiconductor substrate SB constituting the semiconductor chip CP. It is substantially parallel to the main surface. The upper surface of the pad PD corresponds to the surface on the opposite side to the interlayer insulating film IL6.

  The solder layer SD1 formed on the tip surface of the pillar electrode PL has a dome shape. This is because, as described later, the solder layer SD1 is initially formed as a solder plating layer, and thereafter, the solder plating layer is melted and resolidified.

  The tip end surface of the pillar electrode PL protrudes more than the upper surface (main surface) PA2a of the insulating film PA. The upper surface PA2a of the insulating film PA is the same as the upper surface of the resin film PA2, and the upper surface PA2a of the insulating film PA and the upper surface of the resin film PA2 mean the same surface. For this reason, the upper surface PA2a of the insulating film PA is a main surface on the side facing the wiring substrate CB in a state where the semiconductor chip CP is mounted on the wiring substrate CB.

  Therefore, the pillar electrode PL integrally has a portion embedded in the opening OP3 of the insulating film PA (that is, the opening OP3b of the resin film PA2) and a portion protruding from the upper surface PA2a of the insulating film PA. doing. The planar dimension (planar area) of the portion of the pillar electrode PL that protrudes from the upper surface PA2a of the insulating film PA is the planar dimension (planar area) of the opening OP3 of the insulating film PA (that is, the opening OP3b of the resin film PA2). Greater than). That is, the portion of the pillar electrode PL embedded in the opening OP3 of the insulating film PA has a shape corresponding to the opening OP3 of the insulating film PA, but the insulating film PA of the pillar electrode PL The portion protruding from the upper surface PA2a of the second embodiment includes the opening OP3 of the insulating film PA (that is, the opening OP3b of the resin film PA2) in plan view. Therefore, the outer peripheral portion of the portion of the pillar electrode PL that protrudes from the upper surface PA2a of the insulating film PA is located on (is running over) the upper surface PA2a of the insulating film PA. The upper surface PA2a of the insulating film PA in a portion overlapping the pillar electrode PL in a plan view is in contact with the pillar electrode PL (more specifically, the seed layer SE configuring the pillar electrode PL). Further, the side wall of the opening OP3 of the insulating film PA (that is, the opening OP3b of the resin film PA2) is also in contact with the pillar electrode PL (more specifically, the seed layer SE configuring the pillar electrode PL).

  Reflecting that the planar shape of the opening OP3 of the insulating film PA (that is, the opening OP3b of the resin film PA2) is circular, the opening OP3 of the insulating film PA of the pillar electrode PL (that is, the resin film PA2 The planar shape of the portion embedded in the opening OP3b) is circular. Therefore, the three-dimensional shape of the portion of the pillar electrode PL embedded in the opening OP3 of the insulating film PA (that is, the opening OP3b of the resin film PA2) is cylindrical. In addition, reflecting that the planar shape of the opening OP4 of the later-described photoresist layer RP1 used for forming the pillar electrode PL is circular, from the top surface PA2a of the insulating film PA in the pillar electrode PL The planar shape of the protruding portion is circular. Therefore, the three-dimensional shape of the portion of the pillar electrode PL that protrudes from the upper surface PA2a of the insulating film PA is a cylindrical shape.

  As described above, the plurality of pillar electrodes PL are respectively formed (joined) on the plurality of pads PD of the semiconductor chip CP, and the solder layer SD1 is formed on the tip surfaces of the plurality of pillar electrodes PL.

  Next, the cross-sectional structure of the semiconductor chip CP including the structure below the interlayer insulating film IL6 will be described with reference to FIG. FIG. 22 is a cross-sectional view of main parts of the semiconductor chip CP according to the present embodiment, and shows the cross section of the semiconductor chip CP including the structure below the interlayer insulating film IL6 shown in FIG.

  In the semiconductor chip CP of the present embodiment, a semiconductor element such as a MISFET is formed on the main surface of the semiconductor substrate SB, and a wiring structure (multilayer wiring structure) including a plurality of wiring layers is formed on the semiconductor substrate SB. There is. Below, the structural example of semiconductor chip CP of this Embodiment is demonstrated concretely.

  As shown in FIG. 22, a semiconductor element such as a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed on a semiconductor substrate SB made of single crystal silicon or the like that constitutes the semiconductor chip CP of the present embodiment. Although a plurality of MISFETs are formed in the semiconductor substrate SB, two of them (in this case, n channel type MISFETs Qn and p channel type MISFETs Qp) are representatively shown in FIG.

  The element isolation region ST is formed on the main surface of the semiconductor substrate SB by STI (Shallow Trench Isolation) method or the like, and in the semiconductor substrate SB, the MISFET (Qn, Qn,) is formed in the active region defined by the element isolation region ST. Qp) is formed.

  For example, the p-type well PW and the n-type well NW are formed in the semiconductor substrate SB, the gate electrode G1 is formed over the p-type well PW via the gate insulating film GF, and the gate insulating film GF is formed over the n-type well NW. The gate electrode G2 is formed via. In the p-type well PW, n-type semiconductor regions NS for source and drain are formed, and in the n-type well NW, p-type semiconductor regions PS for source and drain are formed. An n-channel type MISFET Qn is formed by the gate electrode G1, the gate insulating film GF under the gate electrode G1, and the n-type semiconductor regions NS (source / drain regions) on both sides of the gate electrode G1. Further, a p-channel type MISFET Qp is formed by the gate electrode G2, the gate insulating film GF under the gate electrode G2, and the p-type semiconductor regions PS (source / drain regions) on both sides of the gate electrode G2.

  Here, although the MISFET is described as an example of the semiconductor element formed on the semiconductor substrate SB, in addition to this, a capacitive element, a resistive element, a memory element, or a transistor having another configuration is formed. It is also good. Further, although a single crystal silicon substrate is described as an example of the semiconductor substrate SB here, as another embodiment, an SOI (Silicon On Insulator) substrate or the like can be used as the semiconductor substrate SB.

  A wiring structure (multilayer wiring structure) including a plurality of interlayer insulating films and a plurality of wiring layers is formed on the semiconductor substrate SB.

  That is, on the semiconductor substrate SB, a plurality of interlayer insulating films IL1, IL2, IL3, IL4, and IL5 are formed, and the plurality of interlayer insulating films IL1, IL2, IL3, IL4, and IL5, the plug V1, the via portion V2, and V3 and V4 and wirings M1, M2, M3 and M4 are formed. Then, over the interlayer insulating film IL5, the interlayer insulating film IL6 is formed, and over the interlayer insulating film IL6, the pad PD is formed. A wire (not shown) in the same layer as the pad PD can also be formed on the interlayer insulating film IL6.

  Specifically, the interlayer insulating film IL1 is formed on the semiconductor substrate SB so as to cover the above-mentioned MISFETs (Qn, Qp), the plug V1 is embedded in the interlayer insulating film IL1, and the plug V1 is embedded. The interlayer insulating film IL2 is formed over the interlayer insulating film IL1, and the wiring M1 is embedded in the interlayer insulating film IL2. Then, over the interlayer insulating film IL2 in which the wiring M1 is embedded, the interlayer insulating film IL3 is formed, the wiring M2 is embedded in the interlayer insulating film IL3, and the interlayer insulating film IL3 is embedded in the wiring M2. A film IL4 is formed, and a wiring M3 is embedded in the interlayer insulating film IL4. Then, the interlayer insulating film IL5 is formed on the interlayer insulating film IL4 in which the wiring M3 is embedded, the wiring M4 is embedded in the interlayer insulating film IL5, and the interlayer insulating film IL5 is embedded on the interlayer insulating film IL5. A film IL6 is formed, and a pad PD is formed on the interlayer insulating film IL6. Each of the interlayer insulating films IL1 to IL6 can be a single-layer insulating film or a stacked film of a plurality of insulating films. Then, over the interlayer insulating film IL6, the insulating film PA is formed so as to cover the pad PD, and in the insulating film PA, an opening OP3 for exposing a part of the pad PD is formed. The pillar electrode PL is formed over the pad PD exposed from the opening OP3 of the insulating film PA (that is, the opening OP3b of the resin film PA2).

  The plug V1 is made of a conductor and disposed under the wiring M1. The plug V1 electrically connects the wiring M1 to various semiconductor regions formed in the semiconductor substrate SB, the gate electrodes G1 and G2, and the like.

  The via portion V2 is made of a conductor, is integrally formed with the wiring M2, is disposed between the wiring M2 and the wiring M1, and electrically connects the wiring M2 and the wiring M1. That is, the wiring M2 and the via portion V2 integrally formed with the wiring M2 are embedded in the interlayer insulating film IL3 by using the dual damascene method. As another mode, it is also possible to separately form the via portion V2 and the wiring M2 by using the single damascene method, and the same applies to the via portions V3, V4, and V5.

  The via portion V3 is made of a conductor, is integrally formed with the wiring M3, is disposed between the wiring M3 and the wiring M2, and electrically connects the wiring M3 and the wiring M2. That is, the wiring M3 and the via portion V3 integrally formed with the wiring M3 are embedded in the interlayer insulating film IL4 by using the dual damascene method.

  The via portion V4 is made of a conductor, is integrally formed with the wiring M4, is disposed between the wiring M4 and the wiring M3, and electrically connects the wiring M4 and the wiring M3. That is, in the interlayer insulating film IL5, the wiring M4 and the via portion V4 integrally formed with the wiring M4 are embedded by using the dual damascene method.

  In addition, although the wirings M1, M2, M3, and M4 are illustrated and described as damascene wirings (embedded wirings) formed by the damascene method here, the present invention is not limited to the damascene wirings, and the conductor film for the wiring is patterned. It can also be formed, for example, as an aluminum wiring.

  In the interlayer insulating film IL6, an opening (through hole, through hole) SH is formed at a position overlapping the pad PD in plan view, and a via V5 is formed in the opening SH (embedded) Yes). The via portion V5 is made of a conductor, is disposed between the pad PD and the wiring M4, and electrically connects the pad PD and the wiring M4. That is, the via portion V5 is embedded in the interlayer insulating film IL6 by using the single damascene method.

  Although the via portion V5 and the pad PD are separately formed in the present embodiment, the via portion V5 can be integrally formed with the pad PD as another form. When the via portion V5 is integrally formed with the pad PD, the via portion V5 is formed by embedding a part of the pad PD in the opening portion SH of the interlayer insulating film IL6.

  The configurations of the pad PD, the insulating film PA (including the openings OP3a and OP3b), and the pillar electrode PL are as described above with reference to FIGS. 20 and 21, and therefore the description thereof will not be repeated here. . Further, in FIG. 7, the region denoted by reference numeral CPB corresponds to the region (wiring structure formation region) below the interlayer insulating film IL6 in FIG. 22.

  The wiring structure (multilayer wiring structure) of the semiconductor chip CP includes a plurality of wiring layers and a plurality of interlayer insulating films (IL1 to IL6). It is preferable to use a low dielectric constant insulating film in one or more layers among IL1 to IL6). By using a low dielectric constant insulating film, parasitic capacitance between wires can be reduced. In particular, if low dielectric constant insulating films are used as the interlayer insulating films IL2, IL3, IL4, and IL5, parasitic capacitances between the wirings in the same layer and between the upper and lower wirings can be properly reduced in the wirings M1, M2, M3, and M4. be able to. Note that a low dielectric constant insulating film is an insulating film having a dielectric constant (relative dielectric constant) lower than the dielectric constant (relative dielectric constant) of silicon oxide, and is called a low dielectric constant film or a low-k film. It can also be done.

<About the manufacturing process of the semiconductor chip>
The manufacturing process of the semiconductor chip CP of the present embodiment will be described with reference to FIGS. 23 to 36 are main-portion cross-sectional views of the semiconductor chip CP in the present embodiment during the manufacturing process thereof.

  First, as shown in FIG. 23, a semiconductor substrate (semiconductor wafer) SB made of, for example, p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm is prepared (prepared). At this stage, the semiconductor substrate SB is in the state of the semiconductor wafer.

  Next, the element isolation region ST is formed in the semiconductor substrate SB using the STI method, the p-type well PW and the n-type well NW are formed using the ion implantation method, and the p-type well PW and the n-type well NW are formed. The gate electrodes G1 and G2 are formed via the gate insulating film GF, and the n-type semiconductor region NS and the p-type semiconductor region PS are formed using an ion implantation method. Thereby, the n-channel type MISFET Qn and the p-channel type MISFET Qp are formed in the semiconductor substrate SB.

  Next, over the semiconductor substrate SB, the interlayer insulating film IL1 is formed so as to cover the MISFETs Qn and Qp, and contact holes are formed in the interlayer insulating film IL1 using photolithography technology and dry etching technology. The plug V1 is formed by embedding a conductive film in the

  Next, an interlayer insulating film IL2 is formed on the interlayer insulating film IL1 in which the plug V1 is embedded, and then the wiring M1 is embedded in the interlayer insulating film IL2 using a single damascene technique. Then, the interlayer insulating film IL3 is formed over the interlayer insulating film IL2 in which the wiring M1 is embedded, and then the wiring M2 and the via portion V2 are embedded in the interlayer insulating film IL3 using dual damascene technology. Then, an interlayer insulating film IL4 is formed over the interlayer insulating film IL3 in which the wiring M2 is embedded, and then the wiring M3 and the via portion V3 are embedded in the interlayer insulating film IL4 using dual damascene technology. Then, the interlayer insulating film IL5 is formed over the interlayer insulating film IL4 in which the wiring M3 is embedded, and then the wiring M4 and the via portion V4 are embedded in the interlayer insulating film IL5 using dual damascene technology.

  Next, an interlayer insulating film IL6 is formed over the interlayer insulating film IL5 in which the wiring M4 is embedded. Then, an opening SH is formed in the interlayer insulating film IL6 using a photolithography technique and an etching technique. When the opening SH is formed in the interlayer insulating film IL6, the upper surface of the wiring M4 is exposed at the bottom of the opening SH.

  Next, a conductive film for the via portion V5 is formed on the interlayer insulating film IL6 so as to fill the opening SH, and then a CMP (Chemical Mechanical Polishing) method, an etch back method, or the like is performed. The conductive film (conductive film for the via V5) outside the opening SH is removed to leave the conductive film (conductive film for the via V5) in the opening SH. Thereby, the via portion V5 formed of the conductive film (conductive film for the via portion V5) embedded in the opening portion SH can be formed.

  Although FIG. 23 shows a laminated structure from the semiconductor substrate SB to the interlayer insulating film IL6, FIGS. 24 to 36 in the following FIGS. 24 to 36 have structures lower than the interlayer insulating film IL6 for simplification of the drawing. Illustration is omitted. Although FIG. 23 shows a cross sectional area corresponding to FIG. 22 above, FIGS. 24 to 36 show cross sectional areas corresponding to FIG. 20 above, so FIG. 24 to FIG. The opening SH and the via portion V5 are not shown.

  Next, as shown in FIG. 24, the pad PD is formed on the interlayer insulating film IL6 in which the via portion V5 is embedded. For example, after forming a conductive film for pad PD on interlayer insulating film IL6 in which via portion V5 is buried, pad PD is formed by patterning this conductive film using photolithography technology and etching technology. can do. In addition, when patterning the conductive film for the pad PD, not only the pad PD but also a wire in the same layer as the pad PD can be formed. As a conductive film for pad PD, the above-mentioned aluminum film can be used. The thickness of the pad PD can be, for example, about 2 to 3 μm.

  Although the case where the via portion V5 and the pad PD are separately formed is illustrated and described here, it is also possible to integrally form the via portion V5 with the pad PD as another form. In that case, in the state where the via portion V5 is not formed, a conductive film for pad PD is formed on the interlayer insulating film IL6 including the inside of the opening SH, and then the conductive film is subjected to photolithography technology and etching technology. The pad PD is formed by using and patterning. Thus, the pad PD and the via portion V5 are integrally formed.

  Next, as shown in FIG. 25, over the interlayer insulating film IL6, the insulating film PA1 is formed so as to cover the pad PD. The insulating film PA1 is preferably made of a silicon nitride film or a silicon oxynitride film, and can be formed using a CVD (Chemical Vapor Deposition) method or the like. An HDP (High Density Plasma: High Density Plasma) -CVD method is particularly preferable as a method for forming the insulating film PA1. The thickness (formation thickness) of the insulating film PA1 can be, for example, about 0.1 to 2 μm. When the insulating film PA1 is formed, since the pad PD is covered with the insulating film PA1, the pad PD is not exposed.

  Next, as shown in FIG. 26, an opening OP3a is formed in the insulating film PA1. The opening OP3a is formed by selectively removing the insulating film PA1 on the pad PD, and the opening OP3a is formed so as to be included in the pad PD in a plan view. For example, after forming the insulating film PA1, a photoresist pattern (not shown) is formed on the insulating film PA1 by photolithography, and the insulating film PA1 is etched using the photoresist pattern as an etching mask. The opening OP3a can be formed in the insulating film PA1 by (dry etching). The opening OP3a is formed to penetrate the insulating film PA1, and at least a part of the pad PD is exposed from the opening OP3a.

  Also, as a conductive film for pad PD, a barrier conductive film (for example, a titanium film, a titanium nitride film, or a laminated film thereof), an aluminum film and a barrier conductive film (for example, a titanium film, a titanium nitride film, In some cases, the laminated film with the laminated film may be used to pattern the laminated film to form the pad PD. In that case, when the opening OP3a is formed in the insulating film PA1, the barrier conductor film (the barrier conductor film on the upper layer side) exposed at the bottom of the opening OP3a is also removed by etching, and the aluminum film constituting the pad PD is removed. It is preferable to expose from the opening OP3a.

  Next, as shown in FIG. 27, a resin film PA2 is formed over the insulating film PA1 including over the pad PD exposed from the opening OP3a. The resin film PA2 is formed over the entire main surface of the semiconductor substrate SB, and therefore, is formed over the insulating film PA1 and over the pad PD exposed from the opening OP3a of the insulating film PA1. At the stage before forming the resin film PA2, the pad PD was exposed from the opening OP3a of the insulating film PA1, but when the resin film PA2 was formed, the pad exposed from the opening OP3a of the insulating film PA1. Since the PD is covered with the resin film PA2, it is not exposed. A polyimide film or the like can be suitably used as the resin film PA2. The resin film PA2 can be formed, for example, by a coating method. The thickness (formed film thickness) of the resin film PA2 can be thicker than the thickness (formed film thickness) of the insulating film PA1, and can be, for example, about 5 μm.

  Next, as shown in FIG. 28, an opening OP3b is formed in the resin film PA2. The opening OP3b can be formed, for example, as follows. That is, the resin film PA2 is formed as a photosensitive resin film, and the resin film PA2 made of the photosensitive resin is exposed and developed to selectively remove the resin film PA2 in a portion to be the opening OP3b. Thus, the opening OP3b is formed in the resin film PA2. Thereafter, heat treatment is performed to cure the resin film PA2. The opening OP3b is formed to penetrate the resin film PA2, and at least a part of the pad PD is exposed from the opening OP3b.

  As another mode, the opening OP3b is formed in the resin film PA2 by dry etching the resin film PA2 using a photoresist layer formed on the resin film PA2 by photolithography as an etching mask. In this case, the resin film PA2 may not be a photosensitive resin film.

  The opening OP3b of the resin film PA2 is formed so as to be included in the opening OP3a of the insulating film PA1 in a plan view. Therefore, when the opening OP3b is formed in the resin film PA2, the inner wall of the opening OP3a of the insulating film PA1 is covered with the resin film PA2.

  Thus, the insulating film PA having the opening OP3 exposing at least a part of the pad PD is formed. The insulating film PA is made of an insulating film PA1 and a resin film PA2. Since the opening OP3b of the resin film PA2 is included in the opening OP3a of the insulating film PA1 in plan view, the opening OP3 of the insulating film PA substantially matches the opening OP3b of the resin film PA2, and the insulating film The inner wall (side wall) of the opening OP3 of PA is formed of the inner wall (side wall) of the opening OP3 b of the resin film PA2.

  Next, as shown in FIG. 29, a seed layer is formed on the insulating film PA (resin film PA2) including the side wall of the opening OP3 (OP3 b) and the pad PD exposed from the opening OP3 (OP3 b). (Seed film) SE is formed. When the seed layer SE is formed, the upper surface of the pad PD exposed from the opening OP3 (OP3b) is covered with the seed layer SE and is in contact with the seed layer SE.

  The seed layer SE is formed of a single layer or a plurality of metal layers and can be formed using a sputtering method or the like. For example, a laminated film of a chromium (Cr) layer and a copper (Cu) layer on the chromium (Cr) layer can be used as the seed layer SE, in which case the thickness of the chromium (Cr) layer is, for example, 0. The thickness of the copper (Cu) layer can be, for example, about 0.2 μm. Further, the lower chromium (Cr) layer of the seed layer SE can function as a barrier conductor layer, and, for example, a copper diffusion preventing function, the pillar electrode PL and the insulating film PA (resin film PA2) The adhesion (adhesion) of the metal has a function of improving the adhesion (adhesion), but is not limited to the chromium (Cr) layer. Instead of the chromium (Cr) layer, for example, a titanium (Ti) layer, a titanium tungsten (TiW) layer, a titanium nitride (TiN) layer or a tungsten (W) layer can be used.

  Next, as shown in FIG. 30, a photoresist layer (photoresist pattern) RP1 is formed on the seed layer SE by photolithography. The photoresist layer RP1 has an opening OP4 in a region for forming a pillar electrode PL.

  In plan view, the opening OP4 of the photoresist layer RP1 is included in the pad PD. The planar dimension (planar area) of the opening OP4 of the photoresist layer RP1 is larger than the planar dimension (planar area) of the opening OP3b of the resin film PA2, and the opening OP4 of the photoresist layer RP1 in plan view And the opening OP3b of the resin film PA2 is included. Therefore, the side wall (inner wall) of the opening OP3b of the resin film PA2 is located inside the opening OP4 of the photoresist layer RP1 in plan view. Therefore, not only the seed layer SE of the portion located on the pad PD but also the seed layer SE of the portion located on the resin film PA2 are exposed from the opening OP4 of the photoresist layer RP1.

  Next, as shown in FIG. 31, a copper (Cu) layer CL is formed on the seed layer SE exposed from the opening OP4 of the photoresist layer RP1 using a plating method. The copper (Cu) layer CL is a copper (Cu) plating layer. As a plating method for forming the copper (Cu) layer CL, electrolytic plating is preferably used. Since the copper layer CL is formed by the plating method, it is selectively formed on the seed layer SE in a portion exposed from the opening OP4 of the photoresist layer RP1. Thus, the copper (Cu) layer CL is selectively formed in the opening OP4 of the photoresist layer RP1. The pillar electrode PL is mainly formed by the copper (Cu) layer CL. Therefore, the pillar electrode PL is a Cu pillar (Cu pillar electrode) mainly made of copper. In the case of forming the copper (Cu) layer CL using electrolytic plating, the seed layer SE can function as a conductive layer for feeding. The copper layer CL contains copper (Cu) as a main component, and the content of copper (Cu) is preferably 99 atomic% or more.

  Next, as shown in FIG. 32, a solder layer (solder material, solder portion) SD1 is formed on the copper (Cu) layer CL using a plating method. The solder layer SD1 is made of solder (solder material). The solder layer SD1 is a solder plating layer formed by a plating method. As a plating method for forming the solder layer SD1, it is preferable to use an electrolytic plating method. The copper (Cu) layer CL and the solder layer SD1 thereon are selectively formed in the opening OP4 of the photoresist layer RP1.

  Next, as shown in FIG. 33, the photoresist layer RP1 is removed. Then, as shown in FIG. 34, the seed layer SE in the portion exposed without being covered with the copper (Cu) layer CL is removed by etching or the like. As a result, although the seed layer SE of the portion exposed without being covered with the copper (Cu) layer CL is removed, the seed layer SE of the portion covered with the copper (Cu) layer CL, that is, the copper (Cu) layer CL The seed layer SE in the lower part is left without being removed.

  Thus, as shown in FIG. 34, the pillar electrode PL can be formed. The pillar electrode PL is formed of a copper (Cu) layer CL and a seed layer SE under the copper (Cu) layer CL. In other words, the pillar electrode PL includes the seed layer SE and the copper (Cu) layer CL on the seed layer SE. Since the thickness of the seed layer SE is thinner than the thickness of the copper (Cu) layer CL, the pillar electrode PL is mainly formed of the copper (Cu) layer CL. The solder layer SD1 is formed on the tip surface (upper surface) of the pillar electrode PL.

  Since the copper (Cu) layer CL is selectively grown on the seed layer SE exposed from the opening OP4 of the photoresist layer RP1, the side surface of the copper (Cu) layer CL corresponds to the opening OP4 of the photoresist layer RP1. The outer shape of the copper (Cu) layer CL, which is defined by the side wall (inner wall), corresponds to the shape of the opening OP4 of the photoresist layer RP1. That is, the planar shape of the copper (Cu) layer CL corresponds to the planar shape of the opening OP4 of the photoresist layer RP1. For this reason, by setting the shape (planar shape) of the opening OP4 of the photoresist layer RP1 to a desired shape, the copper (Cu) layer CL can be formed to a desired shape. Therefore, the pillar electrode PL is formed. It can be formed into a desired shape. By forming the pillar electrode PL by the metal layer (here, the copper layer CL) selectively formed in the opening OP4 of the photoresist layer RP1, the pillar electrode PL has a columnar electrode having a three-dimensional shape of a pillar Become. In the present embodiment, the planar shape of the opening OP4 of the photoresist layer RP1 is circular, so that the planar shape of the pillar electrode PL can be circular, and the pillar electrode PL is cylindrical. Can.

  At this stage, the shape of the solder layer SD1 substantially matches the shape of the pillar electrode PL, and when the pillar electrode PL has a cylindrical shape, the solder layer SD1 also has a cylindrical shape. Thereafter, heat treatment (heat treatment) is performed to temporarily melt and re-solidify the solder layer SD1. Thereby, the shape of the solder layer SD1 is deformed by the influence of the surface tension of the molten solder, and as shown in FIG. 35, the solder layer SD1 has a dome shape. When heat treatment is performed in this manner, the tip end surface of the pillar electrode PL and the solder layer SD1 can be firmly joined. Further, as shown in FIG. 35, when the solder layer SD1 has a dome shape, the solder layer SD1 is more stable, so that it is possible to suppress the dropout and damage of the solder layer SD1 from the pillar electrode PL.

  In this manner (by the steps of FIGS. 29 to 35), the plurality of pillar electrodes PL are respectively formed (joined) on the plurality of pads PD, and the solder layers are formed on the tip surfaces of the plurality of pillar electrodes PL. A structure in which SD1 is formed is obtained.

  Furthermore, here, the case where the solder layer SD1 is formed on the copper (Cu) layer CL after the formation of the copper (Cu) layer CL has been described. As another embodiment, after forming the copper (Cu) layer CL, before forming the solder layer SD1, a nickel (Ni) layer is formed on the copper (Cu) layer CL by plating (electrolytic plating), The solder layer SD1 can also be formed on the nickel (Ni) layer. In this case, a nickel layer (nickel plating layer) intervenes between the copper (Cu) layer CL and the solder layer SD1 (see FIG. 36). This case is shown in FIG. 36, and the pillar electrode PL includes a seed layer SE, a copper (Cu) layer CL on the seed layer SE, and a nickel (Ni) layer NL on the copper (Cu) layer CL. And will be formed. Although FIG. 36 shows the same process steps as FIG. 35, after forming the copper (Cu) layer CL, nickel (Ni) is formed on the copper (Cu) layer CL before forming the solder layer SD1. This corresponds to the case where the layer NL is formed. When the nickel layer (nickel plating layer) NL is formed, the thickness of the nickel layer NL is thinner than that of the copper (Cu) layer CL, for example, about 3 μm, and the thickness of the pillar electrode PL is mainly copper (Cu) Layer CL.

  Thereafter, the back surface side of the semiconductor substrate SB is ground or polished as necessary to reduce the thickness of the semiconductor substrate SB, and then the semiconductor substrate SB is cut (diced) together with the stacked structure on the semiconductor substrate SB. At this time, the semiconductor substrate SB and the stacked structure on the semiconductor substrate SB are cut (dicing) along the scribe region by a dicing blade (not shown). Thus, semiconductor chips are obtained from the respective chip areas of the semiconductor substrate SB (semiconductor wafer).

  Thus, the semiconductor chip CP can be manufactured.

<About the process of examination>
In a semiconductor device in which a semiconductor chip is flip-chip connected to a wiring substrate, flip-chip connection can be performed by connecting a plurality of solder bumps of the semiconductor chip to a plurality of terminals of the wiring substrate. However, in recent years, with the increase in the number of terminals of the semiconductor chip and the miniaturization of the semiconductor chip, the distance between the solder bumps in the semiconductor chip has been narrowed.

  Therefore, the present inventor forms the plurality of pillar electrodes on the plurality of pads of the semiconductor chip, and connects the plurality of pillar electrodes of the semiconductor chip to the plurality of terminals of the wiring substrate through the solder. , Are considering making flip chip connections.

  By adopting a structure in which the pillar electrode of the semiconductor chip and the terminal of the wiring board are connected by soldering, the distance between the semiconductor chip and the wiring board can be easily increased by the use of the pillar electrode. Even if the distance between adjacent pillar electrodes is reduced due to the increase in the number of terminals and the miniaturization of the semiconductor chip, the underfill resin can be easily filled between the semiconductor chip and the wiring substrate. In addition, since the amount of solder in each solder connection can be reduced by using the pillar electrode, the solder connection can be reduced even if the distance between adjacent pillar electrodes is reduced due to the increase in the number of terminals of the semiconductor chip and the miniaturization of the semiconductor chip. It is easy to prevent the short circuit caused by contact with each other. Therefore, in order to meet the increase in the number of terminals of the semiconductor chip and the demand for miniaturization of the semiconductor chip, it is desirable to adopt a structure in which the pillar electrodes of the semiconductor chip and the terminals of the wiring substrate are connected by solder.

  In addition, the semiconductor chip has a wiring structure (multilayer wiring structure) having a plurality of wiring layers, and by connecting the elements formed in the semiconductor chip with the wiring formed in the wiring structure, the semiconductor An integrated circuit is formed. Along with the demand for miniaturization of semiconductor chips, miniaturization of interconnections in semiconductor chips is also advancing, but along with this, the distance (distance) between interconnections is also becoming smaller. When the distance between the wires decreases, the capacitance (parasitic capacitance) between the adjacent wires increases, the transmission speed of the signal transmitted through the wires decreases, and the signal delay and the power consumption may increase. For this reason, it is desirable to reduce the capacitance (parasitic capacitance) between adjacent wires by using a low dielectric constant insulating film as an interlayer insulating film forming the wiring structure. However, although the low dielectric constant insulating film has a dielectric constant lower than that of a silicon oxide film, the low dielectric constant insulating film is likely to be weaker in strength than a silicon oxide film.

  The inventor examined the reliability of the semiconductor device in the case of adopting a structure in which the pillar electrode of the semiconductor chip and the terminal of the wiring substrate are connected by soldering, through experiments and simulations. As a result, when adopting a structure in which the pillar electrodes of the semiconductor chip and the terminals of the wiring substrate are connected by soldering, optimizing the dimensions and the like of the respective members improves the reliability of the manufactured semiconductor device. Above, I found it to be extremely important.

  For example, when connecting a pillar electrode of a semiconductor chip to a terminal of a wiring substrate by flip chip connection with solder, when cooling after melting and resolidifying the solder, the pillar electrode PL to an interlayer insulating film of the wiring structure of the semiconductor chip Stress is likely to be applied. Applying stress from the pillar electrode PL to the interlayer insulating film of the wiring structure of the semiconductor chip may damage the interlayer insulating film and lead to deterioration of the interlayer insulating film. In particular, when a low dielectric constant insulating film is employed as the interlayer insulating film, damage is likely to be caused to the low dielectric constant insulating film when stress is applied to the low dielectric constant insulating film having low strength from the pillar electrode PL. The damage to the interlayer insulating film of the wiring structure of the semiconductor chip lowers the reliability of the semiconductor device having the semiconductor chip. For this reason, in order to improve the reliability of the semiconductor device, it is desirable to make it difficult for stress to be applied to the interlayer insulating film of the wiring structure of the semiconductor chip from the pillar electrode PL.

The inventors of the present invention have found that the thickness h ₁ of the pillar electrode PL and the pillar electrode are main factors contributing to the magnitude of the stress applied to the interlayer insulating film located below the pillar electrode PL from the pillar electrode PL by experiments and simulations. the diameter D ₁ of the PL, and the thickness of the semiconductor substrate SB constituting the semiconductor chip CP, newly found that there is. Then, it has been found that by optimizing these factors as described later, the magnitude of the stress applied to the interlayer insulating film located below the pillar electrode PL can be reduced to about half.

  In the present embodiment, when adopting a structure in which the pillar electrode of the semiconductor chip and the terminal of the wiring substrate are connected by solder, the reliability of the semiconductor device is optimized by optimizing the dimensions and the like of each member as described below. It is possible to improve the quality.

<About the main features and effects>
The semiconductor device PKG of the present embodiment is a semiconductor device having a wiring board CB and a semiconductor chip CP mounted on the wiring board CB. The semiconductor chip CP is formed on the interlayer insulating film IL6 (first insulating film), the pad PD formed on the interlayer insulating film IL6, and the opening OP3 formed on the interlayer insulating film IL6 and exposing a part of the pad PD. The insulating film PA (second insulating film) having the (first opening) and the pillar electrode PL formed on the pad PD exposed from the opening OP3 are provided. The wiring board CB has a terminal TE and a resist layer SR1 (third insulating film) having an opening OP1 (second opening) for exposing a part of the terminal TE. The insulating film PA of the semiconductor chip CP has an upper surface PA2a which is a main surface (first main surface) on the side facing the wiring substrate CB, and the resist layer SR1 of the wiring substrate CB faces the semiconductor chip CP It has an upper surface SR1a which is a side main surface (second main surface). In plan view, the pillar electrode PL includes the opening OP3 (first opening) of the insulating film PA, and a part of the pillar electrode PL overlaps the insulating film PA. The pillar electrode PL of the semiconductor chip CP and the terminal TE of the wiring substrate CB are connected via the solder layer SD interposed between the pillar electrode PL and the terminal TE.

The first feature of the present embodiment, the thickness of the pillar electrode PL from the upper surface PA2a insulating film PA (first thickness, height) _{h 1,} the solder layer SD from the upper surface SR1a resist layer SR1 the thickness is that (second thickness, height) in more than half of h _2, and is thick h ₂ below. That is, the first feature _is that satisfy the relationship of _{h 2/2 ≦ h 1 ≦} h 2. The thicknesses h ₁ and h ₂ are shown in FIG. 7 and FIG.

satisfy the relation of _{h 2/2 ≦ h 1 ≦} h 2 is equivalent to satisfy the relationship of _{h 1 ≦ h 2 ≦ h 1} × 2. Thus, the first feature, the thickness _{h 2} of the solder layer SD from the upper surface SR1a resist layer SR1 is at one or more times the thickness _{h 1} of the pillar electrode PL from the upper surface PA2a insulating film PA, and It is equivalent to not more than 2 times.

The thickness h ₁ can be regarded as the thickness of the pillar electrodes PL of the portion projecting from the upper surface PA2a insulating film PA (height). The thickness h ₁ can be from the upper surface PA2a insulating film PA, also it is regarded as the distance to the front end surface of the pillar electrode PL (distance when viewed in the thickness direction of the semiconductor chip CP). The thickness h ₁ can be regarded as the thickness of the pillar electrode PL portion (i.e. the portion that rides on the upper surface PA2a insulating film PA) located on the upper surface PA2a insulating film PA. In any case, h ₁ is a dimension as viewed in the thickness direction of the semiconductor chip CP.

The thickness _{h 2} can be a solder layer SD of the thickness of the portion projecting from the upper surface SR1a resist layer SR1 and (height) considered. The thickness h _2, when the upper surface SR1a resist layer SR1, viewed in the thickness direction of the distance (the wiring board CB to the solder layer SD of the upper surface (i.e., from the interface between the solder layer SD and the pillar electrode PL) Distance). In any case, h ₂ is a dimension as viewed in the thickness direction of the wiring board CB. When viewed in the thickness direction of the wiring substrate CB, the distance (distance) between the upper surface PA2a of the insulating film PA of the semiconductor chip CP and the upper surface SR1a of the resist layer SR1 of the wiring substrate CB is the thickness of the pillar electrode PL. This corresponds to the sum of h ₁ and the thickness h ₂ of the solder layer SD (that is, h ₁ + h ₂ ).

The reason why it is desirable to satisfy the first feature _{(h 2/2 ≦ h 1} ≦ h 2), will be described below.

The advantage of adopting a structure in which the pillar electrode PL is provided on the pad PD and the pillar electrode PL of the semiconductor chip CP and the terminal TE of the wiring substrate CB are connected by the solder layer SD is that the semiconductor chip This is to increase the distance between the CP and the wiring board CB and to suppress the amount of solder in the solder connection portion by the amount of use of the pillar electrode PL. In this respect, it is desirable thickness h ₁ of the pillar electrode PL is relatively large, the thickness h ₁ of the pillar electrode PL is small, the significance of using the pillar electrode PL becomes small. In this respect, the thickness _{h 1} of the pillar electrode PL is preferably a solder layer SD of more than half of the thickness _{h 2} (i.e. _{h 2/2 ≦ h 1)} . h _2/2 ≦ h ₁ By so holds, it is possible to enjoy precisely the advantages of using a pillar electrode PL. As a result, the underfill resin (resin portion UFR) is formed between the semiconductor chip CP and the wiring substrate CB even if the distance between the pillar electrodes PL is reduced due to the increase in the number of terminals of the semiconductor chip CP and the miniaturization of the semiconductor chip CP. It becomes easy to fill). In addition, since the amount of solder in each solder connection portion (here, solder layer SD) can be reduced by securing the thickness h ₁ of the pillar electrode PL, the solder connection portions can be formed even if the distance between adjacent pillar electrodes PL decreases. Makes it easy to prevent contact and short circuit. Therefore, the semiconductor chip CP can be miniaturized and the number of terminals can be increased.

On the other hand, if the thickness h ₁ of the pillar electrode PL is too large, the following problems occur. The stress applied to the pillar electrode PL is relieved by the insulating film PA (particularly, the resin film PA2) existing below the pillar electrode PL. However, increasing the thickness h ₁ of the pillar electrode PL, the stress becomes larger applied to the pillar electrode PL, can no longer be mitigated sufficiently by the stress insulating film PA (especially resin film PA2), the pillar electrode PL Stress is transmitted to the interlayer insulating film (IL1 to IL6) located below the pillar electrode PL, and stress is applied to the interlayer insulating film (IL1 to IL6). Applying stress to the interlayer insulating film located below the pillar electrode PL from the pillar electrode PL may lead to the occurrence of damage to the interlayer insulating film, which reduces the reliability of the semiconductor device PKG. According to the experiments and simulations of the inventor, the magnitude of the stress applied from the pillar electrode PL to the interlayer insulating film (IL1 to IL6) below the pillar electrode PL depends on the thickness h ₁ of the pillar electrode PL. , in order to reduce the stress applied from the pillar electrode PL below the interlayer insulating film of the pillar electrode PL (IL1~IL6), it is effective to reduce the thickness h ₁ of the pillar electrode PL.

In this respect, the thickness h ₁ of the pillar electrode PL is preferably equal to or less than the thickness h ₂ of the solder layer SD (that is, h ₁ ≦ h ₂ ). By satisfying h ₁ ≦ h _2, it is possible to reduce the stress applied to the interlayer insulating film (IL1 to IL6) below the pillar electrode PL from the pillar electrode PL, and therefore, it is caused by the stress from the pillar electrode PL Thus, damage to the interlayer insulating film located below the pillar electrode PL can be suppressed or prevented, and the reliability of the semiconductor device can be improved.

Therefore, as the first _feature, it is desirable to satisfy the relation of _{h 2/2 ≦ h 1 ≦} h 2. Thereby, the above-mentioned advantage by using pillar electrode PL can be properly enjoyed, and stress applied to interlayer insulating film (IL1 to IL6) located below pillar electrode PL from pillar electrode PL can be properly reduced. be able to. Thereby, the reliability of the semiconductor device can be improved. In addition, since the adjacent distance between the pillar electrodes PL can be reduced, the semiconductor chip CP can be miniaturized and the number of terminals can be increased.

FIG. 37 shows the result of simulation study on the correlation between the thickness of the pillar electrode (horizontal axis in FIG. 37) and the stress applied to the interlayer insulating film below the pillar electrode from the pillar electrode (vertical axis in FIG. 37). FIG. The horizontal axis of FIG. 37 is a thickness of the pillar electrodes corresponds to the thickness h _1. Also from the graph of FIG. 37, it can be understood that the stress applied to the interlayer insulating film below the pillar electrode from the pillar electrode can be reduced by reducing the thickness (h ₁ ) of the pillar electrode. The thickness h ₁ of the pillar electrode PL is preferably about 15 to 25 μm. Thus, for example, the thickness _{h 1} of the pillar electrode PL and 20 [mu] m, in combination to 30μm of thickness _{h 2} solder layer SD is suitable.

Second feature of this embodiment is the sum of the thickness _{h 1} and the solder layer SD thickness _{h 2} of the pillar electrode PL (i.e. _h 1 + _{h 2)} is, 0 of the diameter _{D 1} of the pillar electrode PL. 5 times or more and 0.8 times or less. That is, the second feature is that the relationship of D ₁ × 0.5 ≦ h ₁ + h ₂ ≦ D ₁ × 0.8 is satisfied. The diameter _{D 1} is shown in FIGS. 20 and 21. The diameter D of the pillar electrode PL ₁ is the diameter substantially the same as the opening OP4 of the photoresist layer RP1.

In addition, satisfying the relation of D ₁ × 0.5 ≦ h ₁ + h ₂ ≦ D ₁ × 0.8 means satisfying the relation of 0.5 ≦ (h ₁ + h ₂ ) / D ₁ ≦ 0.8. It is equivalent.

  The reason why it is desirable to satisfy the second feature will be described below.

If the diameter D ₁ of the pillar electrode PL is reduced to increase (h ₁ + h ₂ ) / D ₁ , the stress acting in the direction in which the pillar electrode PL falls is increased. If the stress acting in the direction in which the pillar electrode PL falls is increased, stress is easily applied to the interlayer insulating film (IL1 to IL6) located below the pillar electrode PL from the pillar electrode PL, which is not preferable. In order to reduce the stress applied from the pillar electrode PL to the interlayer insulating film below the pillar electrode PL, it is effective to increase the diameter D ₁ of the pillar electrode PL. In this respect, (h ₁ + h ₂ ) / D ₁ is preferably 0.8 or less.

On the other hand, increasing the diameter D ₁ of the pillar electrode PL to reduce (h ₁ + h ₂ ) / D _{1 corresponds} to an underfill resin (resin portion UFR) filled between the semiconductor chip CP and the wiring substrate CB. This leads to a reduction in volume, leading to a reduction in the protective effect of the underfill resin. Further, increasing the diameter D ₁ of the pillar electrode PL to reduce (h ₁ + h ₂ ) / D ₁ leads to an increase in the arrangement pitch of the pillar electrodes PL, which is disadvantageous to the miniaturization of the semiconductor chip and the increase in the number of terminals. It becomes. Therefore, also too small to increase the diameter _{D 1} of the pillar electrode PL and _{(h 1 + h 2) /} D 1, is not preferred. In this respect, (h ₁ + h ₂ ) / D ₁ is preferably 0.5 or more.

Therefore, as the second feature, the sum of the thickness _{h 1} and the solder layer SD of thickness _{h 2} of the pillar electrode PL is above 0.5 times the diameter _{D 1} of the pillar electrode PL, and 0.8-fold It is desirable that it is the following (ie, D ₁ × 0.5 ≦ h ₁ + h ₂ ≦ D ₁ × 0.8). Thereby, the stress acting in the direction in which the pillar electrode PL falls can be suppressed, and the stress can be hardly applied to the interlayer insulating film (IL1 to IL6) located below the pillar electrode PL from the pillar electrode PL. Reliability can be improved. In addition, since the volume of the underfill resin (resin part UFR) filled between the semiconductor chip CP and the wiring substrate CB can be easily secured, the protection effect by the underfill resin can be accurately obtained. In addition, the arrangement pitch of the pillar electrodes PL can be easily reduced, which is advantageous for the miniaturization of the semiconductor chip and the multi-terminal arrangement.

FIG. 38 shows the result of a simulation study of the correlation between the diameter of the pillar electrode (horizontal axis in FIG. 38) and the stress (vertical axis in FIG. 38) applied to the interlayer insulating film below the pillar electrode from the pillar electrode. It is a graph. The horizontal axis of FIG. 38 is a diameter of the pillar electrodes, corresponds to the diameter D _1. Also from the graph of FIG. 38, it can be seen that the stress applied to the interlayer insulating film below the pillar electrode from the pillar electrode can be reduced by increasing the diameter (D ₁ ) of the pillar electrode. The diameter _{D 1} of the pillar electrode PL is about 85~105μm are preferred.

A third feature of the present embodiment, the diameter _{D 2} of the opening OP3 of the insulating film PA is that at least 0.4 times the diameter _{D 1} of the pillar electrode PL, and 0.75 times or less . That is, the third feature is that the relationship of D ₁ × 0.4 ≦ D ₂ ≦ D ₁ × 0.75 is satisfied. The diameters D ₁ and D ₂ are shown in FIGS. 20 and 21. The opening OP3 of the insulating film PA is because it is composed by an opening OP3b of the resin film PA2, the diameter _{D 2} of the opening OP3 of the insulating film PA is the same as the diameter of the opening OP3b resin film PA2 is there.

  The reason why it is desirable to satisfy the third feature is described below.

When the diameter D ₂ of the opening OP3 insulating film PA decreases, the diameter of the pillar electrode PL portion filled in the opening OP3 insulating film PA also becomes small, part of which is buried in the opening OP3 insulating film PA The current density in the pillar electrode PL is increased. When the current density in the pillar electrode PL of the portion embedded in the opening OP3 of the insulating film PA becomes high, deterioration of the pillar electrode PL (for example, deterioration due to electromigration) is likely to occur, and EM (ElectroMigration) life etc. may be reduced. Not desirable because To suppress the deterioration of the pillar electrode PL, it is effective to increase the diameter D ₂ of the opening OP3 of the insulating film PA. In this respect, the diameter _{D 2} of the opening OP3 of the insulating film PA is preferably 0.4 times or more the diameter _{D 1} of the pillar electrode PL (i.e. _{D 1 × 0.4 ≦ D 2)} .

In addition, the insulating film PA (particularly the resin film PA2) has a function as a buffer layer (stress buffer layer, stress relaxation layer), and the stress applied to the pillar electrode PL is the insulating film PA as a buffer layer. It is relieved by (especially the resin film PA2). However, increasing the diameter D ₂ of the opening OP3 of the insulating film PA, functions as a buffer layer of insulating film PA (especially resin film PA2) decreases, the stress applied to the pillar electrode PL insulating film PA (especially Since the effect of relaxation by the resin film PA2 is reduced, stress is easily applied to the interlayer insulating film (IL1 to IL6) below the pillar electrode PL from the pillar electrode PL.

Therefore, as electromigration measures, in order to reduce the current density flowing in the pillar electrode PL, an excessively large diameter D ₂ of the opening OP3 of the insulating film PA connecting the pillar electrode PL to the pad PD, an insulating film PA ( In particular, the function of the resin film PA2) as a buffer layer is reduced, and the stress applied to the interlayer insulating film from the pillar electrode PL is increased, which may cause damage to the interlayer insulating film. Therefore, the too large diameter _{D 2} of the opening OP3 of the insulating film PA is not preferable. To reduce the stress applied from the pillar electrode PL below the interlayer insulating film of the pillar electrode PL (IL1~IL6), it is effective to reduce the diameter _{D 2} of the opening OP3 of the insulating film PA. In this respect, the diameter _{D 2} of the opening OP3 of the insulating film PA is preferably less 0.75 times the diameter _{D 1} of the pillar electrode PL (i.e. _{D 2 ≦ D 1 × 0.75)} .

Therefore, as a third aspect, the diameter _{D 2} of the opening OP3 of the insulating film PA is above 0.4 times the diameter _{D 1} of the pillar electrode PL, and is desirably 0.75 times or less (i.e., D ₁ × 0.4 ≦ D ₂ ≦ D ₁ × 0.75). Thereby, the current density in the pillar electrode PL of the portion embedded in the opening OP3 of the insulating film PA can be suppressed, so that deterioration of the pillar electrode PL (for example, deterioration due to electromigration) can be suppressed and EM life etc. is improved. Can. Further, the function as the buffer layer of the insulating film PA (particularly the resin film PA2) can be easily secured, and the stress applied to the interlayer insulating film (IL1 to IL6) below the pillar electrode PL from the pillar electrode PL can be reduced. . Therefore, the reliability of the semiconductor device can be improved.

  According to a fourth feature of the present embodiment, the insulating film PA has a laminated structure of an insulating film PA1 made of an inorganic insulating film and a resin film PA2 over the insulating film PA1, and the insulating film PA is of the insulating film PA1 in plan view. The opening OP3a (third opening) includes the opening OP3b (fourth opening) of the resin film PA2, and the opening OP3 of the insulating film PA is formed by the opening OP3b of the resin film PA2. It is that you are.

  The reason why it is desirable to satisfy the fourth feature is described below.

  The insulating film PA has a stacked structure of the insulating film PA1 and the resin film PA2 over the insulating film PA1, and the opening OP3a of the insulating film PA1 includes the opening OP3b of the resin film PA2 in plan view. For example, since the inner wall of the opening OP3 of the insulating film PA is formed of the inner wall of the opening OP3b of the resin film PA2, the pillar electrode PL is in contact with the resin film PA2 but not in contact with the insulating film PA1. Since the resin film PA2 is made of a resin material, the resin film PA2 is relatively soft and excellent in the function as a buffer layer (stress buffer layer, stress relaxation layer) that relieves the stress applied to the pillar electrode PL. Therefore, by making the pillar electrode PL in contact with the resin film PA2 but not in contact with the insulating film PA1, the stress applied to the pillar electrode PL can be easily relaxed by the resin film PA2, and the pillar electrode PL The stress applied to the interlayer insulating film (IL1 to IL6) below the pillar electrode PL can be reduced. Thereby, it is possible to suppress or prevent the occurrence of damage to the interlayer insulating film located below the pillar electrode PL due to the stress from the pillar electrode PL. For this reason, it is desirable to satisfy the fourth feature, whereby the reliability of the semiconductor device can be improved. For example, a combination in which the diameter of the opening OP3a is about 55 μm and the diameter of the opening OP3b is about 40 μm is preferable.

  Further, among the resin film PA2 on the insulating film PA1, the resin film PA2 mainly functions as a buffer layer for relieving stress applied to the pillar electrode PL, and improves the function as the buffer layer. Therefore, as the film of the uppermost layer of the semiconductor chip CP, the insulating film (that is, the resin film PA2) made of a resin material is used. If this function (function as a buffer layer) of the resin film PA2 is taken into consideration, it is particularly preferable if the resin film PA2 is a polyimide resin film. By doing so, the stress applied to the pillar electrode PL can be more appropriately relieved by the resin film PA2, and the pillar electrode PL to the interlayer insulating film (IL1 to IL6) below the pillar electrode PL Stress applied can be reduced more accurately.

  In addition, since the insulating film PA1 is made of an inorganic insulating film, the insulating film PA1 can properly function as a passivation film. The insulating film PA1 is more preferably made of a silicon nitride film or a silicon oxynitride film. By doing so, the moisture resistance of the semiconductor chip CP can be improved, and thus the reliability of the semiconductor device is improved. It can be done.

A fifth aspect of the present embodiment, the thickness of the resin film PA2 between the pads PD and the pillar electrode PL (third thickness) T ₁ is the thickness of the pad PD (fourth thickness) T ₂ It is larger than the thickness h ₁ of the pillar electrode PL. That is, the fifth feature is that the relationship of T ₂ <T ₁ <h ₁ is satisfied. The thicknesses T ₁ and T ₂ are shown in FIGS. 7 and 20.

Here, the thickness T _1, during the upper surface of the pad PD (upper surface of the pad PD of the portion not covered with the insulating film PA1) and the pillar electrode PL (pillar electrode PL portion rides on the resin film PA2) It is the thickness of the resin film PA2 of the part to intervene. In other words, the thickness _{T 1} in plan view, inside of the opening OP3A, and, in the region outside the opening OP 3 b, corresponds to the thickness of the resin film PA2. The thicknesses T ₁ and T ₂ are dimensions as viewed in the thickness direction of the semiconductor chip CP.

  The reason why it is desirable to satisfy the fifth feature is described below.

When the thickness (T ₁ ) of the resin film PA2 is reduced, the function of the resin film PA2 as a buffer layer is reduced, and the function of relieving stress applied to the pillar electrode PL by the resin film PA2 is reduced. Stress is easily applied from the pillar electrode PL to the interlayer insulating film (IL1 to IL6) below the pillar electrode PL. For this reason, it is not preferable to make the thickness (T ₁ ) of the resin film PA2 too thin. In order to reduce the stress applied from the pillar electrode PL to the interlayer insulating film (IL1 to IL6) below the pillar electrode PL, it is effective to increase the thickness (T ₁ ) of the resin film PA2. In this respect, the thickness _{T 1} of the resin layer PA2 is larger than the thickness _{T 2} of the pad PD (thick) is preferably (i.e. _T 2 _<T 1).

On the other hand, when the thickness (T ₁ ) of the resin film PA2 is too thick, it is attributed to the difference between the thermal contraction rate of the resin film PA2 and the thermal contraction rates of the interlayer insulating films (IL1 to IL6) constituting the wiring structure. The semiconductor chip CP is easily warped. For this reason, it is not preferable to make the thickness (T ₁ ) of the resin film PA2 too large. In this respect, the thickness _{T 1} of the resin layer PA2 is preferably smaller than the thickness _{h 1} of the pillar electrode PL (i.e. _T 1 _<h 1).

Therefore, as a fifth feature, it is desirable that thickness T ₁ of resin film PA ₂ be larger than thickness T _{2 of} pad PD and smaller than thickness h ₁ of pillar electrode PL (that is, T ₂ < T ₁ <h ₁ ). Thus, the function of the resin film PA2 as a buffer layer can be easily ensured, and the stress applied from the pillar electrode PL to the interlayer insulating film (IL1 to IL6) below the pillar electrode PL can be reduced. Thereby, it is possible to suppress or prevent the occurrence of damage to the interlayer insulating film located below the pillar electrode PL due to the stress from the pillar electrode PL. In addition, unnecessary warping of the semiconductor chip CP due to the difference between the thermal contraction rates of the resin film PA2 and the interlayer insulating films (IL1 to IL6) can be easily suppressed or prevented. Therefore, the reliability of the semiconductor device can be improved.

A sixth aspect of the present embodiment, in plan view, the diameter _{D 3} of the opening OP1 in the resist layer SR1 is, is smaller than the diameter _{D 1} of the pillar electrode PL (see FIG. 39). That is, the sixth feature is that the relationship of D ₃ <D ₁ is satisfied. The diameter _{D 3} is shown in FIG. 11 and FIG. 39. From another viewpoint, the sixth feature is that the opening OP1 of the resist layer SR1 is included in the pillar electrode PL in a plan view. Here, FIG. 39 is a plan view of relevant parts of the semiconductor device PKG, and FIG. 39 is a plan view of the terminal of the wiring board CB, the opening OP1 of the resist layer SR1 and the pillar electrode PL in the semiconductor device PKG. The layout is shown.

  The reason why it is desirable to satisfy the sixth feature is described below.

In plan view, the diameter D ₃ of the opening OP1 in the resist layer SR1, the results in greater than the diameter D ₁ of the pillar electrode PL, part of the solder layer SD1 becomes easy to raise wettability on the side surface of the pillar electrode PL I will. If part of the solder layer SD1 gets wet on the side surface of the pillar electrode PL, it becomes difficult to fill the underfill resin (resin part UFR) between the semiconductor chip CP and the wiring board CB, which is not preferable. Further, if part of the solder layer SD1 gets wet on the side surface of the pillar electrode PL, the risk of a short circuit between the adjacent pillar electrodes PL increases, which is not preferable. Further, a part of the solder layer SD1 increases wetting to the side of the pillar electrode PL, correspondingly, the smaller the thickness h ₂ of the solder layer SD, since the distance between the semiconductor chip CP and the wiring board CB is narrowed Not desirable.

Thus, as a feature of the sixth, in plan view, the diameter _{D 3} of the opening OP1 in the resist layer SR1 is preferably smaller than the diameter _{D 1} of the pillar electrode PL. From another viewpoint, in plan view, the opening OP1 of the resist layer SR1 is preferably contained in the pillar electrode PL. As a result, the shape of the solder layer SD connecting the pillar electrode PL and the terminal TE becomes the shape as shown in FIG. 7, and the solder constituting the solder layer SD1 is less likely to get wet on the side surface of the pillar electrode PL. Therefore, the underfill resin (resin part UFR) can be easily filled between the semiconductor chip CP and the wiring board CB, and the semiconductor device PKG can be easily manufactured. In addition, since the risk of a short circuit between the adjacent pillar electrodes PL can be reduced, the reliability of the semiconductor device can be improved. For example, the combination of the diameter _{D 1} of the pillar electrode PL is about 85～105Myuemu, the diameter _{D 3} of the opening OP1 in the resist layer SR1 about 65~75μm is suitable.

The arrangement pitch of the pillar electrodes PL in the semiconductor chip CP is preferably larger than a value (D ₁ +15 μm) obtained by adding 15 μm to the diameter D ₁ of the pillar electrode PL. That is, in the plan view, it is preferable to secure 15 μm or more of the closest contact distance (the distance between the closest portions) of the adjacent pillar electrodes PL. As a result, the underfill resin (resin part UFR) can be easily filled between the semiconductor chip CP and the wiring board CB. If an example is given, diameter D ₁ of pillar electrode PL can be about 85-105 micrometers, and arrangement pitch of pillar electrodes PL can be about 130 micrometers.

Further supplement to the sixth feature. As described above, as a feature of the sixth, in plan view, the diameter _{D 3} of the opening OP1 in the resist layer SR1 is smaller than the diameter _{D 1} of the pillar electrode PL _(D 3 <D ₁₎ is, the resist layer SR1 any diameter _{D 3} of the opening OP1 is 0.7 times or more and 0.8 times or less the diameter _{D 1} of the pillar electrode _{PL (D 1 × 0.7 ≦ D} 3 ≦ D 1 × 0.8) Are particularly preferred. The reason is described below.

As described above, as a feature of the sixth, in plan view, the diameter _{D 3} of the opening OP1 in the resist layer SR1 is smaller than the diameter _{D 1} of the pillar electrode _{PL (D 3 <D 1)} , the alternative view Then, in plan view, the opening OP1 of the resist layer SR1 is included in the pillar electrode PL. As a result, the solder constituting the solder layer SD1 is less likely to get wet on the side surface of the pillar electrode PL. However, because the solder constituting the solder layer SD1 to reliably prevent the rising wetting a side surface of the pillar electrode PL in a plan view, the diameter D ₃ of the opening OP1 in the resist layers SR1 of the pillar electrode PL diameter D ₁ not only smaller than, further the diameter _{D 3} of the opening OP1 in the resist layer SR1, 0.8 times the diameter _{D 1} of the pillar electrode PL (i.e. _{D 3} ≦ _{D 1} × 0.8) It is preferable to do. If the diameter _{D 3} of the opening OP1 in the resist layer SR1 and 0.8 times the diameter _{D 1} of the pillar electrode _{PL (D 3 ≦ D 1 ×} 0.8), solder pillar electrodes constituting the solder layer SD1 It is possible to more accurately prevent the side surfaces of the PL from getting wet.

On the other hand, when the diameter _{D 3} of the opening OP1 in the resist layer SR1 decreases, the solder layer SD diameter burried in the opening OP1 in the resist layers SR1 becomes small, embedded in the openings OP1 in the resist layer SR1 The current density in the solder layer SD of a part becomes high. When the current density in the solder layer SD of the portion embedded in the opening OP1 of the resist layer SR1 becomes high, deterioration of the solder layer SD (for example, deterioration due to electromigration) tends to occur, and EM life etc. may be reduced. Not desirable. To suppress or prevent degradation of resulting solder layer SD to an increase in the current density, it is effective to not too small a diameter D ₃ of the opening OP1 in the resist layer SR1. Further, the diameter _{D 3} of the opening OP1 in the resist layer SR1 to the diameter _{D 1} of the pillar electrode PL ratio (i.e. _D 3 / _{D 1)} when the smaller, the resist layer SR1 of top SR1a the resist layer SR1 openings OP1 A constricted portion of the solder layer SD is formed at a position in contact with the corner portion formed by the inner wall (side wall), and the risk of cracking in the solder layer SD starting from the constricted portion increases. To suppress or prevent the cracking of the solder layer SD is that too small a ratio of the diameter _{D 3} of the opening OP1 in the resist layer SR1 to the diameter _{D 1} of the pillar electrode PL (i.e. _D 3 / _{D 1)} It is valid. That is, in order to suppress or prevent the solder layer SD deterioration or cracks, it is effective not too small a diameter D ₃ of the opening OP1 in the resist layer SR1.

Thus, as a feature of the sixth, the openings OP1 in the resist layers SR1 in a plan view is contained in the pillar electrode PL (diameter _{D 3} of the opening OP1 is smaller than the diameter _{D 1} of the pillar electrode PL), the diameter _{D 3} of the opening OP1 in the resist layer SR1, and 0.8 times less than 0.7 times the diameter _{D 1} of the pillar electrode PL (i.e. _{D 1 × 0.7 ≦ D 3 ≦} D 1 × 0. It is particularly preferable to set it as 8). That is, the ratio (D ₃ / D ₁ ) of diameter D ₃ of opening OP1 of resist layer SR1 to diameter D ₁ of pillar electrode PL is 0.7 or more and 0.8 or less (that is, 0.7 ≦ D _3). It is particularly preferable to set / D ₁ ≦ 0.8). By doing so, it is possible to properly prevent the solder constituting the solder layer SD1 from getting wet on the side surface of the pillar electrode PL, and to suppress or prevent the deterioration and cracks of the solder layer SD. Reliability can be more accurately improved.

  Although FIG. 39 shows the case where the planar shape of the terminal TE is a quadrangle (rectangle) as an example, the present invention is not limited to this, and the planar shape of the terminal TE may be circular or the like.

  A seventh feature of the present embodiment is that the thickness of the semiconductor substrate SB constituting the semiconductor chip CP is 25 to 300 μm. The reason why it is desirable to satisfy the seventh feature is described below.

  When the thickness of the semiconductor substrate SB constituting the semiconductor chip CP is large, the semiconductor chip CP is not easily deformed. On the other hand, if the thickness of the semiconductor substrate SB constituting the semiconductor chip CP is reduced, the semiconductor chip CP is easily deformed and stress applied to the interlayer insulating films (IL1 to IL6) constituting the wiring structure of the semiconductor chip CP The semiconductor chip CP can be relaxed by deformation. Therefore, reducing the thickness of the semiconductor substrate SB acts to reduce the stress applied from the pillar electrode PL to the interlayer insulating film (IL1 to IL6) below the pillar electrode PL. From this point of view, it is preferable that the thickness of the semiconductor substrate SB constituting the semiconductor chip CP be made thin to some extent and not more than 300 μm. On the other hand, when the thickness of the semiconductor substrate SB is too thin, the risk of cracking of the semiconductor substrate SB increases, so the thickness of the semiconductor substrate SB is preferably 25 μm or more.

  Therefore, as a seventh feature, the thickness of the semiconductor substrate SB constituting the semiconductor chip CP is desirably in the range of 25 to 300 μm. Thereby, the stress applied to the interlayer insulating film (IL1 to IL6) below the pillar electrode PL from the pillar electrode PL can be relieved by the deformation of the semiconductor chip CP, and the semiconductor substrate SB is properly broken. Can be prevented. Therefore, the reliability of the semiconductor device can be improved, and the semiconductor device can be easily manufactured. In addition, the manufacturing yield of the semiconductor device can be improved.

  FIG. 40 simulates the correlation between the thickness of the semiconductor substrate constituting the semiconductor chip (horizontal axis in FIG. 40) and the stress applied to the interlayer insulating film below the pillar electrode from the pillar electrode (vertical axis in FIG. 40) It is a graph which shows the result investigated by. Also from the graph of FIG. 40, it can be seen that the stress applied to the interlayer insulating film below the pillar electrode from the pillar electrode can be reduced by reducing the thickness of the semiconductor substrate constituting the semiconductor chip. Therefore, it is preferable that the thickness of the semiconductor substrate SB constituting the semiconductor chip CP be 300 μm or less.

  An eighth feature of the present embodiment is that the planar shape of the opening OP3 of the insulating film PA (the opening OP3b of the resin film PA2) is circular (see FIG. 21). Further, it is more preferable that the planar shape of the pillar electrode PL is circular. The reason why it is desirable to satisfy the eighth feature is described below.

  The planar shape of the opening OP3 of the insulating film PA (the opening OP3b of the resin film PA2) may be various planar shapes such as a quadrangular shape (rectangular shape), a polygonal shape other than a quadrangle, or a circular shape. Among these, the circular shape is particularly preferable. By making the planar shape of the opening OP3 of the insulating film PA (the opening OP3b of the resin film PA2) circular, the pillar of the portion embedded in the opening OP3 of the insulating film PA (the opening OP3b of the resin film PA2) The electrode PL has a cylindrical shape. As a result, anisotropic stress is less likely to be generated in the pillar electrode PL, and it is possible to prevent occurrence of a phenomenon in which stress is concentrated on the corner portion of the pillar electrode PL. This effect is further enhanced by making the planar shape of the pillar electrode PL circular. Thereby, the stress applied to the interlayer insulating film (IL1 to IL6) below the pillar electrode PL from the pillar electrode PL can be reduced. Therefore, it is possible to suppress or prevent damage to the interlayer insulating film located below the pillar electrode PL due to the stress from the pillar electrode PL. Therefore, the reliability of the semiconductor device can be improved.

  The semiconductor chip CP also has a wiring structure including a plurality of wiring layers. The present embodiment is effective when applied to the case where the wiring structure of the semiconductor chip CP includes a low dielectric constant insulating film. The reason is as follows.

  As described above, in recent years, since the distance between the interconnections in the semiconductor chip has become smaller, the parasitic capacitance between adjacent interconnections may increase, which may lead to an increase in signal delay and power consumption. For this reason, it is desirable to reduce the parasitic capacitance between adjacent wires by using a low dielectric constant insulating film as an interlayer insulating film constituting the wiring structure of the semiconductor chip, thereby improving the performance of the semiconductor device. Can. However, although the low dielectric constant insulating film has a dielectric constant lower than that of a silicon oxide film, the low dielectric constant insulating film is likely to be weaker in strength than a silicon oxide film. Therefore, when a low dielectric constant insulating film is employed as an interlayer insulating film included in the wiring structure, when stress is applied to the interlayer insulating film under the pillar electrode PL from the pillar electrode PL, the stress is applied to the interlayer insulating film. The risk of damage is increased. That is, it can be said that the low dielectric constant insulating film is a film having low resistance to the stress from the pillar electrode PL.

  On the other hand, in the present embodiment, the stress applied to the interlayer insulating film (IL1 to IL6) below the pillar electrode PL from the pillar electrode PL is reduced by the above features (first to eighth features). . Therefore, even when a low dielectric constant insulating film having low resistance to stress is adopted as an interlayer insulating film included in the wiring structure, an interlayer insulating film made of a low dielectric constant insulating film is formed by the stress from the pillar electrode PL. It is possible to suppress or prevent the occurrence of damage. Therefore, if the present embodiment is applied to the case where the wiring structure of the semiconductor chip CP includes a low dielectric constant insulating film, an effect of reducing parasitic capacitance between adjacent wirings in the semiconductor chip CP can be obtained. In addition, it is possible to suppress or prevent the low dielectric constant insulating film from being damaged by the stress from the pillar electrode PL. Therefore, the performance of the semiconductor device can be improved, and the reliability of the semiconductor device can be improved. This can be applied to the ninth and tenth features described later.

  Next, a first modification of the present embodiment will be described. FIGS. 41 and 42 are main-portion cross-sectional views (FIG. 41) and main-portion plan views (FIG. 42) of a semiconductor device PKG of a first modification example of the present embodiment. 41 shows a sectional view (partially enlarged sectional view) of a region corresponding to FIG. 7 described above, and FIG. 42 shows a plan view corresponding to FIG. 21 described above. FIG. 41 substantially corresponds to the cross-sectional view at the position of line A6-A6 in FIG. FIG. 43 is an explanatory view for explaining the effect of the semiconductor device of the first modified example, and a cross-sectional view of a region corresponding to the above-mentioned FIG. 7 is shown.

  The semiconductor device of the first modification shown in FIGS. 41 and 42 is mainly different from the semiconductor device of FIG. 7 in having the ninth feature.

  That is, the ninth feature is that, in the plan view, the pad PD includes the pillar electrode PL in the pad PD and the pillar electrode PL formed on the pad PD. That is, in plan view, the pillar electrode PL is included in the pad PD and does not protrude from the pad PD. From another point of view, the ninth feature is that, in a plan view, the position of the side (peripheral) side PDS of the pad PD of the semiconductor chip CP is the same as the side PLS of the pillar electrode PL or the side PLS of the pillar electrode PL It is to be located outside. Here, in plan view, the side away from the opening OP3 of the insulating film PA is the outside, and the side approaching the opening OP3 of the insulating film PA is the inside.

  The side surface PLS of the pillar electrode PL is a side surface of the pillar electrode PL in a portion located on the upper surface PA2a of the insulating film PA (that is, a portion running on the upper surface PA2a of the insulating film PA). The side surface PLS of the pillar electrode PL overlaps with the insulating film PA2 in plan view, and is in contact with the resin portion UFR. That is, the side surface PLS of the pillar electrode PL is a side surface in contact with the resin portion UFR.

  The effects of the ninth feature are described below, comparing FIG. 41 with FIG.

  When forming an insulating film, if there is a level difference in the base of the insulating film, a level difference reflecting the level difference of the base may occur in the insulating film. The insulating film PA is formed so that a part (central part) of the upper surface of the pad PD is exposed from the opening OP3 and covers the outer peripheral part and the side surface of the upper surface of the pad PD. Therefore, in the upper surface PA2a of the insulating film PA, there may be a case where a step difference DS caused by the side surface PDS of the pad PD. Each of FIG. 41 and FIG. 43 shows the case where a step DS caused by the side surface PDS of the pad PD is formed on the upper surface PA2a of the insulating film PA. Incidentally, comparing the case of FIG. 41 with the case of FIG. 43, the plane dimension (plane area) of the pad PD is larger in FIG. 41 than in FIG. 43, and in FIG. Although the side surface PDS of the pad PD does not overlap with the pillar electrode PL, in the case of FIG. 43, the side surface PDS of the pad PD overlaps with the pillar electrode PL in plan view.

  In the case of FIG. 43, a step DS due to the side surface PDS of the pad PD is formed on the upper surface PA2a of the insulating film PA, and the pillar electrode PL is also present on the step DS. That is, in the case of FIG. 43, the pillar electrode PL exists in the region outside the step DS on the upper surface PA2a of the insulating film PA. In this case (FIG. 43), the lower surface PLK of the pillar electrode PL in contact with the insulating film PA is not flat but has a shape reflecting the step difference DS. Specifically, the lower surface PLK of the pillar electrode PL has a shape in which the region near the end of the lower surface PLK protrudes (sharps) toward the semiconductor chip CP. The surface of the pillar electrode PL in contact with the upper surface PA2a of the insulating film PA is denoted by the symbol PLK, and is defined as the lower surface PLK of the pillar electrode PL.

  In the case where lower surface PLK of pillar electrode PL has a shape as shown in FIG. 43, temperature cycle (when the high temperature state and the low temperature state are alternately repeated) of lower surface PLK of pillar electrode PL is When the region in the vicinity of the end portion presses the insulating film PA, stress is applied to the pad PD or the interlayer insulating film of the semiconductor chip CP, so that deformation of the pad PD or damage to the interlayer insulating film tends to occur.

  In order to suppress deformation of the pad PD and damage to the interlayer insulating film caused by the stress from the pillar electrode PL, the lower surface PLK of the pillar electrode PL in contact with the insulating film PA should be flat to the end of the lower surface PLK. Is valid. For that purpose, even if the step DS of the insulating film PA is generated, it is necessary to prevent the step DS from affecting the shape of the lower surface PLK of the pillar electrode PL. This is because the pad PD and the pillar electrode PL are designed such that the pillar electrode PL does not exist on the step DS of the insulating film PA, and the side surface PLS of the pillar electrode PL is positioned inside the step DS in plan view. It can be realized by doing.

  The level difference DS of the insulating film PA is generated due to the side surface PDS of the pad PD, and the planar positional relationship between the level difference DS of the insulating film PA and the side surface PDS of the pad PD is The step DS is always located outside the side surface PDS of the pad PD. As described above, in plan view, the side of the insulating film PA far from the opening OP3 is the outer side, and the side approaching the opening OP3 of the insulating film PA is the inner side. Therefore, if the pillar electrode PL is included in the pad PD in plan view and the pillar electrode PL is not protruded from the pad PD, the side surface PLS of the pillar electrode PL is necessarily the insulating film PA in plan view. Therefore, the pillar electrode PL is not present on the step DS of the insulating film PA. Thereby, as shown in FIG. 41, even if the step DS of the insulating film PA is generated, the lower surface PLK of the pillar electrode PL in contact with the insulating film PA can be made flat to the end of the lower surface PLK.

  That is, when the ninth feature is satisfied, even if the step DS caused by the side surface PDS of the pad PD is generated in the insulating film PA, the step DS does not affect the shape of the lower surface PLK of the pillar electrode PL. The lower surface PLK of the pillar electrode PL in contact with the insulating film PA can be planarized to the end of the lower surface PLK (see FIG. 41). Compared to the case of FIG. 43, in the case of FIG. 41, reflecting that the lower surface PLK of the pillar electrode PL is flat, the pad PD or interlayer insulation of the semiconductor chip CP from the lower surface PLK of the pillar electrode PL Since stress applied to the film can be relaxed, deformation of the pad PD or damage to the interlayer insulating film can be suppressed. Therefore, by satisfying the ninth feature, it is possible to suppress or prevent the deformation of the pad PD and the damage of the interlayer insulating film due to the stress from the pillar electrode PL at the time of temperature cycle. Thereby, the reliability of the semiconductor device can be improved.

  The ninth feature can be combined with one or more of the first to eighth features.

  Next, a second modification of the present embodiment will be described. FIG. 44 is a plan view of relevant parts of a semiconductor device PKG of the second modified example of the present embodiment, and corresponds to FIG. FIG. 44 shows a planar layout of the terminal of the wiring board CB, the opening OP1 of the resist layer SR1, and the pillar electrode PL in the semiconductor device PKG of the second modification. The cross-sectional view of the semiconductor device PKG of the second modification is basically the same as FIGS. 6 and 7 described above.

The semiconductor device of the second modification shown in FIG. 44 has a tenth feature. A tenth feature is that 1.5 ≦ D ₄ / D ₃ ≦ 2.

Here, as described above, _{D 3} is the diameter of the opening OP1 in the resist layer SR1. Further, _{D 4} is the diameter of the terminal TE. The terminal TE is, of copper layer TE1 and the copper layer TE1 on the nickel layer TE2 Prefecture, since the nickel layer TE2 is contained in the copper layer TE1 in a plan view, the diameter _{D 4} of the terminal TE is the terminal TE It corresponds to the diameter of the copper layer TE1 to be configured. In the second modification, as shown in FIG. 44, the planar shape of the terminal TE, that is, the planar shape of the copper layer TE1 constituting the terminal TE is circular. Further, as in the case of FIG. 39, also in the case of FIG. 44, the planar shape of the opening OP1 of the resist layer SR1 is circular. The nickel layer TE2 constituting the terminal TE is formed on the copper layer TE1 in a portion exposed from the opening OP1 of the resist layer SR1. Therefore, the planar shape and the planar dimensions of the opening OP1 of the resist layer SR1 The planar shape and the planar dimension of the nickel layer TE2 constituting the terminal TE are substantially the same.

  The reason and effect of adopting the tenth feature will be described below.

  The adhesion between the resist layer SR1 and the terminal TE (copper layer TE1) is not so strong, so if the contact area between the resist layer SR1 and the terminal TE (copper layer TE1) is small, the resist layer SR1 and the terminal TE (copper) The adhesion (adhesiveness) with the layer TE1) is lowered, and there is a concern about peeling at the interface between the resist layer SR1 and the terminal TE. Peeling at the interface between the resist layer SR1 and the terminal TE is not preferable because it leads to a decrease in the reliability of the semiconductor device.

Therefore, it is desirable that the contact area between the resist layer SR1 and the terminal TE (copper layer TE1) be increased to some extent to make it difficult to cause peeling at the interface between the resist layer SR1 and the terminal TE. To increase the contact area of the terminal TE (the copper layer TE1) and the resist layer SR1, increase the diameter _{D 4} of the terminal TE, but to reduce the diameter _{D 3} of the opening OP1 in the resist layer SR1, which This corresponds to increasing the ratio (D ₄ / D ₃ ) of the diameter D ₄ of the terminal TE to the diameter D ₃ of the opening OP 1 of the resist layer SR 1.

That is, if D ₄ / D ₃ is made smaller, the contact area between the resist layer SR 1 and the terminal TE (copper layer TE 1) becomes smaller, and there is concern about peeling at the interface between the resist layer SR 1 and the terminal TE. In order to suppress or prevent, it is effective not to make D ₄ / D ₃ too small.

On the other hand, when the diameter _{D 3} of the opening OP1 in the resist layer SR1 decreases, the solder layer SD diameter burried in the opening OP1 in the resist layers SR1 becomes small, embedded in the openings OP1 in the resist layer SR1 The current density in the solder layer SD of a part becomes high. When the current density in the solder layer SD of the portion embedded in the opening OP1 of the resist layer SR1 becomes high, deterioration of the solder layer SD (for example, deterioration due to electromigration) tends to occur, and EM life etc. may be reduced. Not desirable. To suppress or prevent degradation of resulting solder layer SD to an increase in the current density, it is effective to not too small a diameter D ₃ of the opening OP1 in the resist layer SR1.

Also, increasing the diameter D ₄ of the terminal TE, either the arrangement pitch of the terminal TE is large, or leads to the distance between the adjacent terminal TE becomes narrow. As the arrangement pitch of the terminals TE increases, the arrangement pitch of the pads PD of the semiconductor chip CP correspondingly increases, which is not preferable because it goes against the demand for miniaturization and multi-terminal formation of the semiconductor chip CP. In addition, when the distance between the adjacent terminals TE becomes narrow, it becomes difficult to pass the wiring between the adjacent terminals TE in the wiring substrate CB, which leads to the restriction of the wiring layout of the wiring substrate CB, which is not preferable. Therefore, to suppress the arrangement pitch of the terminal TE, in order to reduce the constraints of the wiring layout of the wiring board CB, it is effective to not too large a diameter D ₄ of the terminal TE.

And increasing the diameter _{D 4} of the terminal TE, and reducing the diameter _{D 3} of the opening OP1 in the resist layer SR1 are both the diameter D of the terminal TE to the diameter _{D 3} of the opening OP1 in the resist layer SR1 It acts to increase the ratio of ₄ (D ₄ / D ₃ ).

Therefore, to suppress or prevent the deterioration of the solder layer SD due to the increase of the current density, and to suppress the arrangement pitch of the terminals TE and reduce the restriction of the wiring layout of the wiring board CB, D ₄ / D It is effective not to make ₃ large too much.

Therefore, in the second modification, the tenth feature is adopted, and the relationship of 1.5 ≦ D ₄ / D ₃ ≦ 2 is satisfied. By satisfying the relationship 1.5 ≦ D ₄ / D ₃ , the contact area between the resist layer SR 1 and the terminal TE is secured to a certain extent, and the adhesion between the resist layer SR 1 and the terminal TE is enhanced, whereby the resist layer is formed. It is possible to make it difficult to cause peeling at the interface between 1 and the terminal TE. Further, by satisfying the relationship of D ₄ / D ₃ ≦ 2, deterioration of the solder layer SD due to an increase in current density can be suppressed or prevented, and the arrangement pitch of the terminals TE can be suppressed, and the wiring of the wiring board CB Layout constraints can be reduced. Accordingly, by satisfying the relationship of 1.5 ≦ D ₄ / D ₃ ≦ 2, the reliability of the semiconductor device can be improved, and it is advantageous for the miniaturization (reduction in area) and the increase in the number of terminals of the semiconductor chip CP. Thus, the degree of freedom of the wiring layout of the wiring board CB can be improved.

Further, it has been described that it is preferable to satisfy the relationship of D ₁ × 0.7 ≦ D ₃ ≦ D ₁ × 0.8 in relation to the sixth feature, but with this relationship and the tenth feature When the relationship of 1.5 ≦ D ₄ / D ₃ ≦ 2 is combined, the diameter D _{4 of the} terminal TE and the diameter D ₁ of the pillar electrode PL satisfy 1.05 ≦ D ₄ / D ₁ ≦ 1. It is preferable to satisfy the relationship of 6.

  The tenth feature can also be combined with one or more of the first to ninth features.

  Further, in FIG. 44, the planar shape of the terminal TE is circular. When the planar shape of the terminal TE is circular, the following effects can be obtained.

  That is, when the planar shape of the terminals TE is circular, the distance between the adjacent terminals TE can be efficiently increased. For example, comparing the case where the planar shape of the terminal TE is circular and the case where the rectangular shape is employed, if the arrangement pitch of the terminals TE is the same, the distance between adjacent terminals TE is greater than the case where the planar shape of the terminals TE is rectangular. The case where the planar shape of the terminal TE is circular is wider. Therefore, by making the planar shape of the terminals TE circular, the distance between the adjacent terminals TE can be efficiently increased, and it becomes easy to pass the wiring between the adjacent terminals TE in the wiring board CB. The degree of freedom of the wiring layout on the substrate CB can be further improved.

  In addition, if the opening OP1 of the resist layer SR1 is circular, anisotropic stress is less likely to be generated in the solder layer SD, and stress concentration at the corner of the solder layer SD is prevented. can do. This makes it easy to suppress or prevent the deterioration or crack of the solder layer SD.

  Next, the presence or absence of the nickel layer NL in the pillar electrode PL will be supplemented. FIGS. 7 and 35 show the case where the nickel layer (nickel plating layer) does not intervene between the copper layer CL and the solder layer SD, and the pillar electrode PL is formed on the seed layer SE and the seed layer SE. And the copper layer CL. As another form, as described with reference to FIG. 36, the pillar electrode PL can be formed of the seed layer SE, the copper layer CL on the seed layer SE, and the nickel layer NL on the copper layer CL. In that case, the nickel layer NL is interposed between the copper layer CL and the solder layer SD.

  However, as in FIGS. 7 and 35, the pillar electrode PL does not have the nickel layer NL as in the case where the pillar electrode PL has the nickel layer NL (FIG. 36), and the copper layer CL and the solder layer SD In the case where the nickel layer (NL) does not intervene between them, the EM life can be improved. The reason is considered as follows.

  First, an EM test is performed on a semiconductor device (corresponding to a semiconductor device to which the pillar electrode PL of FIG. 36 is applied) in which the nickel layer NL is interposed between the copper layer CL and the solder layer SD constituting the pillar electrode PL. Will be explained. In this case, diffusion of nickel (Ni) occurs from the nickel layer TE2 constituting the terminal TE to the solder layer SD side, and an EM open failure occurs between the nickel layer TE2 and the solder layer SD. This is the main factor that determines the EM lifetime.

  Next, an EM test is conducted on a semiconductor device (corresponding to a semiconductor device to which the pillar electrode PL of FIG. 35 is applied) in which the nickel layer (NL) is not interposed between the copper layer CL and the solder layer SD constituting the pillar electrode PL. The case where it carried out is demonstrated. In this case, due to the thermal diffusion of copper (Cu) from the copper layer CL, a CuSn layer is formed on the nickel layer TE2 that constitutes the terminal TE, and this CuSn layer from the nickel layer TE2 to the solder layer SD. Function as a barrier layer against the diffusion of nickel (Ni). Therefore, the EM open failure hardly occurs between the nickel layer TE2 and the solder layer SD which constitute the terminal TE. In this case, the EM open failure occurring between the copper layer CL constituting the pillar electrode PL and the solder layer SD, not between the nickel layer TE2 constituting the terminal TE and the solder layer SD, is the main factor determining the EM life. However, the EM lifetime is improved (for example, improved by about 25%) as compared with the semiconductor device to which the pillar electrode PL of FIG. 36 is applied.

  Therefore, the EM life can be increased by preventing the nickel layer (NL) from being interposed between the copper layer CL and the solder layer SD that constitute the pillar electrode PL without the pillar electrode PL having the nickel layer NL. It can be improved. Therefore, the reliability of the semiconductor device can be further improved.

  As mentioned above, although the invention made by the present inventor was concretely explained based on the embodiment, the present invention is not limited to the embodiment, and can be variously changed in the range which does not deviate from the summary. Needless to say.

  In addition, a part of the contents described in the above embodiment (including the modified example) will be described below.

[Supplementary Note 1]
A semiconductor device comprising: a wiring substrate; and a semiconductor chip mounted on the wiring substrate,
The semiconductor chip is
A first insulating film,
A pad formed on the first insulating film;
A second insulating film formed on the first insulating film and having a first opening that exposes a part of the pad;
A pillar electrode formed on the pad exposed from the first opening;
Have
The wiring board is
Terminal,
A third insulating film having a second opening that exposes a portion of the terminal;
Have
The second insulating film of the semiconductor chip has a first main surface opposite to the wiring substrate,
The third insulating film of the wiring substrate has a second main surface facing the semiconductor chip,
In a plan view, the pillar electrode includes the first opening, and a part of the pillar electrode overlaps the second insulating film.
The pillar electrode of the semiconductor chip and the terminal of the wiring substrate are connected via a solder layer interposed between the pillar electrode and the terminal.
In a plan view, the second opening is included in the pillar electrode,
The semiconductor device according to claim 1, wherein a third diameter of the second opening is not less than 0.7 times and not more than 0.8 times a first diameter of the pillar electrode.

[Supplementary Note 2]
A semiconductor device comprising: a wiring substrate; and a semiconductor chip mounted on the wiring substrate,
The semiconductor chip is
A first insulating film,
A pad formed on the first insulating film;
A second insulating film formed on the first insulating film and having a first opening that exposes a part of the pad;
A pillar electrode formed on the pad exposed from the first opening;
Have
The wiring board is
Terminal,
A third insulating film having a second opening that exposes a portion of the terminal;
Have
The second insulating film of the semiconductor chip has a first main surface opposite to the wiring substrate,
The third insulating film of the wiring substrate has a second main surface facing the semiconductor chip,
In a plan view, the pillar electrode includes the first opening, and a part of the pillar electrode overlaps the second insulating film.
The pillar electrode of the semiconductor chip and the terminal of the wiring substrate are connected via a solder layer interposed between the pillar electrode and the terminal.
The semiconductor device, wherein the pad includes the pillar electrode in plan view.

[Supplementary Note 3]
A semiconductor device comprising: a wiring substrate; and a semiconductor chip mounted on the wiring substrate,
The semiconductor chip is
A first insulating film,
A pad formed on the first insulating film;
A second insulating film formed on the first insulating film and having a first opening that exposes a part of the pad;
A pillar electrode formed on the pad exposed from the first opening;
Have
The wiring board is
Terminal,
A third insulating film having a second opening that exposes a portion of the terminal;
Have
The second insulating film of the semiconductor chip has a first main surface opposite to the wiring substrate,
The third insulating film of the wiring substrate has a second main surface facing the semiconductor chip,
In a plan view, the pillar electrode includes the first opening, and a part of the pillar electrode overlaps the second insulating film.
The pillar electrode of the semiconductor chip and the terminal of the wiring substrate are connected via a solder layer interposed between the pillar electrode and the terminal.
A semiconductor device in which 1.5 ≦ D ₄ / D ₃ ≦ 2, where D ₃ is a diameter of the second opening of the third insulating film and D ₄ is a diameter of the terminal.

BL solder balls BS base layer CB wiring board CL copper layer CP semiconductor chip _D 1, _{D 2} diameter _h 1, _{h 2} thickness IL1, IL2, IL3, IL4, IL5, IL6 interlayer insulating film LA land M1, M2, M3 , M4 Wiring NL Nickel layer OP1, OP2, OP3, OP3a, OP3b, OP4, SH Opening PA, PA1 Insulating film PA2 Resin film PA2a Upper surface PD Pad PKG Semiconductor device PL Pillar electrode Qn, Qp MISFET
SD, SD1, SD2 solder layer SE seed layer SB semiconductor substrate SR1, SR2 resist layer SR1a top ST isolation region _T 1, _{T 2} thickness TE terminal TE1 copper layer TE2 nickel layer UFR resin portion V1, V2, V3, V4, V5 via part

Claims (20)

A semiconductor device comprising: a wiring substrate; and a semiconductor chip mounted on the wiring substrate,
The semiconductor chip is
A first insulating film,
A pad formed on the first insulating film;
A second insulating film formed on the first insulating film and having a first opening that exposes a part of the pad;
A pillar electrode formed on the pad exposed from the first opening;
Have
The wiring board is
Terminal,
A third insulating film having a second opening that exposes a portion of the terminal;
Have
The second insulating film of the semiconductor chip has a first main surface opposite to the wiring substrate,
The third insulating film of the wiring substrate has a second main surface facing the semiconductor chip,
In a plan view, the pillar electrode includes the first opening, and a part of the pillar electrode overlaps the second insulating film.
The pillar electrode of the semiconductor chip and the terminal of the wiring substrate are connected via a solder layer interposed between the pillar electrode and the terminal.
The semiconductor device according to claim 1, wherein a first thickness of the pillar electrode from the first major surface is a half or more of a second thickness of the solder layer from the second major surface and a second thickness or less. In the semiconductor device according to claim 1,
The sum total of said 1st thickness and said 2nd thickness is 0.5 times or more of the 1st diameter of said pillar electrode, and is 0.8 times or less. In the semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein a second diameter of the first opening is not less than 0.4 times and not more than 0.75 times a first diameter of the pillar electrode. In the semiconductor device according to claim 1,
The second insulating film has a laminated structure of an inorganic insulating film and a resin film on the inorganic insulating film,
The inorganic insulating film has a third opening,
The resin film has a fourth opening,
In a plan view, the third opening includes the fourth opening,
The semiconductor device according to claim 1, wherein the first opening is formed by the fourth opening of the resin film. In the semiconductor device according to claim 4,
The semiconductor device, wherein the pillar electrode is in contact with the resin film but is not in contact with the inorganic insulating film. In the semiconductor device according to claim 4,
The semiconductor device, wherein the resin film is a polyimide resin film. In the semiconductor device according to claim 6,
The semiconductor device, wherein the inorganic insulating film is made of a silicon nitride film or a silicon oxynitride film. In the semiconductor device according to claim 4,
The semiconductor device, wherein the resin film is an insulating film on the top layer of the semiconductor chip. In the semiconductor device according to claim 4,
The semiconductor device, wherein a third thickness of the resin film between the pad and the pillar electrode is larger than a fourth thickness of the pad and smaller than the first thickness. In the semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein a planar shape of the first opening is circular. In the semiconductor device according to claim 10,
The semiconductor device according to claim 1, wherein a planar shape of the pillar electrode is circular. In the semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein in plan view, a third diameter of the second opening is smaller than a first diameter of the pillar electrode. In the semiconductor device according to claim 1,
The semiconductor device, wherein the second opening is included in the pillar electrode in a plan view. In the semiconductor device according to claim 1,
The semiconductor chip has a semiconductor substrate,
The semiconductor device according to claim 5, wherein a fifth thickness of the semiconductor substrate is 25 to 300 μm. In the semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the pillar electrode is a Cu pillar electrode mainly made of copper. In the semiconductor device according to claim 1,
A semiconductor device, further comprising a resin portion filled between the wiring substrate and the semiconductor chip. In the semiconductor device according to claim 1,
The semiconductor chip has a wiring structure including a plurality of wiring layers,
The semiconductor device, wherein the wiring structure includes a low dielectric constant insulating film. In the semiconductor device according to claim 1,
The semiconductor device, wherein the third insulating film is an insulating film on the top layer of the wiring substrate. In the semiconductor device according to claim 1,
The semiconductor device, wherein the third insulating film is a solder resist layer. A semiconductor device comprising: a wiring substrate; and a semiconductor chip mounted on the wiring substrate,
The semiconductor chip is
A first insulating film,
A pad formed on the first insulating film;
A second insulating film formed on the first insulating film and having a first opening that exposes a part of the pad;
A pillar electrode formed on the pad exposed from the first opening;
Have
The wiring board is
Terminal,
A third insulating film having a second opening that exposes a portion of the terminal;
Have
The second insulating film of the semiconductor chip has a first main surface opposite to the wiring substrate,
The third insulating film of the wiring substrate has a second main surface facing the semiconductor chip,
In a plan view, the pillar electrode includes the first opening, and a part of the pillar electrode overlaps the second insulating film.
The pillar electrode of the semiconductor chip and the terminal of the wiring substrate are connected via a solder layer interposed between the pillar electrode and the terminal.
The first thickness of the pillar electrode from the first main surface is a half or more of the second thickness of the solder layer from the second main surface and the second thickness or less,
The sum of the first thickness and the second thickness is at least 0.5 times and at most 0.8 times the first diameter of the pillar electrode,
The second diameter of the first opening is at least 0.4 times and at most 0.75 times the first diameter of the pillar electrode,
The second insulating film has a laminated structure of an inorganic insulating film and a resin film on the inorganic insulating film,
The inorganic insulating film has a third opening,
The resin film has a fourth opening,
In a plan view, the third opening includes the fourth opening,
The semiconductor device according to claim 1, wherein the first opening is formed by the fourth opening of the resin film.

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