CN102194706B - Encapsulation process - Google Patents
Encapsulation process Download PDFInfo
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- CN102194706B CN102194706B CN 201010123574 CN201010123574A CN102194706B CN 102194706 B CN102194706 B CN 102194706B CN 201010123574 CN201010123574 CN 201010123574 CN 201010123574 A CN201010123574 A CN 201010123574A CN 102194706 B CN102194706 B CN 102194706B
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- semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
The invention relates to an encapsulation process. The encapsulation process comprises the following steps of: arranging a semiconductor base material onto a carrier, wherein one side, facing the carrier, of the semiconductor base material is provided with a plurality of connection points; thinning the semiconductor base material by the back side of the semiconductor base material; forming a plurality of through silicon penetrating holes in the thinned semiconductor base material; forming a plurality of first connection pads on the semiconductor base material, wherein the first connection pads are connected with the through silicon penetrating holes respectively; connecting a plurality of chips and the semiconductor base material, wherein the chips are electrically connected with the corresponding first connection pads respectively; forming encapsulation colloid on the semiconductor base material so as to cover the chips and the first connection pads; separating the semiconductor base material from the carrier, and forming a plurality of solder balls on the semiconductor base material; and cutting the encapsulation colloid and the semiconductor base material.
Description
Technical field
The present invention relates to a kind of encapsulating structure, and be particularly related to a kind of Gestapelte halbleiterbausteine encapsulating structure.
Background technology
In information society now, the user pursues high-speed, high-quality, polyfunctional electronic product.With regard to product appearance, the design of electronic product is to stride forward towards light, thin, short, little trend.Therefore, the Electronic Packaging technical development goes out such as multiple semiconductor element encapsulation technologies such as Gestapelte halbleiterbausteine encapsulation.
The Gestapelte halbleiterbausteine encapsulation is to utilize the mode of vertical stacking that a plurality of semiconductor elements are packaged in the same encapsulating structure, so packaging density can be promoted so that the packaging body miniaturization, and the mode that can utilize solid to pile up shortens the path of the signal transmission between the semiconductor element, with signal transmitting speed between the lifting semiconductor element, and the semiconductor element of difference in functionality can be combined in the same packaging body.
The manufacture method of known a kind of Gestapelte halbleiterbausteine encapsulation is in having straight-through silicon wafer perforation (Through Silicon Via with chip-stacked, TSV) on the wafer carrier, to carry out the encapsulation of wafer scale, and after finishing encapsulation, wafer carrier is cut together with the sealing on it, to form a plurality of independent packaging units.Each independent packaging units can be connected with the circuit external plate by the soldered ball that is formed on the wafer bottom surface.
Yet, known technology is to form soldered ball in the wafer carrier bottom earlier, the wafer carrier that directly will have soldered ball afterwards is disposed on the carrier, and soldered ball on the wafer carrier is imbedded in the adhesion glue-line on the carrier, up to finishing the wafer-class encapsulation step, and wafer carrier and carrier after separating just expose the soldered ball that is positioned at the wafer carrier bottom surface.Therefore, when the bottom surface of wafer carrier forms larger-size soldered ball, this large-sized soldered ball will be difficult to carrier on the firm combination of adhesion glue-line, thereby influence the technology reliability.
Summary of the invention
The invention provides a kind of packaging technology, when it can avoid known Gestapelte halbleiterbausteine package application wafer-class encapsulation technology, because adopt the large scale soldered ball, and cause engaging between wafer carrier and the carrier bad, influence the problem of technology reliability.
For specifically describing content of the present invention, at this a kind of packaging technology is proposed.At first, the semiconductor base material is disposed on the carrier, wherein semiconductor substrate has towards a first surface of carrier and is positioned at a plurality of contacts on the first surface.Come the thinning semiconductor substrate by semiconductor substrate with respect to the dorsal part of first surface, wherein the semiconductor substrate after the thinning has the second surface with respect to first surface.(Through Silicon Via is TSV) in the semiconductor substrate of this after thinning to form a plurality of straight-through silicon perforation.Straight-through silicon perforation is corresponding and connect contact respectively.Then, form a plurality of first connection pads on the second surface of semiconductor substrate, the straight-through silicon perforation of corresponding and connection respectively of described first connection pad.Engage a plurality of chips to the second surface of semiconductor substrate, wherein said chip is electrically connected to corresponding first connection pad respectively.Form a packing colloid on the second surface of semiconductor substrate, wherein packing colloid covers chip and first connection pad.Separating semiconductor base material and carrier form a plurality of soldered balls then on the first surface of semiconductor substrate, and wherein said soldered ball is electrically connected to corresponding contact respectively.Afterwards, cut packing colloid and semiconductor substrate simultaneously, to form a plurality of encapsulation units.
In one embodiment of this invention, described packaging technology also is included in semiconductor substrate is disposed at before the carrier, forms one and reroutes layer on the first surface of semiconductor substrate.This surface of rerouting layer has a plurality of second connection pads, and second connection pad is electrically connected to contact respectively.In addition, described packaging technology more can form a ball substrate layer at each second connection pad.
In one embodiment of this invention, described packaging technology also is included in after separating semiconductor base material and the carrier and before forming soldered ball, forms one and reroute layer on the first surface of semiconductor substrate.Described surface of rerouting layer has a plurality of second connection pads, and second connection pad is electrically connected to contact respectively.In addition, described packaging technology also is included in and forms a ball substrate layer on each second connection pad.
In one embodiment of this invention, described packaging technology also is included in and forms a ball substrate layer on each first connection pad.
In one embodiment of this invention, joint chip to the method for semiconductor substrate comprises with flip-chip flip-chip bonded technology each chip is engaged to corresponding first connection pad via a plurality of conductive projections.
In one embodiment of this invention, described packaging technology also is included in joint chip to semiconductor substrate and before forming packing colloid, forms a primer between each chip and semiconductor substrate, wherein primer coated with conductive projection.
Based on above-mentioned, the present invention is disposed at semiconductor substrate on the carrier earlier, and waits to finish the wafer-class encapsulation step, and semiconductor substrate and carrier after separating, just forms soldered ball on the first surface of semiconductor substrate.Therefore, the packaging technology that the present invention proposes can be avoided adopting between semiconductor substrate that the large scale soldered ball may cause and the carrier and engage bad problem, helps to promote the technology reliability.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended diagram to be described in detail below.
Description of drawings
Figure 1A～1K illustrates a kind of packaging technology according to one embodiment of the invention in regular turn.
Fig. 2 A～2K illustrates a kind of packaging technology according to another embodiment of the present invention in regular turn.
Fig. 3 A～3E illustrates the part flow process according to a kind of packaging technology of one embodiment of the invention in regular turn.
Description of reference numerals
102,202: encapsulation unit
110,210,310: semiconductor substrate
110a, 210a, 310a: first surface
110b, 210b, 310b: second surface
112,212,312: contact
114,214,314: protective layer
116,216: the first connection pads
116a, 216a: ball substrate layer
119,219: the side of semiconductor substrate
120,220,320: layer reroutes
122,222: the second connection pads
322: connection pad
122a, 222a, 322a: ball substrate layer
130,230,330: carrier
132,232,332: adhesion coating
140,240,340: straight-through silicon perforation
342: the conduction duct
342a a: end in conduction duct
150,250,350: chip
152,252,352: conductive projection
160,260: primer
170,270: packing colloid
370: scolder
179,279: the side of packing colloid
180,280: soldered ball
Embodiment
Form soldered ball in the wafer carrier bottom earlier compared to known technology, and the wafer carrier that will have soldered ball is disposed on the carrier, make soldered ball on the wafer carrier imbed technology in the adhesion glue-line on the carrier, the present invention engages semiconductor substrate earlier with carrier, wait to finish wafer-class encapsulation technology and semiconductor substrate and carrier after separating, on the first surface of semiconductor substrate bottom, form soldered ball again.Below enumerate a plurality of embodiment process of the present invention is described.
Figure 1A～1K illustrates a kind of packaging technology according to one embodiment of the invention in regular turn.
At first, shown in Figure 1A, provide semiconductor substrate 110, it for example is common silicon wafer or is made by other semi-conducting materials.Semiconductor substrate 110 has a first surface 110a and is positioned at a plurality of contacts 112 on the first surface 110a.Semiconductor substrate 110 inside can according to prior art make internal connection-wire structure or in be embedded with source or passive component (not illustrating).In addition, but the first surface 110a of semiconductor substrate 110 goes up protective mulch 114, with protection contact 112.
Be noted that the semiconductor substrate 110 of present embodiment can encapsulate with one or more chip as the support plate of wafer-class encapsulation technology simultaneously, only because of the restriction of drawing size, present embodiment is only drawn local semiconductor substrate 110.
Then, as shown in Figure 1B, in some cases, present embodiment can be chosen on the first surface 110a of semiconductor substrate 110, namely on the protective layer 114, makes layer (the Redistribution Layer) 120 that reroute in addition.Layer 120 the surface of rerouting has a plurality of second connection pads 122, its circuit by layer 120 inside of rerouting is electrically connected to the contact 112 on the first surface 110a of semiconductor substrate 110 respectively, in order to the position of the external contact of readjusting semiconductor substrate 110.At this, can also form ball substrate layer (Under Bump Metallurgy Layer, UBM layer) 122a on second connection pad 122, increase the then effect of soldered ball and second connection pad 122 of follow-up formation thus.
The situation that step after the present embodiment is formed with layer (the Redistribution Layer) 120 that reroute with the semiconductor substrate 110 surfaces explanation that continues.
Hold above-mentionedly, then, shown in Fig. 1 C, the first surface 110a of semiconductor substrate 110 is disposed on the carrier 130 towards carrier 130.Carrier 130 surfaces for example are coated with adhesion coating 132, and semiconductor substrate 110 is fixed on the carrier 130 by adhesion coating 132, and second connection pad 122 that wherein is positioned at layer 120 surface of rerouting directly contacts with adhesion coating 132.Simultaneously, come thinning semiconductor substrate 110 by semiconductor substrate 110 with respect to the dorsal part of first surface 110a, make semiconductor substrate 110 after the thinning have the second surface 110b with respect to first surface 110a.
Then, shown in Fig. 1 D, (Through Silicon Via, TSV) 140 in semiconductor substrate 110 to form a plurality of straight-through silicon perforation.Straight-through silicon perforation 140 is corresponding and be connected to contact 112 respectively, and the circuit by layer 120 inside of rerouting is connected to second connection pad 122 respectively.
Then, shown in Fig. 1 E, form a plurality of first connection pads 116 on the second surface 110b of semiconductor substrate 110.The straight-through silicon perforation 140 of corresponding and connection respectively of first connection pad 116.In addition, present embodiment can be chosen on first connection pad 116 and to form ball substrate layer 116a, increases the effect of following of projection and first connection pad 116 on the follow-up chip thus.
Afterwards, shown in Fig. 1 F, engage a plurality of chips 150 to the second surface 110b of semiconductor substrate 110, make chip 150 be electrically connected to first connection pad 116 on the second surface 110b.In the present embodiment, for example be with flip-chip flip-chip bonded technology a plurality of conductive projections 152 of each chip 150 bottom it to be engaged to corresponding first connection pad 116.
Then, shown in Fig. 1 G, present embodiment can select to form a primer 160 between each chip 150 and semiconductor substrate 110, makes primer 160 coated with conductive projections 152.Yet present embodiment also can be selected not form primer 160 and directly carry out subsequent technique.
Shown in Fig. 1 H, after joint chip 150 and semiconductor substrate 110, form a packing colloid 170 on the second surface 110b of semiconductor substrate 110, make packing colloid 170 cover all chip 150, conductive projection 152 and first connection pads 116 on the semiconductor substrate 110.If present embodiment forms primer 160 between chip 150 and semiconductor substrate 110 before being chosen in and forming packing colloid 170, the packing colloid 170 that then herein forms can cover primer 160.Otherwise if the step shown in Fig. 1 G is not carried out in the present embodiment selection, the packing colloid 170 that then herein forms can replace primers 160, directly inserts the space between the conductive projection 152.
Then, shown in Fig. 1 I, separating semiconductor base material 110 and carrier 130 are to expose second connection pad 122 on the layer 120 that reroutes.And, after separating semiconductor base material 110 and carrier 130, form second connection pad 122 of a plurality of soldered balls 180 on the layer 120 that reroutes as Fig. 1 J, make soldered ball 180 be electrically connected to corresponding contact 112 respectively via the layer 120 that reroutes.
Afterwards, shown in Fig. 1 K, carry out a singulation technology, namely cut packing colloid 170 and semiconductor substrate 110 simultaneously, to form a plurality of encapsulation units 102.Because packing colloid 170 and semiconductor substrate 110 are simultaneously cropped, so the side 179 of packing colloid 170 can align with the side 119 of semiconductor substrate 110, and chip 150 is coated in the packing colloid 170.
Based on above-mentioned, present embodiment is disposed at semiconductor substrate 110 on the carrier 130 earlier, and waits to finish after the wafer-class encapsulation step of Fig. 1 D～1I, just forms soldered ball 180 on the first surface 110a of semiconductor substrate 110.Therefore, present embodiment need not considered to engage bad problem between semiconductor substrate 110 bottoms make semiconductor substrate 110 that large scale soldered ball 180 may cause and carrier 130, helps to promote technology reliability and selectivity.
Previous embodiment just form the layer that reroutes at semiconductor substrate earlier, yet the present invention was not limited to this before semiconductor substrate is disposed at carrier.For example, the present invention can also be chosen in and finish after wafer-class encapsulation and separating semiconductor base material and the carrier, forms to reroute layer on semiconductor substrate again.Hereinafter will describe for another embodiment again.
Fig. 2 A～2K illustrates a kind of packaging technology according to another embodiment of the present invention in regular turn.
At first, shown in Fig. 2 A, provide semiconductor substrate 210, it for example is common silicon wafer or is made by other semi-conducting materials.Semiconductor substrate 210 has a first surface 210a and is positioned at a plurality of contacts 212 on the first surface 210a.Semiconductor substrate 210 inside can according to prior art make internal connection-wire structure or in be embedded with source or passive device (not illustrating).In addition, but the first surface 210a of semiconductor substrate 210 goes up protective mulch 214, with protection contact 212.
Be noted that the semiconductor substrate 210 of present embodiment can encapsulate with one or more chip as the support plate of wafer-class encapsulation technology simultaneously, only because of the restriction of drawing size, present embodiment is only drawn local semiconductor substrate 210.
Then, shown in Fig. 2 B, the first surface 210a of semiconductor substrate 210 is disposed on the carrier 230 towards carrier 230.Carrier 230 surfaces for example are coated with adhesion coating 232, and semiconductor substrate 210 is fixed on the carrier 230 by adhesion coating 232, and the contact 212 that wherein is positioned on the first surface 210a of semiconductor substrate 210 directly contacts with adhesion coating 232.Simultaneously, come thinning semiconductor substrate 210 by semiconductor substrate 210 with respect to the dorsal part of first surface 210a, make semiconductor substrate 210 after the thinning have the second surface 210b with respect to first surface 210a.
Then, shown in Fig. 2 C, (Through Silicon Via, TSV) 240 in semiconductor substrate 210 to form a plurality of straight-through silicon perforation.Straight-through silicon perforation 240 is corresponding and be connected to contact 212 respectively.
Then, shown in Fig. 2 D, form a plurality of first connection pads 216 on the second surface 210b of semiconductor substrate 210.The straight-through silicon perforation 240 of corresponding and connection respectively of first connection pad 216.In addition, present embodiment can be chosen on first connection pad 216 and to form ball substrate layer 216a, increases the effect of following of projection and first connection pad 216 on the follow-up chip thus.
Afterwards, shown in Fig. 2 E, engage a plurality of chips 250 to the second surface 210b of semiconductor substrate 210, make chip 250 be electrically connected to first connection pad 216 on the second surface 210b.In the present embodiment, for example be with flip-chip flip-chip bonded technology a plurality of conductive projections 252 of each chip 250 bottom it to be engaged to corresponding first connection pad 216.
Then, shown in Fig. 2 F, present embodiment can select to form a primer 260 between each chip 250 and semiconductor substrate 210, makes primer 260 coated with conductive projections 252.Yet, in other embodiments, also can select not form primer 260 and directly carry out subsequent technique.
Shown in Fig. 2 G, after joint chip 250 and semiconductor substrate 210, form a packing colloid 270 on the second surface 210b of semiconductor substrate 210, make packing colloid cover chip 250, conductive projection 252 and first connection pad 216.If present embodiment forms primer 260 between chip 250 and semiconductor substrate 210 before being chosen in and forming packing colloid 270, the packing colloid 270 that then herein forms can cover primer 260.Anti-, if the step shown in Fig. 2 F is not carried out in the present embodiment selection, the packing colloid 270 that then herein forms can replace primer 260, directly inserts the space between the conductive projection 252.
Then, shown in Fig. 2 H, separating semiconductor base material 210 and carrier 230 are with the contact 212 on the first surface 210a that exposes semiconductor substrate 210.And shown in Fig. 2 I, in some cases, present embodiment can be chosen on the first surface 210a of semiconductor substrate 210, namely on the protective layer 214, makes the layer 220 that reroutes in addition.Layer 220 the surface of rerouting has a plurality of second connection pads 222, its circuit by layer 220 inside of rerouting is electrically connected to the contact 212 on the first surface 210a of semiconductor substrate 210 respectively, in order to the position of the external contact of readjusting semiconductor substrate 210.At this, can also form ball substrate layer 222a on second connection pad 222, increase the then effect of soldered ball and second connection pad 222 of follow-up formation thus.
The situation that step after the present embodiment is formed with layer (the Redistribution Layer) 120 that reroute with the semiconductor substrate 110 surfaces explanation that continues.
Afterwards, shown in Fig. 2 J, after separating semiconductor base material 210 and carrier 230, form second connection pad 222 of a plurality of soldered balls 280 on the layer 220 that reroutes, make soldered ball 280 be electrically connected to corresponding contact 212 respectively via the layer 220 that reroutes.
Then, shown in Fig. 2 K, carry out a singulation technology, namely cut packing colloid 270 and semiconductor substrate 210 simultaneously, to form a plurality of encapsulation units 202.Because packing colloid 270 and semiconductor substrate 210 are simultaneously cropped, so the side 279 of packing colloid 270 can align with the side 219 of semiconductor substrate 210, and chip 250 is coated in the packing colloid 270.
Based on above-mentioned, present embodiment is disposed at semiconductor substrate 210 on the carrier 230 earlier, and waits to finish after the wafer-class encapsulation step of Fig. 2 C～2I, just forms soldered ball 280 on the first surface 210a of semiconductor substrate 210.Therefore, present embodiment need not considered to engage bad problem between semiconductor substrate 210 bottoms make semiconductor substrate 210 that large scale soldered ball 280 may cause and carrier 230, helps to promote technology reliability and selectivity.On the other hand, compared to previous embodiment, present embodiment is chosen in to be finished after wafer-class encapsulation and separating semiconductor base material and the carrier, just forms to reroute layer on semiconductor substrate.
Aforementioned a plurality of embodiment selects earlier semiconductor substrate to be carried out thinning, makes a plurality of straight-through silicon perforation again in semiconductor substrate.Yet, in other embodiments of the invention, can also in semiconductor substrate, make the conduction duct earlier, again semiconductor substrate is carried out thinning, make the conduction duct expose semiconductor substrate, form a plurality of straight-through silicon perforation.
Fig. 3 A～3E illustrates the part flow process according to a kind of packaging technology of one embodiment of the invention in regular turn.
At first, as shown in Figure 3A, provide semiconductor substrate 310, it for example is common silicon wafer or is made by other semi-conducting materials.Semiconductor substrate 310 has a first surface 310a and is positioned at a plurality of contacts 312 on the first surface 310a.Also have a plurality of conductions duct 342 in the semiconductor substrate 310, corresponding and be connected to contact 312 respectively, and semiconductor substrate 310 inside can according to prior art make internal connection-wire structure or in be embedded with source or passive device (not illustrating).In addition, but the first surface 310a of semiconductor substrate 310 goes up protective mulch 314, with protection contact 312.
Be noted that the semiconductor substrate 310 of present embodiment can encapsulate with one or more chip as the support plate of wafer-class encapsulation technology simultaneously, only because of the restriction of drawing size, present embodiment is only drawn local semiconductor substrate 310.
Then, described as previous embodiment shown in Fig. 3 B, present embodiment can be chosen on the first surface 310a of semiconductor substrate 310, namely on the protective layer 314, makes layer (the Redistribution Layer) 320 that reroute in addition.Layer 320 the surface of rerouting has a plurality of connection pads 322, and its circuit by layer 320 inside of rerouting is electrically connected to the contact 312 on the first surface 310a of semiconductor substrate 310 respectively, in order to the position of the external contact of readjusting semiconductor substrate 310.At this, can also form ball substrate layer 322a on the connection pad 322, increase the then effect of soldered ball and the connection pad 322 of follow-up formation thus.
The situation that step system after the present embodiment is formed with the layer 320 that reroutes with the semiconductor substrate 310 surfaces explanation that continues.
Hold above-mentionedly, then, shown in Fig. 3 C, the first surface 310a of semiconductor substrate 310 is disposed on the carrier 330 towards carrier 330.Carrier 330 surfaces for example are coated with adhesion coating 332, and semiconductor substrate 310 is fixed on the carrier 330 by adhesion coating 332, and the connection pad 322 that wherein is positioned at layer 320 surface of rerouting directly contacts with adhesion coating 332.
And, shown in Fig. 3 D, come thinning semiconductor substrate 310 by semiconductor substrate 310 with respect to the dorsal part of first surface 310a, wherein the semiconductor substrate after the thinning 310 has the second surface 310b with respect to first surface 310a, and an end 342a in each conduction duct 342 protrudes second surface 310b and becomes logical silicon perforation 340 always.Straight-through silicon perforation 340 is connected to connection pad 322 by the circuit of layer 320 inside of rerouting respectively.
Then, shown in Fig. 3 E, engage a plurality of chips 350 to the straight-through silicon perforation 340 of exposing.In the present embodiment, for example be with flip-chip flip-chip bonded technology a plurality of conductive projections 352 of each chip 350 bottom it to be engaged to corresponding straight-through silicon perforation 340.Conductive projection 352 for example is connected by scolder 370 with corresponding straight-through silicon perforation 340.Conductive projection 352 can be as the column-like projection block that illustrates among Fig. 1 D or the projection of other kenels.
Afterwards, can carry out the step as Fig. 1 G～1K, to form the encapsulation unit 102 that is illustrated as Fig. 1 K.The detailed technology content can repeat no more with reference to the description of previous embodiment herein.
In addition, please refer to the embodiment that Fig. 2 A～2K illustrates, except before semiconductor substrate is disposed at carrier, just form outside the technical scheme of the layer that reroutes at semiconductor substrate earlier, manufacture method in conjunction with aforesaid straight-through silicon perforation, the present invention can also be chosen in and finish after wafer-class encapsulation and separating semiconductor base material and the carrier, just forms to reroute layer on semiconductor substrate.
Though the present invention discloses as above with embodiment; so it is not in order to limit the present invention; those of ordinary skill in the technical field under any; without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim person of defining.
Claims (6)
1. packaging technology comprises:
The semiconductor base material is disposed on the carrier, wherein this semiconductor substrate has towards a first surface of this carrier and is positioned at a plurality of contacts on this first surface, wherein before this semiconductor substrate is disposed at this carrier, form one and reroute layer on this first surface of this semiconductor substrate, this surface of rerouting layer has a plurality of second connection pads, and those second connection pads are electrically connected to those contacts respectively;
Come this semiconductor substrate of thinning by this semiconductor substrate with respect to the dorsal part of this first surface, this semiconductor substrate after the thinning has the second surface with respect to this first surface;
Form a plurality of straight-through silicon and bore a hole in this semiconductor substrate, those straight-through silicon perforation are corresponding and connect those contacts respectively;
Form a plurality of first connection pads on this second surface of this semiconductor substrate, those first connection pads are corresponding and connect those straight-through silicon perforation respectively;
Engage a plurality of chips to this second surface of this semiconductor substrate, those chips are electrically connected to corresponding those first connection pads respectively;
Form a packing colloid on this second surface of this semiconductor substrate, this packing colloid covers those chips and those first connection pads;
Separate this semiconductor substrate and this carrier, afterwards, form a plurality of soldered balls on this first surface of this semiconductor substrate, those soldered balls are electrically connected to corresponding those contacts respectively; And
Cut this packing colloid and this semiconductor substrate simultaneously, to form a plurality of encapsulation units.
2. packaging technology as claimed in claim 1 wherein engages those chips to the method for this semiconductor substrate and comprises with flip-chip flip-chip bonded technology each chip is engaged to corresponding those first connection pads via a plurality of conductive projections.
3. packaging technology as claimed in claim 2 also is included in and engages those chips to this semiconductor substrate and before forming this packing colloid, forms a primer between each chip and this semiconductor substrate, and this primer coats those conductive projections.
4. packaging technology comprises:
The semiconductor base material is disposed on the carrier, wherein this semiconductor substrate has towards a first surface of this carrier and is positioned at a plurality of contacts on this first surface, and has a plurality of conductions duct in this semiconductor substrate, corresponding and be connected to those contacts respectively, before this semiconductor substrate is disposed at this carrier, form one and reroute layer on this first surface of this semiconductor substrate, this surface of rerouting layer has a plurality of connection pads, and those connection pads are electrically connected to those contacts respectively;
Come this semiconductor substrate of thinning by this semiconductor substrate with respect to the dorsal part of this first surface, this semiconductor substrate after the thinning has the second surface with respect to this first surface, and an end in each conduction duct protrudes this second surface and becomes logical silicon perforation always;
Engage a plurality of chips to this second surface of this semiconductor substrate, those chips are electrically connected to corresponding those straight-through silicon perforation respectively;
Form a packing colloid on this second surface of this semiconductor substrate, this packing colloid covers those chips;
Separate this semiconductor substrate and this carrier, afterwards, form a plurality of soldered balls on this first surface of this semiconductor substrate, those soldered balls are electrically connected to corresponding those contacts respectively; And
Cut this packing colloid and this semiconductor substrate simultaneously, to form a plurality of encapsulation units.
5. packaging technology as claimed in claim 4 wherein engages those chips to the method for this semiconductor substrate and comprises with flip-chip flip-chip bonded technology each chip is engaged to corresponding those first connection pads via a plurality of conductive projections.
6. packaging technology as claimed in claim 5 also is included in and engages those chips to this semiconductor substrate and before forming this packing colloid, forms a primer between each chip and this semiconductor substrate, and this primer coats those conductive projections.
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| CN 201010123574 CN102194706B (en) | 2010-03-02 | 2010-03-02 | Encapsulation process |
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| CN 201010123574 CN102194706B (en) | 2010-03-02 | 2010-03-02 | Encapsulation process |
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| CN2570980Y (en) * | 2002-09-23 | 2003-09-03 | 威盛电子股份有限公司 | Packaging arrangement of superintegrated circuit |
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| CN101197360A (en) * | 2006-12-07 | 2008-06-11 | 育霈科技股份有限公司 | Multi-chips package and method of forming the same |
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