CN108962773A - Fan-out package structure and its manufacturing method - Google Patents
Fan-out package structure and its manufacturing method Download PDFInfo
- Publication number
- CN108962773A CN108962773A CN201810836986.4A CN201810836986A CN108962773A CN 108962773 A CN108962773 A CN 108962773A CN 201810836986 A CN201810836986 A CN 201810836986A CN 108962773 A CN108962773 A CN 108962773A
- Authority
- CN
- China
- Prior art keywords
- conductive column
- chip
- conductive
- fan
- out package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000004806 packaging method and process Methods 0.000 claims abstract description 28
- 238000003466 welding Methods 0.000 claims abstract description 15
- 230000015572 biosynthetic process Effects 0.000 claims abstract 2
- 239000000463 material Substances 0.000 claims description 30
- 239000011521 glass Substances 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 14
- 238000001459 lithography Methods 0.000 claims description 14
- 229910000679 solder Inorganic materials 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 6
- 238000004080 punching Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 36
- 238000000034 method Methods 0.000 description 16
- 238000005538 encapsulation Methods 0.000 description 9
- 230000008569 process Effects 0.000 description 9
- 239000012790 adhesive layer Substances 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- 238000012163 sequencing technique Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
The invention discloses a kind of fan-out package structures, comprising: chip, the chip have first surface, and the first surface includes conductive welding disk；And to the plastic packaging layer that the chip is wrapped up, the plastic packaging layer includes first surface and second surface, wherein second surface is opposite with first surface, it is provided with the first rewiring structure on the first surface, it is provided with the second rewiring structure on a second surface, the plastic packaging layer further includes the first conductive column through first surface and second surface, first conductive column reroutes structure and second first and reroutes formation electrical connection between structure, it further include the second conductive column in plastic packaging layer, second conductive column extends to the conductive welding disk of the chip from first surface, it is formed and is electrically connected between the chip and the first rewiring structure.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, specifically, the present invention relates to fan-out package structure and its systems
Make method.
Background technique
Increasingly develop to miniaturization, intelligence, high-performance and high reliability direction to meet electronic product, chip
Miniaturization, it is intelligent make the quantity of chip package pin while being promoted, the size of packaging pin also drops at the fast speed.
I/O connection terminal is dispersed within chip surface area in traditional flip chip wafer grade encapsulation scheme, to limit I/O
Linking number.Fan-out-type wafer-level packaging can solve this problem, simultaneously because it has miniaturization, low cost and height
The advantages that integrated level, therefore rapidly becoming the selection of novel chip and Wafer level packaging.
The back side of bare chip is usually embedded in the epoxy, then in the front of bare chip by existing fan-out package
It forms dielectric layer and reroutes layer, and formed and be electrically connected between the positive pad of bare chip and rewiring layer, rerouting layer can
Again it plans the route for being connected to peripheral epoxy regions from the I/O on bare chip, then is formed on the pad for rerouting layer
Fan-out package structure is consequently formed in soldered ball raised structures.
The density that fan-out-type wafer-level packaging can be realized three-dimensional stacking is maximum, and outer dimension is minimum, and significantly
Improve chip performance and low-power consumption, but there is also certain defects.It is embedded in the epoxy by the back side of bare chip
In the process, usually bare chip is directly adhered on adhesive layer, then bare chip is transferred in support substrate or bracket.So
And since adhesive layer is easily deformed distortion, the reliability of product encapsulation is leveraged, properties of product are reduced.In addition because of modeling
Sliding caused by closure material is shunk also hardly results in control.
Summary of the invention
Aiming at the problems existing in the prior art, according to one embodiment of present invention, a kind of fan-out package knot is provided
Structure, comprising:
Chip, the chip have first surface, and the first surface includes conductive welding disk；And
To the plastic packaging layer that the chip is wrapped up, the plastic packaging layer includes first surface and second surface, wherein second
Surface is opposite with first surface, is provided with the first rewiring structure on the first surface, is provided with the second weight on a second surface
Wire structures, the plastic packaging layer further include the first conductive column through first surface and second surface, and first conductive column exists
First, which reroutes structure and second, reroutes and forms electrical connection between structure, further includes the second conductive column in plastic packaging layer, and described the
Two conductive columns extend to the conductive welding disk of the chip from first surface, are formed between the chip and the first rewiring structure
Electrical connection.
In one embodiment of the invention, the first rewiring structure and/or the second rewiring structure include N layers and lead
Electric line and the dielectric being arranged between conducting wire, wherein N >=2.
In one embodiment of the invention, the first rewiring structure is led with first conductive column and described second
Electric column is electrically connected, and is provided with one or more external pads and/or solder bump in the first rewiring structure.
In one embodiment of the invention, the second rewiring structure is electrically connected with first conductive column, described
One or more external pads and/or solder bump are provided in second rewiring structure.
According to another embodiment of the invention, a kind of manufacturing method of fan-out package structure is provided, comprising:
The first conductive column and the second conductive column are formed on slide glass, it is conductive that the height of first conductive column is higher than second
Column；
Flip-chip is welded to the slide glass, the conductive welding disk of the chip is welded to second conductive column, and described
One conductive column is dispersed in the outside of the chip；
Plastic packaging is carried out to the chip and slide glass, so that capsulation material encapsulates the chip, first conductive column completely
With second conductive column；
The capsulation material, and the first conductive column of exposure is thinned；
First is formed on the first surface of the capsulation material after being thinned reroutes structure；
Removal slide glass and to slide glass contact side capsulation material second surface carry out it is thinned, the second surface with
First surface is opposite；And
Second is formed on the second surface reroutes structure.
In another embodiment of the present invention, first conductive column of exposure includes by being laser-ablated in described first
Punching above conductive column.
In another embodiment of the present invention, first conductive column of exposure includes while capsulation material and chip is thinned
The back side is to expose the first conductive column.
In another embodiment of the present invention, the manufacturing method of the fan-out package structure further includes in first weight
Soldered ball is formed in wire structures and the second rewiring structure.
In another embodiment of the present invention, forming the first rewiring structure includes:
Dielectric layer is formed on the first surface of capsulation material, certain media layer is removed with sudden and violent by lithography and etching technology
Reveal the first conductive column, then forms one or more layers conductive material, then conduction is not needed by the removal of lithography and etching technology
Region, thus conducting wire needed for being formed.
In another embodiment of the present invention, forming the second rewiring structure includes:
Dielectric layer is formed on the second surface of capsulation material, certain media layer is removed with sudden and violent by lithography and etching technology
Reveal the first conductive column and the second conductive column, then forms one or more layers conductive material, then remove by lithography and etching technology
Conductive region is not needed, thus conducting wire needed for being formed.
Fan-out package structure and its manufacturing method disclosed by the invention, are capable of forming high-precision encapsulating structure.
After flip-chip is welded to slide glass, chip, without offset, avoids welding tolerance in plastic package process.
The conductive column for forming different height in advance on slide glass, plays interconnecting channel, substantially reduces two-sided interconnection
Technology difficulty.After completing plastic packaging, it is thinned to that chip conductive column is exposed, and process operability is strong, risk factor is low.And the encapsulation
The chip of structure is wrapped up comprehensively, high reliablity.
Detailed description of the invention
For the above and other advantages and features for each embodiment that the present invention is furture elucidated, will be presented with reference to attached drawing
The more specific description of various embodiments of the present invention.It is appreciated that these attached drawings only describe exemplary embodiments of the invention, therefore
It is not to be regarded as being restriction on its scope.In the accompanying drawings, in order to cheer and bright, identical or corresponding component will use identical or class
As mark indicate.
Fig. 1 shows the cross-sectional view of fan-out package structure 100 according to an embodiment of the invention.
Fig. 2A to Fig. 2 G shows the diagrammatic cross-section that embodiment according to the present invention forms the process of fan-out package structure.
Fig. 3 shows the flow chart that embodiment according to the present invention forms fan-out package structure.
Specific embodiment
In the following description, with reference to each embodiment, present invention is described.However, those skilled in the art will recognize
Know can in the case where none or multiple specific details or with other replacements and/or addition method, material or component
Implement each embodiment together.In other situations, well known structure, material or operation are not shown or are not described in detail in order to avoid making this
The aspects of each embodiment of invention is obscure.Similarly, for purposes of explanation, specific quantity, material and configuration are elaborated, with
Comprehensive understanding to the embodiment of the present invention is just provided.However, the present invention can be implemented in the case where no specific detail.This
Outside, it should be understood that each embodiment shown in the accompanying drawings is illustrative expression and is not drawn necessarily to scale.
In the present specification, the reference of " one embodiment " or " embodiment " is meaned to combine embodiment description
A particular feature, structure, or characteristic is included at least one embodiment of the invention.Occur in everywhere in this specification short
Language " in one embodiment " is not necessarily all referring to the same embodiment.
It should be noted that the embodiment of the present invention is described processing step with particular order, however this is only
Facilitate and distinguish each step, and is not the sequencing for limiting each step, it in different embodiments of the invention, can be according to work
Skill is adjusted to adjust the sequencing of each step.
In order to solve bare chip to be directly adhered on adhesive layer bare chip is transferred to support substrate again in the prior art
Or on bracket during, adhesive layer is easily deformed distortion, and chip is caused to deviate, influence product encapsulation reliability the problem of,
The present invention primarily serves positioning and fixed function by chip inverse bonding slide glass, reduces plastic packaging and chip offset is caused to influence；Simultaneously should
Scheme can increase subsequent technique precision to avoid inverse bonding tolerance.In addition, being formed just by being embedded to high salient point in advance on slide glass
Anti- two sides interconnecting channel, reduces the technology difficulty of two-sided interconnection, is such as bonded, deep hole technique.It is convex by the way that slide glass is thinned to chip
Point, process operability is strong, is also convenient for subsequent front and back sides interconnection.The finally achievable two-sided three-dimension packaging being fanned out to of chip embedded type
Structure.
Fig. 1 shows the cross-sectional view of fan-out package structure 100 according to an embodiment of the invention.Fan-out-type
Encapsulating structure 100 includes chip 110 and the plastic packaging layer 120 wrapped up chip.
Chip 110 can be a plurality of types of chips, for example, storage chip, processor chips etc..Chip 110 can also
Be stack multiple chips or completed complete partial encapsulation module.Chip 110 can have first surface 110a, chip
110 first surface 110a may include device region, chip circuit (not shown) and conductive welding disk 111.
Plastic packaging layer 120 is encapsulated chip 110.Plastic packaging layer 120 has first surface 120a and second surface 120b,
Wherein second surface 120b is opposite with first surface 120a.The first rewiring structure 130 is provided on first surface 120a.?
The second rewiring structure 140 is provided on second surface 120b.Plastic packaging layer 120, which also has, runs through first surface 120a and the second table
The first conductive column 121 of face 120b, the first conductive column 121, which is used to reroute structure 130 and second first, reroutes structure 140
Between formed electrical connection.Plastic packaging layer 120 also has the second conductive column 122, and the second conductive column 122 is extended to from first surface 120a
The conductive welding disk 111 of chip 110 is electrically connected for being formed between chip 110 and the first rewiring structure 130.
In some embodiments of the invention, the first rewiring structure 130 and the second rewiring structure 140 may include one layer
Or multilayer conductive route and the dielectric being arranged between conducting wire.First reroutes structure 130 and the first conductive column
121 and second conductive column 122 be electrically connected, be provided with one or more external pads in the first rewiring structure 130 and solder be convex
Point.Second rewiring structure 140 is electrically connected with the first conductive column 121, is provided with one or more in the second rewiring structure 140
External pad and solder bump.
In some other embodiment of the invention, the first rewiring structure 130 and/or the second rewiring structure 140 can
It does not include external pad, one or more solder bumps are formed directly into the top of conducting wire.
The external pad of chip 110 can be planned again by the first rewiring structure 130 and the second rewiring structure 140
Position and the route connecting with external circuit realize the two-sided measurements of the chest, waist and hips encapsulating structure being fanned out to of chip embedded type.Due to can be abundant
Using the area on 110 surface of chip and the area for the body structure surface being fanned out to, therefore the surface area that can be used for being electrically interconnected arrangement is big
It is big to increase, so that interconnection density be made to maximize, while the size of soldered ball can be increased.
Fan-out package structure is formed according to one embodiment of present invention below with reference to Fig. 2A to Fig. 2 G and Fig. 3 description
Process.Fig. 2A to Fig. 2 G shows the diagrammatic cross-section that embodiment according to the present invention forms the process of fan-out package structure.
Fig. 3 shows the flow chart that embodiment according to the present invention forms fan-out package structure.
Firstly, providing chip 210 to be packaged, the first surface 210a of chip 210 may include device region, chip circuit (figure
In be not shown) and conductive welding disk 211.
In step 310, the first conductive column 221 and the second conductive column 222 are formed on slide glass 220, as shown in Figure 2 A.First
The height of conductive column 221 is higher than the second conductive column 222.The first conductive column can be determined according to the layout of chip surface conductive welding disk
221 and second conductive column 222 specific location.
In step 320,210 upside-down mounting of chip is welded to slide glass, as shown in Figure 2 B.The conductive welding disk of chip 210 is welded to
Two conductive columns 222, the first conductive column 221 are dispersed in the outside of chip 210.After completing flip chip bonding, the height of the first conductive column 221
The second surface 210b of chip can be higher or lower than.
In step 330, plastic packaging is carried out to chip and slide glass, so that capsulation material 223 encapsulating chip 210, first completely are led
Electric column 221 and the second conductive column 222, as shown in Figure 2 C.
In step 340, capsulation material 223, and the first conductive column 221 of exposure is thinned.In one embodiment of the invention,
As shown in Figure 2 D, the height of the first conductive column 221 is lower than the height of chip 210, therefore, can be by being laser-ablated in the first conduction
It is punched above column 221, to expose the first conductive column 221.It in another embodiment of the present invention, can be by the way that modeling be thinned simultaneously
The first conductive column 221 is exposed at the back of closure material 223 and chip 210.In yet another embodiment of the present invention, first is conductive
The height of column 221 can be higher than the height of the second surface 210b of chip 210, therefore, only by the way that capsulation material 223 is thinned
The first conductive column 221 of exposure.
Next, being formed on the surface of the capsulation material after being thinned in step 350 and rerouting structure.Reroute structure
For the first conductive column 221 to be electrically connected to one or more solder bumps, as shown in Figure 2 E.Structure is rerouted for example, being formed
Concrete technology may include forming dielectric layer on the surface of capsulation material, pass through lithography and etching technology remove certain media layer
With the first conductive column of exposure, one or more layers conductive material then is formed by techniques such as PVD, ALD, chemical plating and plating,
Conductive region is not needed by the removal of lithography and etching technology again, thus conducting wire needed for being formed.Also optionally leading
Second dielectric layer is formed in electric line, and part second dielectric layer is removed by lithography and etching technology and reroutes structure to expose
External pad.In the embodiment shown in Fig. 2 E, rerouting structure includes one layer of rewiring layer.Those skilled in the art answers
The understanding, in other embodiments of the invention, rerouting structure may include that one or more layers reroutes layer.
In step 360, removes slide glass 220 and carry out thinned, such as figure to the capsulation material 223 for contacting side with slide glass 210
Shown in 2F.Dotted portion in Fig. 2 E shows the position of scheduled thinned dead line.It in practical applications, can be according to plastic packaging material
The property of material and the requirement of package dimension determine the position of thinned dead line.The surface of capsulation material 223 after being thinned
On 223a, the first conductive column 221 and the second conductive column 222 are exposed.
In step 370, is formed on the surface 223a of the capsulation material after being thinned and reroute structure.Structure is rerouted to be used for
First conductive column 221 and the second conductive column 222 are electrically connected to one or more solder bumps.Complete 223 phase of capsulation material
Two surfaces are formed after rerouting structure, optionally forms solder bump in the rewiring structure on two surfaces, such as
Shown in Fig. 2 G.For example, the concrete technology for forming rewiring structure may include forming dielectric layer on the surface of capsulation material, pass through
Lithography and etching technology removes certain media layer with the first conductive column of exposure and the second conductive column, then passes through PVD, ALD, chemistry
The techniques such as plating and plating form one or more layers conductive material, then do not need conductive area by the removal of lithography and etching technology
Domain, thus conducting wire needed for being formed.Second dielectric layer is also optionally formed in conducting wire, and passes through lithography and etching
Technology removes the external pad that part second dielectric layer reroutes structure with exposure.
Fan-out package structure and its manufacturing method disclosed by the invention are capable of forming high-precision encapsulation encapsulation knot
Structure.After flip-chip is welded to slide glass, chip, without offset, avoids welding tolerance in plastic package process.
The conductive column for forming different height in advance on slide glass, plays interconnecting channel, substantially reduces two-sided interconnection
Technology difficulty.After completing plastic packaging, it is thinned to that chip conductive column is exposed, and process operability is strong, risk factor is low.And the encapsulation
The chip of structure is wrapped up comprehensively, high reliablity.
Although described above is various embodiments of the present invention, however, it is to be understood that they are intended only as example to present
, and without limitation.For those skilled in the relevant art it is readily apparent that various combinations, modification can be made to it
Without departing from the spirit and scope of the invention with change.Therefore, the width of the invention disclosed herein and range should not be upper
It states disclosed exemplary embodiment to be limited, and should be defined according only to the appended claims and its equivalent replacement.
Claims (10)
1. a kind of fan-out package structure, comprising:
Chip, the chip have first surface, and the first surface includes conductive welding disk；And
To the plastic packaging layer that the chip is wrapped up, the plastic packaging layer includes first surface and second surface, wherein second surface
It is opposite with first surface, it is provided with the first rewiring structure on the first surface, is provided with the second rewiring on a second surface
Structure, the plastic packaging layer further include the first conductive column through first surface and second surface, and first conductive column is first
It reroutes structure and second and reroutes formation electrical connection between structure, further include the second conductive column in plastic packaging layer, described second leads
Electric column extends to the conductive welding disk of the chip from first surface, is formed and is electrically connected between the chip and the first rewiring structure
It connects.
2. fan-out package structure as described in claim 1, which is characterized in that described first reroutes structure and/or second
The dielectric that structure includes N layers of conducting wire and is arranged between conducting wire is rerouted, wherein N >=2.
3. fan-out package structure as claimed in claim 2, which is characterized in that described first reroutes structure and described first
Conductive column and second conductive column electrical connection, be provided in the first rewiring structure one or more external pads and/
Or solder bump.
4. fan-out package structure as claimed in claim 2, which is characterized in that described second reroutes structure and described first
Conductive column is electrically connected, and is provided with one or more external pads and/or solder bump in the second rewiring structure.
5. a kind of manufacturing method of fan-out package structure, comprising:
The first conductive column and the second conductive column are formed on slide glass, the height of first conductive column is higher than the second conductive column；
Flip-chip is welded to the slide glass, the conductive welding disk of the chip is welded to second conductive column, and described first leads
Electric column is dispersed in the outside of the chip；
Plastic packaging is carried out to the chip and slide glass, so that capsulation material encapsulates the chip, first conductive column and institute completely
State the second conductive column；
The capsulation material, and the first conductive column of exposure is thinned；
First is formed on the first surface of the capsulation material after being thinned reroutes structure；
Removal slide glass simultaneously carries out thinned, the second surface and first to the second surface of the capsulation material with slide glass contact side
Surface is opposite；And
Second is formed on the second surface reroutes structure.
6. the manufacturing method of fan-out package structure as claimed in claim 5, which is characterized in that first conductive column of exposure
Including by being laser-ablated in punching above first conductive column.
7. the manufacturing method of fan-out package structure as claimed in claim 5, which is characterized in that first conductive column of exposure
Including capsulation material and chip back being thinned simultaneously to expose the first conductive column.
8. the manufacturing method of fan-out package structure as claimed in claim 5, which is characterized in that further include in first weight
Soldered ball is formed in wire structures and the second rewiring structure.
9. the manufacturing method of fan-out package structure as claimed in claim 5, which is characterized in that form first and reroute structure
Include:
Dielectric layer is formed on the first surface of capsulation material, certain media layer is removed to expose the by lithography and etching technology
Then one conductive column forms one or more layers conductive material, then does not need conductive region by the removal of lithography and etching technology,
To form required conducting wire.
10. the manufacturing method of fan-out package structure as claimed in claim 5, which is characterized in that form second and reroute knot
Structure includes:
Dielectric layer is formed on the second surface of capsulation material, certain media layer is removed to expose the by lithography and etching technology
Then one conductive column and the second conductive column form one or more layers conductive material, then are not required to by the removal of lithography and etching technology
Conductive region is wanted, thus conducting wire needed for being formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810836986.4A CN108962773A (en) | 2018-07-26 | 2018-07-26 | Fan-out package structure and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810836986.4A CN108962773A (en) | 2018-07-26 | 2018-07-26 | Fan-out package structure and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108962773A true CN108962773A (en) | 2018-12-07 |
Family
ID=64464985
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810836986.4A Pending CN108962773A (en) | 2018-07-26 | 2018-07-26 | Fan-out package structure and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108962773A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109786347A (en) * | 2018-12-20 | 2019-05-21 | 华进半导体封装先导技术研发中心有限公司 | The fan-out package structure and packaging method of chip |
| CN110335852A (en) * | 2019-07-18 | 2019-10-15 | 上海先方半导体有限公司 | A kind of fan-out packaging structure and packaging method |
| CN110581079A (en) * | 2019-09-23 | 2019-12-17 | 合肥矽迈微电子科技有限公司 | Fan-out type chip packaging method and fan-out type chip packaging body |
| CN111341796A (en) * | 2020-02-26 | 2020-06-26 | 南通智通达微电子物联网有限公司 | Fan-out type packaging method of image sensor |
| CN111415909A (en) * | 2019-01-07 | 2020-07-14 | 台达电子企业管理（上海）有限公司 | Multi-chip packaged power module |
| CN112582366A (en) * | 2020-12-11 | 2021-03-30 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging structure and preparation method thereof |
| WO2022012498A1 (en) * | 2020-07-13 | 2022-01-20 | 矽磐微电子(重庆)有限公司 | Chip packaging structure and manufacturing method therefor |
| US11316438B2 (en) | 2019-01-07 | 2022-04-26 | Delta Eletronics (Shanghai) Co., Ltd. | Power supply module and manufacture method for same |
| US11399438B2 (en) | 2019-01-07 | 2022-07-26 | Delta Electronics (Shanghai) Co., Ltd. | Power module, chip-embedded package module and manufacturing method of chip-embedded package module |
| WO2023087323A1 (en) * | 2021-11-22 | 2023-05-25 | 华为技术有限公司 | Photoelectric transceiver assembly and method for manufacturing same |
| US11676756B2 (en) | 2019-01-07 | 2023-06-13 | Delta Electronics (Shanghai) Co., Ltd. | Coupled inductor and power supply module |
| WO2024086970A1 (en) * | 2022-10-24 | 2024-05-02 | 广东省科学院半导体研究所 | Fan-out type package structure and preparation method therefor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090236686A1 (en) * | 2006-04-19 | 2009-09-24 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming UBM Fixed Relative to Interconnect Structure for Alignment of Semiconductor Die |
| US20170033062A1 (en) * | 2015-07-29 | 2017-02-02 | STATS ChipPAC Pte. Ltd. | Antenna In Embedded Wafer-Level Ball-Grid Array Package |
| CN107808878A (en) * | 2016-09-09 | 2018-03-16 | 力成科技股份有限公司 | Stack chip packaging structure |
-
2018
- 2018-07-26 CN CN201810836986.4A patent/CN108962773A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090236686A1 (en) * | 2006-04-19 | 2009-09-24 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming UBM Fixed Relative to Interconnect Structure for Alignment of Semiconductor Die |
| US20170033062A1 (en) * | 2015-07-29 | 2017-02-02 | STATS ChipPAC Pte. Ltd. | Antenna In Embedded Wafer-Level Ball-Grid Array Package |
| CN107808878A (en) * | 2016-09-09 | 2018-03-16 | 力成科技股份有限公司 | Stack chip packaging structure |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109786347A (en) * | 2018-12-20 | 2019-05-21 | 华进半导体封装先导技术研发中心有限公司 | The fan-out package structure and packaging method of chip |
| US11316438B2 (en) | 2019-01-07 | 2022-04-26 | Delta Eletronics (Shanghai) Co., Ltd. | Power supply module and manufacture method for same |
| US11901113B2 (en) | 2019-01-07 | 2024-02-13 | Delta Electronics (Shanghai) Co., Ltd. | Inversely coupled inductor and power supply module |
| US11676756B2 (en) | 2019-01-07 | 2023-06-13 | Delta Electronics (Shanghai) Co., Ltd. | Coupled inductor and power supply module |
| CN111415909A (en) * | 2019-01-07 | 2020-07-14 | 台达电子企业管理（上海）有限公司 | Multi-chip packaged power module |
| US11399438B2 (en) | 2019-01-07 | 2022-07-26 | Delta Electronics (Shanghai) Co., Ltd. | Power module, chip-embedded package module and manufacturing method of chip-embedded package module |
| US11227856B2 (en) | 2019-01-07 | 2022-01-18 | Delta Electronics (Shanghai) Co., Ltd. | Multi-chip package power module |
| CN110335852A (en) * | 2019-07-18 | 2019-10-15 | 上海先方半导体有限公司 | A kind of fan-out packaging structure and packaging method |
| CN110581079B (en) * | 2019-09-23 | 2021-09-03 | 合肥矽迈微电子科技有限公司 | Fan-out type chip packaging method and fan-out type chip packaging body |
| CN110581079A (en) * | 2019-09-23 | 2019-12-17 | 合肥矽迈微电子科技有限公司 | Fan-out type chip packaging method and fan-out type chip packaging body |
| CN111341796A (en) * | 2020-02-26 | 2020-06-26 | 南通智通达微电子物联网有限公司 | Fan-out type packaging method of image sensor |
| WO2022012498A1 (en) * | 2020-07-13 | 2022-01-20 | 矽磐微电子(重庆)有限公司 | Chip packaging structure and manufacturing method therefor |
| CN112582366A (en) * | 2020-12-11 | 2021-03-30 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging structure and preparation method thereof |
| WO2023087323A1 (en) * | 2021-11-22 | 2023-05-25 | 华为技术有限公司 | Photoelectric transceiver assembly and method for manufacturing same |
| WO2024086970A1 (en) * | 2022-10-24 | 2024-05-02 | 广东省科学院半导体研究所 | Fan-out type package structure and preparation method therefor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108962773A (en) | Fan-out package structure and its manufacturing method | |
| CN108022923B (en) | Semiconductor package | |
| US8592952B2 (en) | Semiconductor chip and semiconductor package with stack chip structure | |
| US9130024B2 (en) | Three-dimensional semiconductor device | |
| US10847304B2 (en) | InFO coil on metal plate with slot | |
| US10074628B2 (en) | System-in-package and fabrication method thereof | |
| CN102376595A (en) | Method and semiconductor device of forming FO-WLCSP having conductive layers and conductive vias | |
| KR20010088374A (en) | Semiconductor device | |
| KR20180124256A (en) | Stacked semiconductor package having mold via and method for manufacturing the same | |
| US9196601B2 (en) | Semiconductor device | |
| TWI622153B (en) | System-in-package and method for fabricating the same | |
| CN109585431A (en) | A kind of fan-out packaging structure and its manufacturing method of Flash chip stacking | |
| EP3547364B1 (en) | Semiconductor chip and semiconductor package including the same | |
| KR20170027391A (en) | Semiconductor package on which a plurality of chips is embedded and method of manufacturing the same | |
| US20230099787A1 (en) | Semiconductor package and method of fabricating the same | |
| KR101142339B1 (en) | Semiconductor chip | |
| US9741680B1 (en) | Wire bond through-via structure and method | |
| CN101465341B (en) | Stacked chip packaging structure | |
| CN208433398U (en) | Two-sided fan-out package structure | |
| TW202145495A (en) | Semiconductor package including capacitor | |
| CN110211954A (en) | A kind of multichip packaging structure and its manufacturing method | |
| US20110006412A1 (en) | Semiconductor chip package and method for manufacturing thereof and stack package using the same | |
| CN104392979A (en) | Chip stacking encapsulation structure | |
| CN103928416B (en) | There is semiconductor package part and the stacking method thereof of passive device | |
| CN114695323A (en) | Semiconductor device package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20181207 |