CN110581079A - Fan-out type chip packaging method and fan-out type chip packaging body - Google Patents
Fan-out type chip packaging method and fan-out type chip packaging body Download PDFInfo
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- CN110581079A CN110581079A CN201910897022.5A CN201910897022A CN110581079A CN 110581079 A CN110581079 A CN 110581079A CN 201910897022 A CN201910897022 A CN 201910897022A CN 110581079 A CN110581079 A CN 110581079A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
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- H01L2224/73265—Layer and wire connectors
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
Abstract
The invention provides a fan-out chip packaging method and a fan-out chip packaging body, wherein the thickness of a chip can be reduced to be less than or equal to 50um by utilizing the processes of multiple packaging, slotting, conductive metal layer deposition, pin electroplating, graphical connection and the like, so that the body resistance of the chip is greatly reduced, and the performance of components is improved; the back silver layer is manufactured by silver adhesive without adopting a back silver process, and the substrate is not bonded by conductive adhesive, so that two main materials of the substrate and the silver adhesive are saved, and the manufacturing cost of the chip is effectively saved.
Description
Technical Field
the invention relates to the field of semiconductor packaging, in particular to a high-performance power semiconductor fan-out type chip packaging method and a fan-out type chip packaging body prepared by the packaging method.
background
with the development of electronic products, semiconductor technology has been widely used to manufacture memory, Central Processing Unit (CPU), Liquid Crystal Display (LCD), Light Emitting Diode (LED), laser diode, and other devices or chip sets. Since electronic components such as semiconductor components, micro-electro-mechanical systems (MEMS) or optoelectronic components have minute and fine circuits and structures, in order to prevent dust, acid-base substances, moisture, oxygen, etc. from contaminating or eroding the electronic components, thereby affecting the reliability and lifetime thereof, the related functions of Power Distribution, Signal Distribution, Heat Dissipation, protection and Support, etc. need to be provided for the electronic components by packaging technology.
referring to fig. 1A to 1F, a process flow chart of a conventional chip packaging method is shown. The method specifically comprises the following steps:
(1) providing a wafer; a wafer 10 is provided having a plurality of metal pads 111 on the front surface of the chips 11, wherein the wafer 10 has an initial thickness of 750um, as shown in fig. 1A.
(2) Thinning the back of the wafer; the wafer 10 is typically thinned to around 100um as shown in fig. 1B. The thinned wafer 10 is very easy to break during transportation and subsequent processes due to its small thickness.
(3) forming a metal layer on the back of the wafer; the metal layer 13 may be formed on the back surface of the wafer 10 by sputtering or vapor deposition, as shown in fig. 1C. Because the thinned wafer 10 is small in thickness, after the metal layer 13 is attached, the stress is increased, so that the wafer 10 is warped, the transportation difficulty is improved, and the risk of fragment is increased.
(4) Cutting the wafer to form a single chip; two chips 11 are cut and formed as illustrated in fig. 1D.
(5) Bonding a single chip on a substrate with a patterned circuit through a conductive adhesive; specifically, a back silver layer 15 for conducting electricity is formed on the lower surface of the metal layer 13 of the single chip 11 formed by cutting; a patterned circuit 101 formed on the substrate 100 by electroplating, and a conductive adhesive 102 is applied to a portion of the patterned circuit 101 where a chip is to be attached; the side of the chip 11 having the silver-backed layer 15 is pressed against the conductive adhesive 102, so that the chip 11 is bonded to the substrate 100 through the conductive adhesive 102, as shown in fig. 1E.
(6) connecting the chip and the graphical circuit on the substrate, and carrying out plastic package to obtain a chip package body; specifically, the chip 11 is connected to the patterned circuit 101 on the substrate 100 through the bonding wire 16 to implement the circuit function of the chip 11; then, the chip 11 is encapsulated by a plastic encapsulating material such as ceramic or polyester to form a plastic encapsulating layer 103, and the plastic encapsulating layer 103 encapsulates the bonding wires 16, the chip 11 and the patterned circuit 101, as shown in fig. 1F.
Therefore, the back silver layer for conducting electricity needs to be arranged on the back surface of the chip of the existing chip packaging body, so that the manufacturing cost of the chip is increased; in the preparation process of the chip packaging body, the thinned wafer is very easy to break in transportation and subsequent processes, and after a metal layer is formed on the back of the thinned wafer, the stress is increased to enable the wafer to warp, so that the transportation difficulty is improved, and the risk of breaking is increased.
Therefore, a new chip packaging process is needed to overcome the above-mentioned disadvantages of the conventional chip packaging process.
disclosure of Invention
The invention aims to provide a fan-out chip packaging method and a fan-out chip packaging body, which can ensure good transportability, avoid the risk of fragment, greatly reduce the thickness of a chip, improve the performance of a component and save the manufacturing cost of the chip.
In order to achieve the above object, the present invention provides a fan-out chip packaging method, which comprises the following steps: (1) providing a product to be packaged, wherein the product to be packaged comprises a carrier, at least one chip is attached to the carrier, and a plurality of metal bonding pads are arranged on the front surface of the chip; (2) forming a first plastic packaging layer to cover the chip, and then removing the carrier, wherein the first plastic packaging layer extends outwards from at least one side surface of the chip to form a region to be grooved; (3) thinning the chip and the first plastic packaging layer from one side of the back surface of the chip, and grooving the region to be grooved of the first plastic packaging layer to form a groove; (4) depositing a conductive metal layer in the groove, electroplating the back of the chip to form a first pin, and electroplating the back of the conductive metal layer to form a second pin; (5) and processing the first plastic packaging layer from one side of the front surface of the chip to expose and connect the top surface of the metal pad and the front surface of the conductive metal layer, and performing plastic packaging to obtain a fan-out chip packaging product.
In order to achieve the above object, the present invention also provides a fan-out chip package, comprising: the front surface of the chip is provided with a plurality of metal bonding pads, and the back surface of the chip is provided with at least one first pin; the back of the conductive metal layer is provided with a second pin; the first plastic packaging layer covers the chip and the conductive metal layer and exposes the metal bonding pad, the first pin, the front surface of the conductive metal layer and the second pin; the graphical connecting line is connected between the front surface of the conductive metal layer and the corresponding metal bonding pad; the second plastic package layer wraps the first plastic package layer, the first pins and the second pins from the back of the chip; and the third plastic packaging layer wraps the first plastic packaging layer and the graphical connecting line from the front surface of the chip.
the invention has the advantages that: according to the fan-out chip packaging method, in the preparation process, the initial thickness of the chip is 200-250 micrometers, so that the risk of fragment in transportation and subsequent processes is avoided, and good transportability is ensured; the chip is firstly subjected to primary plastic packaging before being thinned, and the chip can be thinned to the utmost extent due to the good supporting property of the plastic packaging material on the chip. The thickness of the prepared fan-out chip packaging body can be reduced to be less than or equal to 50um, so that the body resistance of the chip is greatly reduced, and the performance of components is improved; the back silver layer is manufactured by silver adhesive without adopting a back silver process, and the substrate is not bonded by conductive adhesive, so that two main materials of the substrate and the silver adhesive are saved, and the manufacturing cost of the chip is effectively saved.
drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1A to 1F are process flow diagrams of a conventional chip packaging method;
FIG. 2 is a schematic diagram illustrating steps of a fan-out chip packaging method according to the present invention;
FIGS. 3A-3H are process flow diagrams of one embodiment of a fan-out chip packaging method of the present invention;
FIGS. 4A-4E are process flow diagrams of one embodiment of the present invention for preparing a product to be packaged;
fig. 5 is a perspective view of an embodiment of a fan-out chip packaging method of the invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar components or components having the same or similar functions throughout. The directional phrases used in this disclosure include, for example: up, down, left, right, front, rear, inner, outer, lateral, etc., are simply directions with reference to the drawings. The embodiments described below by referring to the drawings and directional terms used are exemplary only, are used for explaining the present invention, and are not construed as limiting the present invention. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.
referring to fig. 2, a step diagram of a fan-out chip packaging method according to the present invention is shown. The method comprises the following steps: s21: providing a product to be packaged, wherein the product to be packaged comprises a carrier, at least one chip is attached to the carrier, and a plurality of metal bonding pads are arranged on the front surface of the chip; s22: forming a first plastic packaging layer to cover the chip, and then removing the carrier, wherein the first plastic packaging layer extends outwards from at least one side surface of the chip to form a region to be grooved; s23: thinning the chip and the first plastic packaging layer from one side of the back surface of the chip, and grooving the region to be grooved of the first plastic packaging layer to form a groove; s24: depositing a conductive metal layer in the groove, electroplating the back of the chip to form a first pin, and electroplating the back of the conductive metal layer to form a second pin; and S25: and processing the first plastic packaging layer from one side of the front surface of the chip to expose and connect the top surface of the metal pad and the front surface of the conductive metal layer, and performing plastic packaging to obtain a fan-out chip packaging product. Step S25 may be followed by further comprising: s26: and exposing the surfaces of the first pin and the second pin, performing surface anti-oxidation treatment, and then cutting to form a single fan-out chip package. The above steps are described in detail below with reference to the accompanying drawings and embodiments.
Please refer to fig. 2 and fig. 3A to fig. 3H together, wherein fig. 3A to fig. 3H are process flow diagrams of an embodiment of a fan-out chip packaging method according to the present invention.
regarding step S21: a product to be packaged is provided, where the product to be packaged includes a carrier, at least one chip is attached to the carrier, and a plurality of metal pads are disposed on a front surface of the chip, please refer to fig. 2 and fig. 3A together, where fig. 3A is a front view of the product to be packaged according to this embodiment. In this embodiment, the product to be packaged includes a carrier 31, at least one chip 32 is attached to the carrier 31, a plurality of metal pads 321 are disposed on a front surface of the chip 32, and all the chips 32 are disposed on the carrier 31 in a normal mounting manner. In this embodiment, for clarity of illustrating the technical solution of the present invention, two metal pads 321 are illustrated on the front surface of the chip 32, in other embodiments, one or more metal pads 321 may be disposed on the front surface of the chip 32, and the number and shape of the metal pads on the chip are not limited in the present invention.
In a further embodiment, the carrier 31 is a film layer or tape having adhesive properties. The chip is attached to the film layer or the adhesive tape which has viscosity and high temperature resistance, the back surface of the chip does not need to adopt a back silver process to manufacture a back silver layer by using silver adhesive, and the substrate does not need to be bonded by conductive adhesive, so that two main materials of the substrate and the silver adhesive are saved, and the manufacturing cost of the chip is effectively saved.
In a further embodiment, the initial thickness of the chip 32 in the product to be packaged is 200-250 um, and the initial thickness of the chip 32 is not too thin, so that the risk of fragment in transportation and subsequent processes is avoided, and good transportability is ensured.
regarding step S22: fig. 2 and fig. 3B to 3C are also referred to, in which fig. 3B is a cross-sectional view of the product to be packaged that is provided in this embodiment after being packaged, and fig. 3C is a cross-sectional view of the product to be packaged that is provided in this embodiment after the carrier is removed from the product to be packaged. The first plastic package layer 33 is used for plastic packaging the chip 32, and the radius of the first plastic package layer 33 is larger than that of the chip 32, so that the first plastic package layer 33 extends outwards from at least one side surface of the chip 32 to form a region 331 to be grooved. The number and position of the regions to be grooved can be set according to the circuit arrangement requirement of the chip, which is not limited by the invention.
In a further embodiment, a plastic package material such as ceramic or polyester may be used to form the first plastic package layer 33 by plastic package of the chip 32 on the product to be packaged.
regarding step S22: fig. 2 and fig. 3B to fig. 3C are also referred to, where fig. 3B is a cross-sectional view of the product to be packaged that is provided in this embodiment after being packaged, and fig. 3C is a cross-sectional view of the product to be packaged that is provided in this embodiment after the carrier is removed from the product to be packaged.
as shown in fig. 3B, the first molding compound 33 molds the chip 32, and a radius of the first molding compound 33 is larger than a radius of the chip 32, so that the first molding compound 33 extends out of a to-be-grooved area 331 on at least one side of the chip 32. The number and position of the regions to be grooved can be set according to the circuit arrangement requirement of the chip, which is not limited by the invention.
In a further embodiment, a plastic package material such as ceramic or polyester may be used to form the first plastic package layer 33 by plastic package of the chip 32 on the product to be packaged.
As shown in fig. 3C, after the carrier 31 is removed from the encapsulated product, the back surface of the chip 32 is exposed to the first molding layer 33, which facilitates the subsequent thinning process.
regarding step S23: the chip and the first plastic package layer are thinned from one side of the back surface of the chip, and the region to be grooved of the first plastic package layer is grooved to form a groove, please refer to fig. 2 and fig. 3D together, where fig. 3D is a cross-sectional view of the encapsulated product to be packaged after being thinned and grooved, provided by this embodiment.
In a further embodiment, the chip 32 and the first molding layer 33 may be ground and thinned from the back side of the chip 32, and the molding material of the first molding layer 33 may support the chip 32 well, so that the chip 32 may be thinned to a great extent.
in a further embodiment, the thickness of the chip 32 after thinning is less than or equal to 50um, so that the bulk resistance of the chip 32 is greatly reduced, and the performance of the component is improved.
In a further embodiment, the first molding layer 33 may be grooved in the region 331 to be grooved by a laser method or a mechanical method, so as to form a groove 332. The groove is deep to the top surface of the metal pad 321.
Regarding step S24: referring to fig. 2 and fig. 3E together, a conductive metal layer is deposited in the groove, and a first lead is formed on the back surface of the chip by electroplating, and a second lead is formed on the back surface of the conductive metal layer by electroplating, where fig. 3E is a cross-sectional view of the structure shown in fig. 3D after the conductive metal layer deposition and the lead electroplating are performed.
In a further embodiment, a metal layer deposition process such as sputter deposition or chemical deposition may be used to deposit the conductive metal layer 34 in the groove 332 and fill the groove 332. Thereafter, a first lead 322 is formed on the back side of the chip 32 by electroplating, and a second lead 341 is formed on the back side of the conductive metal layer 34 by electroplating. The pin plating material and the conductive metal layer may be the same metal material.
Regarding step S25: processing the first plastic package layer from one side of the front surface of the chip to expose and connect the top surface of the metal pad and the front surface of the conductive metal layer, and performing plastic package to obtain a fan-out chip package product, please refer to fig. 2 and fig. 3F to 3H together, where fig. 3F is a cross-sectional view of the structure shown in fig. 3E after the package is performed, fig. 3G is a cross-sectional view of the structure shown in fig. 3F after the grinding is performed, and fig. 3H is a cross-sectional view of the fan-out chip package product provided in this embodiment.
In a further embodiment, step S25 can be implemented by the following steps:
1) Forming a second plastic packaging layer to cover the first plastic packaging layer, the first pins and the second pins; as shown in fig. 3F. The structure shown in fig. 3E may be plastic-encapsulated by using a plastic-encapsulating material such as ceramic or polyester to form the second plastic-encapsulating layer 35. The material of the second molding layer 35 may be the same as or different from the material of the first molding layer 33. The second molding compound layer 35 covers the first molding compound layer 33, the first pins 322, and the second pins 341, and due to the good support property of the molding compound of the second molding compound layer 35, the subsequent grinding treatment is facilitated, and the surface oxidation of the first pins 322 and the second pins 341 can be avoided.
2) Grinding the first plastic packaging layer from one side of the front surface of the chip to expose the top surface of the metal pad and the front surface of the conductive metal layer; as shown in fig. 3G. For example, a surface mechanical polishing process may be used to expose the top surface of the metal pad 321 and the front surface of the conductive metal layer 34, so as to facilitate subsequent circuit arrangement.
3) performing circuit arrangement, connecting the top surface of the metal pad with the front surface of the conductive metal layer through a graphical connecting wire, and forming a third plastic package layer to coat the first plastic package layer, the second plastic package layer and the graphical connecting wire, thereby forming a fan-out chip package product; as shown in fig. 3H. Specifically, the top surface of the metal pad 321 and the front surface of the conductive metal layer 34 are connected by a patterned connection line 36, so as to implement the circuit function of the chip 32; and then, plastic packaging is carried out on the circuit arrangement structure by adopting plastic packaging materials such as ceramics or polyester and the like to form a third plastic packaging layer 37, and the third plastic packaging layer 37 is used for plastic packaging the first plastic packaging layer 33, the second plastic packaging layer 35 and the graphical connecting line 36, so that a fan-out chip packaging product is formed.
Therefore, the packaging process of the product to be packaged by the fan-out type chip packaging method is completed.
Please refer to fig. 4A to 4E for the product to be packaged provided in step S21, wherein fig. 4A to 4E are process flow diagrams for preparing an embodiment of the product to be packaged according to the present invention. Specifically, the method comprises the following steps:
1) providing a wafer, wherein a plurality of metal bonding pads are arranged on the front surface of a chip contained in the wafer; as shown in fig. 4A. A wafer 40 is provided having a plurality of metal pads 321 on the front surface of the chips 32, wherein the wafer 40 has an initial thickness of typically 750 um.
2) Carrying out pre-thinning treatment on the wafer from one side far away from the metal bonding pad; as shown in fig. 4B. It is right wafer 40 thins to certain thickness in advance, can generally thin to 200 ~ 250um according to different chips. The thickness of the wafer 40 after the pre-thinning treatment is 200-250 um, that is, the initial thickness of the chip 32 formed after the subsequent cutting is 200-250 um, and the initial thickness of the chip 32 is not too thin, so that the risk of fragment in the transportation and the subsequent process is avoided, and the good transportability is ensured.
Preferably, after the pre-thinning treatment, metal balls are implanted on the top surfaces of the metal pads of the chip; as shown in fig. 4C. The metal balls 41 are implanted on the top surface of the metal bonding pad 321 of the chip 32, so that the metal bonding pad can be prevented from being oxidized, the height of the metal bonding pad is increased, and the connection of a subsequent graphical connecting line is facilitated.
3) Cutting the wafer to form a single chip; as shown in fig. 4D. The initial thickness of the single chip 32 formed by cutting is 200-250 um, so that the risk of fragment in transportation and subsequent processes is avoided, and good transportability is ensured.
4) Attaching the back surface of the chip to the carrier to form the product to be packaged; as shown in fig. 4E. The carrier 31 is a film layer or an adhesive tape having adhesiveness. The chip is attached to the film layer or the adhesive tape which has viscosity and high temperature resistance, the back surface of the chip does not need to adopt a back silver process to manufacture a back silver layer by using silver adhesive, and the substrate does not need to be bonded by conductive adhesive, so that two main materials of the substrate and the silver adhesive are saved, and the manufacturing cost of the chip is effectively saved.
Preferably, step S25 may be followed by further comprising: s26: exposing the surfaces of the first and second leads, performing surface anti-oxidation treatment, and then cutting to form a single fan-out chip package, please refer to fig. 2 and 5, wherein fig. 5 is a cross-sectional view of the fan-out chip package provided by the present invention.
In a further embodiment, the chip package product may be ground from the back side of the chip 32 to expose the first and second leads; specifically, the second molding compound layer 35 of the chip package product is subjected to surface mechanical grinding treatment to expose the first pins 322 and the second pins 341; then, performing surface oxidation prevention treatment on the first pin 322 and the second pin 341, for example, melting tin, implanting a solder ball, melting nickel, melting gold, etc. to prevent the exposed surfaces of the first pin 322 and the second pin 341 from being oxidized; and then cutting the chip packaging product to form a single fan-out chip packaging body.
Referring to fig. 5, a cross-sectional view of an embodiment of a fan-out chip package is shown. The package body includes: a chip 32, the front surface of the chip 32 has a plurality of metal pads 321, and the back surface of the chip 32 has at least one first pin 322; a conductive metal layer 34, a second lead 341 is formed on the back surface of the conductive metal layer 34; a first molding compound layer 33 covering the chip 32 and the conductive metal layer 34 and exposing the metal pad 321, the first lead 322, the front surface of the conductive metal layer 34 and the second lead 341; a patterned connection line 36 connected between the front surface of the conductive metal layer 34 and the corresponding metal pad 321; a second molding compound layer 35, which covers the first molding compound layer 33, the first leads 322 and the second leads 341 from the back of the chip 32; a third molding compound layer 37, which covers the first molding compound layer 33 and the patterned connecting lines 36 from the front surface of the chip 32.
In a further embodiment, the thickness of the chip is less than or equal to 50 um. Thereby greatly reducing the bulk resistance of the chip and improving the performance of the component.
In a further embodiment, the top surface of the metal pad 321 of the chip 32 is implanted with a metal ball 41, and the patterned connection line 36 further connects the front surface of the conductive metal layer 34 and the metal ball 41 on the corresponding metal pad 321. The metal balls 41 can prevent the oxidation of the corresponding metal pads and increase the height of the metal pads, facilitating the connection of the patterned connection lines 36.
In a further embodiment, the surfaces of the first pin 322 and the second pin 341 are exposed to the second molding compound 35, and the exposed surfaces are respectively provided with an anti-oxidation metal layer. Specifically, the top surface of the first pin 322 is exposed to the second plastic package layer 35, and is provided with a first oxidation-resistant metal layer 51; the top surface of the second lead 341 is exposed to the second molding compound 35, and a second oxidation-resistant metal layer 52 is disposed thereon.
According to the fan-out chip packaging body, the initial thickness of the chip is 200-250 um, so that the risk of fragment in transportation and subsequent processes is avoided, and good transportability is ensured; the chip is firstly subjected to primary plastic packaging before being thinned, the chip can be thinned to the maximum extent due to the good supporting property of the plastic packaging material on the chip, the thickness of the chip can be thinned to be less than or equal to 50um, the body resistance of the chip is greatly reduced, and the performance of components is improved; the back silver layer is manufactured by silver adhesive without adopting a back silver process, and the substrate is not bonded by conductive adhesive, so that two main materials of the substrate and the silver adhesive are saved, and the manufacturing cost of the chip is effectively saved.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A fan-out chip packaging method is characterized by comprising the following steps:
(1) Providing a product to be packaged, wherein the product to be packaged comprises a carrier, at least one chip is attached to the carrier, and a plurality of metal bonding pads are arranged on the front surface of the chip;
(2) Forming a first plastic packaging layer to cover the chip, and then removing the carrier, wherein the first plastic packaging layer extends outwards from at least one side surface of the chip to form a region to be grooved;
(3) thinning the chip and the first plastic packaging layer from one side of the back surface of the chip, and grooving the region to be grooved of the first plastic packaging layer to form a groove;
(4) depositing a conductive metal layer in the groove, electroplating the back surface of the chip to form a first pin, and
Electroplating the back of the conductive metal layer to form a second pin;
(5) and processing the first plastic packaging layer from one side of the front surface of the chip to expose and connect the top surface of the metal pad and the front surface of the conductive metal layer, and performing plastic packaging to obtain a fan-out chip packaging product.
2. the method according to claim 1, characterized in that the product to be packaged is further prepared by the following steps:
(11) Providing a wafer, wherein a plurality of metal bonding pads are arranged on the front surface of a chip contained in the wafer;
(12) Carrying out pre-thinning treatment on the wafer from one side far away from the metal bonding pad;
(13) Cutting the wafer to form a single chip;
(14) And attaching the back surface of the chip to the carrier to form the product to be packaged.
3. The method of claim 2, wherein step (12) is further followed by: and implanting metal balls on the top surface of the metal bonding pad of the chip.
4. The method of claim 1, wherein the thickness of the chip after the thinning process in step (3) is less than or equal to 50 um.
5. The method of claim 1, wherein step (5) further comprises:
(51) Forming a second plastic packaging layer to cover the first plastic packaging layer, the first pins and the second pins;
(52) Grinding the first plastic packaging layer from one side of the front surface of the chip to expose the top surface of the metal pad and the front surface of the conductive metal layer;
(53) And carrying out circuit arrangement, connecting the top surface of the metal pad with the front surface of the conductive metal layer through a graphical connecting wire, and forming a third plastic packaging layer to coat the first plastic packaging layer, the second plastic packaging layer and the graphical connecting wire, thereby forming a fan-out chip packaging product.
6. The method of claim 1, wherein step (5) is further followed by:
(6) and exposing the surfaces of the first pin and the second pin, performing surface anti-oxidation treatment, and then cutting to form a single fan-out chip package.
7. A fan-out chip package, comprising:
The front surface of the chip is provided with a plurality of metal bonding pads, and the back surface of the chip is provided with at least one first pin;
The back of the conductive metal layer is provided with a second pin;
The first plastic packaging layer covers the chip and the conductive metal layer and exposes the metal bonding pad, the first pin, the front surface of the conductive metal layer and the second pin;
The graphical connecting line is connected between the front surface of the conductive metal layer and the corresponding metal bonding pad;
The second plastic package layer wraps the first plastic package layer, the first pins and the second pins from the back of the chip;
And the third plastic packaging layer wraps the first plastic packaging layer and the graphical connecting line from the front surface of the chip.
8. the fan-out chip package of claim 7, wherein the thickness of the chip is less than or equal to 50 um.
9. The fan-out die package of claim 7, wherein metal balls are implanted on top surfaces of the metal pads of the die, and the patterned connecting lines further connect the front surface of the conductive metal layer and the metal balls on the corresponding metal pads.
10. The fan-out chip package of claim 7, wherein surfaces of the first and second leads are exposed to the second molding compound, and the exposed surfaces are respectively provided with an oxidation-resistant metal layer.
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