CN110581079B - Fan-out type chip packaging method and fan-out type chip packaging body - Google Patents
Fan-out type chip packaging method and fan-out type chip packaging body Download PDFInfo
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- CN110581079B CN110581079B CN201910897022.5A CN201910897022A CN110581079B CN 110581079 B CN110581079 B CN 110581079B CN 201910897022 A CN201910897022 A CN 201910897022A CN 110581079 B CN110581079 B CN 110581079B
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims (9)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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CN201910897022.5A CN110581079B (en) | 2019-09-23 | 2019-09-23 | Fan-out type chip packaging method and fan-out type chip packaging body |
Applications Claiming Priority (1)
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CN201910897022.5A CN110581079B (en) | 2019-09-23 | 2019-09-23 | Fan-out type chip packaging method and fan-out type chip packaging body |
Publications (2)
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CN110581079A CN110581079A (en) | 2019-12-17 |
CN110581079B true CN110581079B (en) | 2021-09-03 |
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CN201910897022.5A Active CN110581079B (en) | 2019-09-23 | 2019-09-23 | Fan-out type chip packaging method and fan-out type chip packaging body |
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Families Citing this family (1)
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CN113327900A (en) * | 2021-06-18 | 2021-08-31 | 广东佛智芯微电子技术研究有限公司 | High-radiating-board-level fan-out packaging structure based on copper foil carrier and preparation method thereof |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106571343A (en) * | 2016-11-18 | 2017-04-19 | 三星半导体(中国)研究开发有限公司 | Wafer level fan-out type packaging member integrated with passive element and manufacturing method thereof |
CN108109985A (en) * | 2017-12-26 | 2018-06-01 | 合肥矽迈微电子科技有限公司 | Multichip stacking encapsulation method and packaging body |
CN108878297A (en) * | 2018-07-20 | 2018-11-23 | 合肥矽迈微电子科技有限公司 | Chip-packaging structure and preparation method thereof |
CN108962773A (en) * | 2018-07-26 | 2018-12-07 | 华进半导体封装先导技术研发中心有限公司 | Fan-out package structure and its manufacturing method |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20140038116A (en) * | 2012-09-20 | 2014-03-28 | 제이앤제이 패밀리 주식회사 | Led lamp |
US9425121B2 (en) * | 2013-09-11 | 2016-08-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated fan-out structure with guiding trenches in buffer layer |
-
2019
- 2019-09-23 CN CN201910897022.5A patent/CN110581079B/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106571343A (en) * | 2016-11-18 | 2017-04-19 | 三星半导体(中国)研究开发有限公司 | Wafer level fan-out type packaging member integrated with passive element and manufacturing method thereof |
CN108109985A (en) * | 2017-12-26 | 2018-06-01 | 合肥矽迈微电子科技有限公司 | Multichip stacking encapsulation method and packaging body |
CN108878297A (en) * | 2018-07-20 | 2018-11-23 | 合肥矽迈微电子科技有限公司 | Chip-packaging structure and preparation method thereof |
CN108962773A (en) * | 2018-07-26 | 2018-12-07 | 华进半导体封装先导技术研发中心有限公司 | Fan-out package structure and its manufacturing method |
Non-Patent Citations (1)
Title |
---|
扇出型晶圆级封装技术及其在移动设备中的应用;郭昌宏等;《电子工业专用设备》;20181020(第05期);正文 * |
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CN110581079A (en) | 2019-12-17 |
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EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20191217 Assignee: Anhui Xingtai Financial Leasing Co.,Ltd. Assignor: Hefei Silicon Microelectronics Technology Co.,Ltd. Contract record no.: X2022340000003 Denomination of invention: Fan out chip packaging method and fan out chip packaging body Granted publication date: 20210903 License type: Exclusive License Record date: 20220418 |
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PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Fan out chip packaging method and fan out chip packaging body Effective date of registration: 20220422 Granted publication date: 20210903 Pledgee: Anhui Xingtai Financial Leasing Co.,Ltd. Pledgor: Hefei Silicon Microelectronics Technology Co.,Ltd. Registration number: Y2022980004560 |
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PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20230727 Granted publication date: 20210903 Pledgee: Anhui Xingtai Financial Leasing Co.,Ltd. Pledgor: Hefei Silicon Microelectronics Technology Co.,Ltd. Registration number: Y2022980004560 |
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PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
EC01 | Cancellation of recordation of patent licensing contract |
Assignee: Anhui Xingtai Financial Leasing Co.,Ltd. Assignor: Hefei Silicon Microelectronics Technology Co.,Ltd. Contract record no.: X2022340000003 Date of cancellation: 20230810 |
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EC01 | Cancellation of recordation of patent licensing contract |