CN115346936A - 3D chip packaging structure and packaging method - Google Patents

Abstract

The application belongs to the technical field of chip packaging, and particularly relates to a 3D chip packaging structure and a packaging method. The packaging method aims to solve the technical problems that the existing packaging process is complex and the total packaging cost is high. The 3D chip packaging structure of this application includes the chip body, and the chip body includes: a first chip having a first surface; the second chip is arranged on the first surface of the first chip; the first insulating packaging layer is arranged on the first surface and wraps the surface of the second chip; and the first electric connection structure penetrates through the first insulating packaging layer and is electrically connected between the first chip and the second chip. The packaging method and the packaging device can improve the transmission speed of the first chip and the second chip, optimize the packaging size, simplify the packaging process of the first chip and the second chip, and reduce the complexity of the packaging process, thereby reducing the total packaging cost.

Description

3D chip packaging structure and packaging method

Technical Field

The application relates to the technical field of chip packaging, in particular to a 3D chip packaging structure and a packaging method.

Background

With the increasing requirements of high performance, high transmission rate, small size, high reliability and ultra-low power consumption in chips and electronic products, the development of advanced packaging technology is promoted to be continuously broken through. In order to increase the transmission rate of the chip and optimize the package size of the chip, the demand for three-dimensional (3D) packaging is becoming stronger.

In the related art, in the 3D chip package, a package slot is usually formed on a package silicon substrate, one chip to be packaged is disposed in the package slot, and then the package silicon substrate is stacked and packaged with another chip to be packaged by bonding or the like, and is electrically connected between the two chips through an electrical connection structure.

However, in the 3D chip package in the related art, the packaging process is complicated, and the total package cost is high.

Disclosure of Invention

The application provides a 3D chip packaging structure and a packaging method, which can improve the transmission speed of a chip, optimize the packaging size, simplify the packaging process and reduce the packaging cost.

In order to achieve the above purpose, the present application provides the following technical solutions:

a first aspect of the present application provides a 3D chip packaging structure, which includes: the chip body, the chip body includes:

a first chip having a first surface;

the second chip is arranged on the first surface of the first chip;

the first insulating packaging layer is arranged on the first surface and wraps the surface of the second chip; and

the first electrical connection structure penetrates through the first insulating packaging layer and is electrically connected between the first chip and the second chip.

Compared with the related art, the 3D chip packaging structure provided by the first aspect of the present application has the following advantages:

the embodiment of the application provides a 3D chip package structure includes first chip, second chip, first insulation packaging layer and first electric connection structure, and first chip has the first surface, and the second chip sets up in the first surface of first chip, and first insulation packaging layer sets up in the first surface to wrap up in the surface of second chip, first electric connection structure runs through first insulation packaging layer, and first electric connection structure electric connection is between first chip and second chip. In the above scheme, the second chip is arranged on the first surface of the first chip, and the first insulating packaging layer is formed on the first surface and wraps the surface of the second chip, so that the transmission speed of the chip can be increased, the packaging size can be optimized, the packaging process of the first chip and the second chip can be simplified, the complexity of the packaging process is reduced, and the total packaging cost is reduced.

As an improvement of the above structure of the present application, the projections of the second chip on the first chip are all located inside the edge of the first surface.

As an improvement of the above structure of the present application, the first insulating encapsulation layer extends to an edge of the first surface.

As an improvement of the above structure of the present application, an edge of the first insulating encapsulation layer is flush with an edge of the first surface.

As an improvement of the above structure of the present application, the first insulating encapsulation layer is an epoxy organic layer.

As an improvement of the above structure of the present application, the first chip and the second chip are both provided with pins, and the pins are connected to the first electrical connection structure.

As an improvement of the above structure of the present application, the pin includes a first pin disposed on the first chip, the first pin is disposed on the first surface, and a position of the first pin and a position of the second chip are not overlapped with each other.

As an improvement of the above structure of the present application, the pin further includes a second pin disposed on the second chip, and the second pin is located on a side surface of the second chip deviating from the first chip.

As a modification of the above structure of the present application, an adhesive layer is disposed between the first chip and the second chip, and the adhesive layer is configured to adhere the first chip and the second chip.

As an improvement of the above structure of the present application, the optical device further includes an optical lens, the first chip has a light sensing surface facing away from one side of the second chip, and the optical lens is bonded to the light sensing surface through an optical adhesive.

As an improvement of the above structure of the present application, the first electrical connection structure includes a first electrical contact portion penetrating through two opposite sides of the first insulating encapsulation layer and a second electrical contact portion penetrating through two opposite sides of the first chip, and the first electrical contact portion is in contact conduction with the second chip and the second electrical contact portion respectively.

As an improvement of the above structure of the present application, the chip further includes an insulating layer, where the insulating layer is disposed on a side surface of the first insulating encapsulation layer, which is away from the first chip.

As an improvement of the above structure of the present application, the chip further includes a second insulating encapsulation layer, and the second insulating encapsulation layer wraps at least part of the outer surface of the chip body.

As an improvement of the above structure of the present application, the second insulating encapsulation layer wraps around the outer surface of the first chip and the rest of the surface of the first insulating encapsulation layer where the insulating layer is not disposed.

As an improvement of the above structure of the present application, the number of the second chips is at least two, and at least two of the second chips are disposed on the first surface.

As a modification of the above structure of the present application, the number of the first chips is at least two.

As an improvement of the above structure of the present application, the structure further includes a second electrical connection structure, the second electrical connection structure penetrates through the insulating layer, and the second electrical connection structure is in contact with the first electrical connection structure.

As an improvement of the above structure of the present application, a pad is disposed on a surface of one side of the insulating layer away from the second chip, and the pad is in contact connection with the second electrical connection structure.

As an improvement of the above structure of the present application, an electrical contact bump protruding from the surface of the insulating layer is further disposed on the pad.

A second aspect of the present application provides a 3D chip packaging method, which is applied to the above-mentioned 3D chip packaging structure, and the method includes:

arranging a second chip on the first surface of the first chip;

arranging a first insulating packaging layer on the first surface, wherein the first insulating packaging layer wraps the surface of the second chip;

and forming a first electric connection structure on the first insulating packaging layer, wherein the first electric connection structure is electrically connected between the first chip and the second chip.

The 3D chip packaging method provided by the second aspect of the application comprises the following steps: arranging a second chip on the first surface of the first chip; arranging a first insulating packaging layer on the first surface, wherein the first insulating packaging layer wraps the surface of the second chip; and forming a first electric connection structure on the first insulating packaging layer, wherein the first electric connection structure is connected between the first chip and the second chip. In the method, the second chip is arranged on the first surface of the first chip, and then the first insulating packaging layer is formed on the first surface, so that the first insulating packaging layer wraps the surface of the second chip, the first electric connection structure is formed on the first insulating packaging layer, and the first electric connection structure is electrically connected between the first chip and the second chip, so that 3D packaging of the first chip and the second chip is realized, the transmission speed of the first chip and the second chip can be increased, the packaging size is optimized, the packaging process of the first chip and the second chip can be simplified, the complexity of the packaging process is reduced, and the total packaging cost is reduced.

As an improvement of the foregoing packaging method of the present application, the forming a first electrical connection structure on the first insulating packaging layer specifically includes:

etching an electrical connection hole on the first insulating packaging layer; one end of the electrical connection hole exposes a part of the first pin on the surface of the first chip, and the other end of the electrical connection hole exposes a part of the second pin on the surface of the second chip;

and forming an electric connector in the electric connecting hole to form the first electric connecting structure, wherein the first electric connecting structure is electrically connected between the first pin of the first chip and the second pin of the second chip.

As an improvement of the above-mentioned packaging method of the present application, the disposing the second chip in front of the first surface of the first chip further includes:

and forming a first pin on the first surface of the first chip, and forming a second pin on the surface of the second chip, which is far away from the first surface.

As an improvement of the above packaging method of the present application, after the first insulating packaging layer forms the first electrical connection structure, the method further includes:

and grinding one side of the first chip, which is far away from the first surface, so that the first chip has a preset thickness.

As an improvement of the above-mentioned packaging method of the present application, after the grinding of the side of the first chip facing away from the first surface, the method further includes:

and forming a back adhesive film on one side of the first chip, which is far away from the first surface.

As an improvement of the above-mentioned packaging method of the present application, the disposing the second chip in front of the first surface of the first chip further includes:

grinding a second wafer containing a plurality of second chips to a preset thickness;

and cutting and separating the second raw material wafer ground to the preset thickness to form a plurality of single second chips.

In addition to the technical problems solved by the present application, the technical features constituting the technical solutions, and the advantages brought by the technical features of the technical solutions described above, other technical problems that can be solved by the 3D chip packaging structure and the packaging method provided by the present application, other technical features included in the technical solutions, and advantages brought by the technical features will be further described in detail in the detailed description.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed to be used in the embodiments of the present application or the technical solutions in the prior art are briefly described below, it is obvious that the drawings in the following description are only a part of the embodiments of the present application, and that these drawings and the written description are not intended to limit the scope of the concepts of the present application in any way, but rather to illustrate the concepts of the present application for a person skilled in the art by referring to a specific embodiment, and that other drawings can be obtained from these drawings without inventive efforts for a person skilled in the art.

Fig. 1 is a schematic cross-sectional view of a 3D chip package structure in the related art;

fig. 2 is a schematic cross-sectional view illustrating a structure of a 3D chip package structure according to an embodiment of the present disclosure;

fig. 3 is a schematic cross-sectional view illustrating another structure of a 3D chip package structure according to an embodiment of the disclosure;

fig. 4 is a schematic cross-sectional view illustrating another structure of a 3D chip package structure according to an embodiment of the present disclosure;

fig. 5 is a schematic cross-sectional view illustrating another structure of a 3D chip package structure according to an embodiment of the present disclosure;

fig. 6 is a schematic cross-sectional view illustrating another structure of a 3D chip package structure according to an embodiment of the present disclosure;

fig. 7 is a schematic cross-sectional view illustrating another structure of a 3D chip package structure according to an embodiment of the disclosure;

fig. 8 is a schematic cross-sectional view illustrating another structure of a 3D chip package structure according to an embodiment of the present disclosure;

fig. 9 is a schematic cross-sectional view illustrating another structure of a 3D chip package structure according to an embodiment of the present disclosure;

fig. 10 is a schematic cross-sectional view illustrating another structure of a 3D chip package structure according to an embodiment of the present disclosure;

fig. 11 is a schematic cross-sectional view illustrating another structure of a 3D chip package structure according to an embodiment of the disclosure;

fig. 12 is a schematic cross-sectional view illustrating another structure of a 3D chip package structure according to an embodiment of the disclosure;

fig. 13 is a schematic cross-sectional view illustrating another structure of a 3D chip package structure according to an embodiment of the disclosure;

fig. 14 is a schematic cross-sectional view illustrating another structure of a 3D chip package structure according to an embodiment of the disclosure;

FIG. 15 is a flowchart illustrating a 3D chip packaging method of FIG. 2;

fig. 16 to 22 are schematic cross-sectional views illustrating the packaging process of fig. 2.

Description of reference numerals:

100: a 3D chip packaging structure; 110: a first chip; 11: a first incoming wafer;

120: a second chip; 12: a second incoming wafer; 121: an adhesive layer;

130: a first insulating encapsulation layer; 131: an electrical connection hole; 140: a first electrical connection structure;

141: a first pin; 142: a second pin; 143: a first electrical contact;

144: a second electrical contact; 151: an optical lens; 152: optical cement;

160: an insulating layer; 170: a second insulating encapsulation layer; 180: a second electrical connection structure;

181: a pad; 182: electrically contacting the bumps; 190: carrying out a glue film;

200-an organic layer; 210: a conductive layer; 300: a silicon substrate.

Detailed Description

In the related art, the main reasons that the 3D chip packaging process is complex and the total packaging cost is high are as follows: as an example of the 3D package structure 100 in fig. 1, the packaging process includes: step 1: providing a silicon substrate 300, and forming a package groove on the silicon substrate 300; step 2: disposing the second chip 120 ground to a predetermined thickness in the package groove; and 3, step 3: forming a first electrical connection structure 140 penetrating through the silicon substrate 300 on the silicon substrate 300, disposing the silicon substrate 300 provided with the second chip 120 on the surface of the first chip 110 on the first incoming wafer, and bonding or adhering the silicon substrate with the first chip 110, wherein the first electrical connection structure 140 is electrically connected between the first chip 110 and the second chip 120; finally, the first chip 110 is ground to a predetermined thickness, a back adhesive film is adhered to a side of the first chip 110 away from the second chip 120, and the first chip is cut into single chips, so as to form the 3D package structure shown in fig. 1.

However, when the first chip and the second chip are packaged, a package groove with a predetermined depth needs to be formed on the silicon substrate 300, but the depth of the package groove is difficult to control during formation, and in order to ensure the dimensional accuracy of the package groove, the packaging process is complicated, and the total packaging cost is high.

In view of this, research and development personnel provide a 3D chip packaging structure and a packaging process, which can simplify the packaging process and reduce the packaging cost while improving the transmission speed of the chip and optimizing the packaging size. Research and development personnel do not process the packaging groove on the silicon substrate by changing the packaging process, but arrange the second chip on the first surface of the first chip, and then form the first insulation packaging layer on the first surface, so that the first insulation packaging layer wraps up on the surface of the second chip, and then form the first electric connection structure penetrating through the first insulation layer on the first insulation packaging layer, so that the first electric connection structure is electrically connected between the first chip and the second chip, thereby realizing the 3D packaging of the first chip and the second chip, and thus avoiding preparing the packaging groove on the silicon substrate, simplifying the packaging process and further reducing the total packaging cost.

Reference will now be made in detail to the embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application.

Example one

Fig. 2 is a schematic cross-sectional view of a 3D chip package structure according to an embodiment of the present disclosure.

With reference to fig. 2, an embodiment of the present application provides a 3D chip package structure 100, which includes a chip body, the chip body includes a first chip 110, a second chip 120, a first insulating package layer 130 and a first electrical connection structure 140, the first chip 110 has a first surface, the second chip 120 is disposed on the first surface of the first chip 110, the first insulating package layer 130 is disposed on the first surface and wraps the surface of the second chip 120, the first electrical connection structure 140 penetrates the first insulating package layer 130, and the first electrical connection structure 140 is electrically connected between the first chip 110 and the second chip 120.

It is understood that the first surface of the first chip 110 refers to a surface of a side of the first chip 110 facing the second chip 120.

In the above scheme, the second chip 120 is disposed on the first chip 110, the first insulating package layer 130 is formed on the first surface and wraps the surface of the second chip 120, so as to package the first chip 110 and the second chip 120, and the first electrical connection structure 140 penetrates through the first insulating package layer 130, so that the first electrical connection structure 140 is electrically connected between the first chip 110 and the second chip 120, and by stacking the first chip 110 and the second chip 120, the distance of a transmission line between the first chip 110 and the second chip 120 can be shortened, so that the transmission speed of the chips can be increased, and the package size can be optimized; in addition, the packaging process of the first chip 110 and the second chip 120 can be simplified, and the complexity of the packaging process can be reduced, thereby reducing the overall packaging cost.

In a possible implementation manner, the number of the first electrical connection structures 140 is multiple, and after the first chip 110 and the second chip 120 are electrically connected through the first electrical connection structures 140 (as shown in fig. 2), the first electrical connection structures 140 are electrically led out to contact pads outside the chip body; alternatively, the first chip 110 may be separately led out to a contact point outside the chip body through one first electrical connection structure 140, and the second chip 120 may be separately led out to a contact point outside the chip body through another first electrical connection structure 140, so that the first chip 110 and the second chip 120 are electrically connected outside the chip body.

In some embodiments, the first insulating encapsulation layer 130 may be an epoxy organic layer made of an epoxy organic material; for example, the epoxy organic layer can be made of epoxy resin, and since the epoxy resin has good physical and mechanical properties, electrical insulation properties and adhesion properties, the epoxy resin has better economical efficiency compared with a silicon substrate made of silicon material, so that the total packaging cost can be reduced while the packaging performance is ensured.

Of course, the epoxy organic layer may also be other epoxy organic materials, and the embodiment of the present application is not particularly limited thereto.

In some embodiments, the projections of the second chip 120 on the first chip 110 are all located inside the edge of the first surface, i.e. the cross-sectional dimension of the second chip 120 parallel to the first surface is smaller than the cross-sectional dimension of the first chip 110, so that the overall dimension of the 3D chip structure can be further optimized.

In some embodiments, the first insulating encapsulation layer 130 extends to an edge of the first surface. That is, after the second chip 120 is disposed on the first chip 110, the first insulating encapsulation layer 130 is located on the first surface and wraps the surface of the second chip 120, and the first insulating encapsulation layer 130 extends to the edge of the first chip 110, that is, the area of the first insulating encapsulation layer 130 on the first surface is smaller than or equal to the first surface, so that the overall size of the packaged 3D chip packaging structure 100 can be reduced to optimize the size of the 3D chip packaging structure 100.

In some embodiments, an edge of the first insulating encapsulation layer 130 is flush with an edge of the first surface, so that the overall reliability of the 3D chip packaging structure 100 can be improved while the overall size of the packaged 3D chip packaging structure 100 is reduced.

It can be understood that, when the projection of the second chip 120 on the first chip 110 is located inside the edge of the first surface, by disposing the first insulating packaging layer 130 on the first surface, and the first insulating packaging layer 130 wraps the surface of the second chip, in this way, a sufficient space can be provided for subsequent metal rewiring of circuits, signal lines, and the like between the first chip 110 and the second chip 120, and of course, the surface of the second chip 120 can also be protected, so as to improve the operational reliability of the second chip 120.

In other embodiments, the projection of at least one side of the second chip 120 on the first chip 110 may also be located outside the edge of the first surface, and it is understood that at least one side of the second chip 120 is in a suspended state with respect to the first chip 110, at this time, in order to improve the support stability of the second chip 120, the first insulating encapsulation layer 130 disposed on the first surface of the first chip 110 wraps the second chip 120 to support and protect the second chip 120, so as to improve the working reliability of the second chip 120; in addition, a sufficient space can be provided for metal redistribution between the first chip 110 and the second chip 120.

In some embodiments, the first chip 110 and the second chip 120 are both provided with pins, and the pins are connected to the first electrical connection structures 140, that is, the first electrical connection structures 140 are wired on the first insulating package layer 130 according to actual requirements to lead out the pins on the first chip 110 and the second chip 120, so that the first electrical connection structures 140 are electrically connected to the first chip 110 and the second chip 120 through the pins, respectively, so as to improve the connection reliability between the first electrical connection structures 140 and the first chip 110 and the second chip 120.

Illustratively, the leads include first leads 141 disposed on the first chip 110, the first leads 141 are disposed on the first surface, and the positions of the first leads 141 and the second chip 120 are not overlapped with each other, so that the first electrical connection structure 140 is electrically connected to the first chip 110 through the first leads 141.

The leads may further include second leads 142 disposed on the second chip 120, and the second leads 142 are disposed on a side surface of the second chip 120 away from the first chip 110, so that the first electrical connection structure 140 is electrically connected to the second chip 120 through the second leads 142.

In fig. 2, a first surface of the first chip 110 is provided with a first pin 141, a side surface of the second chip 120 away from the first chip 110 is provided with a second pin 142, and the first electrical connection structure 140 is electrically connected between the first pin 141 and the second pin 142, so that the first chip 110 and the second chip 120 are electrically connected.

In some embodiments, the first lead 141 and the second lead 142 may be Ni/Au-plated to improve electrical connection reliability.

In some embodiments, after the second chip 120 is disposed on the first surface of the first chip 110, the second chip 120 may be connected to the first chip 110 by adhesion.

As in fig. 2, an adhesive layer 121 is disposed between the second chip 120 and the first surface of the first chip 110, so that the second chip 120 is adhered to the first surface of the first chip 110 by the adhesive layer 121; the adhesive layer 121 may be made of a material having adhesiveness, as long as the adhesion between the first chip 110 and the second chip 120 can be achieved, and is not limited in particular.

In some embodiments, there may be at least two second chips 120, and each second chip 120 is disposed on the first surface. Illustratively, as in fig. 3, the second chips 120 are two, two second chips 120 are disposed on the first surface of the first chip 110, and the two second chips 120 may be respectively adhered to the first surface by adhesive layers 121. The adhesive layers 121 corresponding to the second chips 120 may be independent, or may be a common adhesive layer 121, which is not limited in this application; in addition, the two second chips 120 may be the same or different. Preferably, a gap is provided between the second chips 120.

In the above solution, by disposing at least two second chips 120 on the first surface, the integration level of the chips can be improved.

In some embodiments, as shown in fig. 2, 3 and 11, the first electrical connection structure 140 may be a conductive lead penetrating the first insulating encapsulation layer 130, such that one end of the first electrical connection structure 140 is connected to the first chip 110 and the other end of the first electrical connection structure 140 is connected to the second chip 120, to achieve electrical conduction between the first chip 110 and the second chip 120.

The first electrical connection structure 140 may be formed by a metal plating process such as sputtering, electroplating, or evaporation, and the first electrical connection structure 140 may be made of molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium, silver, nickel, or a composite or alloy thereof.

In some embodiments, the 3D chip packaging structure 100 further includes an insulating layer 160, and the insulating layer 160 is disposed on a surface of the first insulating packaging layer 130 on a side facing away from the first chip 110.

Referring to fig. 2 to 5, the 3D chip package structure 100 further includes a second electrical connection structure 180, the second electrical connection structure 180 may be a Redistribution Layer (RDL) in the insulating Layer 160, and the second electrical connection structure 180 is in contact with the first electrical connection structure 140, so that by disposing the second electrical connection structure 180 in the insulating Layer 160, electrical connection points between the first electrical connection structure 140 and an external device can be changed to meet connection requirements of different products.

The second electrical connection structure 180 may be formed by a metal plating process such as sputtering, electroplating, evaporation, etc., and the second electrical connection structure 180 may be made of a conductive material such as molybdenum, ruthenium, gold, silver, nickel, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium, or a composite or alloy thereof.

In order to improve the connection reliability between the external device and the second electrical connection structure 180, as shown in fig. 4, in the present application, at least a portion of the pad 181 is disposed on a surface of a side of the insulating layer 160 away from the second chip 120, and at least a portion of the pad 181 is in contact with the second electrical connection structure 180, and the pad 181 is directly exposed on the surface of the insulating layer 160, so that the external device can be electrically connected to the 3D chip package structure 100 through the pad 181.

Among them, the pad 181 may be Ni/Au formed to improve reliability of electrical connection.

In order to further improve the reliability of the electrical connection between the external device and the second electrical connection structure 180, in the embodiment of the present application, the bonding pad 181 is further provided with an electrical contact bump 182 protruding out of the surface of the insulating layer 160, for example, in fig. 2 and 3, the electrical contact bump 182 may be a solder ball, and the solder ball is used as a solder point for electrical connection with the external device, so as to improve the reliability of the electrical connection. The solder balls can be made of tin metal and other materials.

Of course, the bonding pad 181 may not be disposed on the insulating layer 160, and the electrical contact bump 182 electrically connected to the second electrical connection structure 180 may be directly disposed on the surface of the insulating layer 160, as shown in fig. 6, which may simplify the process and reduce the cost.

Specifically, the 3D chip package structure 100 may be electrically connected to other external devices through solder balls, in order to adapt to electrical connection between devices at different positions and the solder balls, the positions of the solder balls may be adaptively adjusted according to changes of the metal redistribution structure, in order to meet different metal redistribution requirements, in this embodiment, the insulating layer 160 may be set as at least one layer, that is, the insulating layer 160 may be one or more layers, and when the insulating layer 160 is a plurality of layers, the second electrical connection structure 180 may be metal-redistributed for multiple times, so that the electrical contact bumps 182 are set at appropriate positions as required; for example, in fig. 5, the insulating layer 160 has a single-layer structure; in fig. 2, 3, 4, 6 to 14, the insulating layer 160 has a double-layer structure, but the insulating layer 160 may be provided with two or more layers as necessary to further perform metal rerouting of the second electrical connection structure 180.

In some embodiments, the 3D chip package structure 100 may be a photosensitive chip, as shown in fig. 7, further including an optical lens 151, the first chip 110 has a light sensing surface facing away from the second chip 120, that is, the optical lens 151 is disposed on a side of the first chip 110 facing away from the first surface, the optical lens 151 is bonded to the light sensing surface through an optical adhesive 152, where the optical lens 151 may be optical glass or the like.

In some embodiments, the optical adhesive 152 has good light transmittance to improve light transmittance, thereby improving the operational reliability of the photosensitive chip.

It should be noted that the projection of the optical adhesive 152 on the first chip 110 covers the light sensing surface, that is, the whole surface of the optical adhesive 152 is flatly laid on the surface of the light sensing surface, so that the optical adhesive 152 can support the first chip 110 and the optical lens 151 while achieving the adhesion between the first chip 110 and the optical lens 151 and improving the light transmittance, so as to improve the strength of the first chip 110 and avoid the problem that the strength of the first chip 110 is low due to the reduced thickness.

In fig. 7, the first electrical connection structure 140 includes a first electrical contact 143 penetrating through two opposite sides of the first insulating encapsulation layer 130 and a second electrical contact 144 penetrating through two opposite sides of the first chip 110, and the first electrical contact 143 is in contact conduction with the second chip 120 and the second electrical contact 144, respectively.

In some embodiments, the first electrical contact 143 may be a conductive lead penetrating Through the first insulating encapsulation layer 130, and since the first chip 110 is made of a semiconductor material such as Silicon, a TSV (Through Silicon Vias) hole penetrating Through the first chip 110 may be disposed on the first chip 110, such that the TSV hole exposes a pin on an upper surface (i.e., a first surface) of the first chip 110, and a conductive metal is filled in the TSV hole to form the second electrical contact 144, wherein a portion of the second electrical contact 144 may be led out to the first surface of the first chip 110, such that the second electrical contact 144 is electrically connected to the pin on the first chip 110.

Referring to fig. 8, in some embodiments, the chip further includes a second insulating encapsulation layer 170, and the second insulating encapsulation layer 170 wraps at least a portion of an outer surface of the chip body, so that the outer surface of the chip body can be protected by the second insulating encapsulation layer 170, the outer surface of the chip body is prevented from being damaged by an external force, and the working reliability of the chip body is improved; in addition, by providing the second insulating encapsulation layer 170, the area of metal redistribution lines in the 3D chip encapsulation structure 100 can be increased, so that the 3D chip encapsulation structure 100 meets the arrangement requirements of electrical connection points of different external devices, in fig. 8, by providing the second insulating encapsulation layer 170 and manufacturing the electrical contact bumps 182 (solder joints) above the second insulating encapsulation layer 170, more electrical contact bumps 182 can be made, and thus the application range can be increased.

In some embodiments, the second insulating encapsulation layer 170 wraps the outer surface of the first chip 110 and the rest of the surface of the first insulating encapsulation layer 130 where the insulating layer 160 is not disposed, as shown in fig. 8, so that the second insulating encapsulation layer 170 can protect and support the exposed portions of the first chip 110 and the first insulating encapsulation layer 130; in addition, the projection of the insulating layer 160 on the second insulating encapsulation layer 170 covers the second insulating encapsulation layer 170, so that a plurality of welding spots can be led out on the upper surface of the insulating layer 160 to adapt to external devices with different structures.

In other embodiments, the second insulating encapsulation layer 170 wraps the outer surface of the first chip 110, as shown in fig. 9, in the embodiment of the present disclosure, an organic layer 200 is disposed between the first chip 110 and the first insulating encapsulation layer 130, and when the position of the first pin 141 on the first chip 110 is not properly disposed or the area of the first chip 110 is small, or the like, the organic layer 200 may be disposed to perform metal rerouting on the organic layer 200, so as to meet the packaging requirement of the product.

In other embodiments, the conductive layer 210 is disposed on the organic layer 200, and the conductive layer 210 is electrically connected between the first electrical connection structure 140 and the first pin 141, wherein a portion of the conductive layer 210 may be led out to a side surface of the organic layer 200 away from the first surface, so that the first electrical connection structure 140 may be vertically connected to the conductive layer 210, and an electrical connection point of the first electrical connection structure 140 and the conductive layer 210 does not overlap with an electrical connection point of the conductive layer 210 and the first pin on the first chip 110, and thus it can be seen that, by performing metal rerouting over the organic layer 200, a position of the electrical connection point of the first electrical connection structure 140 and the first pin 141 may be adjusted, thereby increasing an applicable range thereof.

It is to be understood that in the above embodiments, the organic layer 200 may be a plurality of layers, and the conductive layer 210 may be a plurality of layers.

In some embodiments, the number of the first chips 110 may also be at least two, and at least two first chips 110 are packaged with the second chip 120, so that the integration level of the 3D chip package structure 100 may be improved while the effects such as the storage capacity may be increased.

Illustratively, in fig. 10, there are two first chips 110, and preferably, the first surfaces of the two first chips 110 are located on the same plane, wherein the two first chips 110 may be the same or different. Preferably, a gap is provided between the first chips 110.

In addition, the outer surface of each first chip 110 is wrapped with a second insulating encapsulation layer 170, so that the outer surface of the first chip 110 is protected by the second insulating encapsulation layer 170, thereby improving the operational reliability of the first chip 110; in addition, the second insulating encapsulation layer 170 can improve the reliability of supporting the second chip 120 and increase the area of the metal rewiring of the electrical connection structure in the chip body.

In some embodiments, as shown in fig. 12, there is one first chip 110, the second chip 120 is disposed on the first chip 110, and in order to perform metal rerouting on the first electrical connection structure 140, so that the first electrical connection structure 140 is electrically connected to the first lead 141 on the first chip 110, an organic layer 200 may also be disposed between the first chip 110 and the second chip 120, and the metal rerouting is performed on the first electrical connection structure 140 above the organic layer 200, in fig. 12, a position where the first electrical connection structure 140 is vertically connected to the first chip 110 does not overlap with a position of the first lead 141, so that the first electrical connection structure 140 is electrically connected to the first lead 141 through the metal rerouting.

Of course, when the positions of the first electrical connection structures 140 vertically connected to the positions of the second pins 142 on the second chip 120 are not overlapped, the organic layer 200 may also be disposed on the side of the second chip 120 away from the first surface, as shown in fig. 13, so that the first electrical connection structures 140 are metal-rewired by being disposed above the organic layer 200, so as to achieve electrical connection between the first electrical connection structures 140 and the second pins 142 on the second chip 120.

Or, when the first electrical connection structure 140 is vertically connected to the first chip 110, the first electrical connection structure 140 is vertically connected to the second chip 120, and the positions of the first electrical connection structure 140 and the second chip 120 are not overlapped with the positions of the first pin 141 and the second pin 142, respectively, the organic layer 200 may be disposed between the first chip 110 and the second chip 120, and the organic layer 200 may also be disposed on the side of the second chip 120 away from the first surface, as shown in fig. 14, in this way, the first electrical connection structure 140 is re-wired with metal above the organic layer 200, so that the first electrical connection structure 140 is electrically connected to the first pin 141 and the second pin 142, respectively, thereby improving the wiring flexibility of the first electrical connection structure 140, and effectively improving the space utilization.

In the above embodiments, a layer of adhesive-backed film 190 may also be disposed on the surface of the first chip 110 on the side away from the second chip 120, and the surface of the first chip 110 is protected by the adhesive-backed film 190, as shown in fig. 2, since the adhesive-backed film 190 has a small thickness, the size of the 3D chip package structure 100 can be reduced, and the safety and reliability of the first chip 110 can be improved.

Example two

Fig. 15 is a flowchart illustrating a 3D chip packaging method according to an embodiment of the present application. In the embodiment of the present application, a packaging method of the structure in fig. 2 is taken as an example to illustrate a 3D chip packaging method provided in the embodiment of the present application.

Referring to fig. 15, an embodiment of the present application provides a 3D chip packaging method, which is applied to the 3D chip packaging structure 100 provided in the foregoing embodiment, and the method includes:

step S101: the second chip is arranged on the first surface of the first chip.

Specifically, as shown in fig. 16 and 17, before disposing the second chips 120 on the first surface of the first chip 110, a first incoming wafer 11 and a second incoming wafer 12 are first provided, where the first incoming wafer 11 includes a plurality of first chips 110, and the second incoming wafer 12 includes a plurality of second chips 120.

It should be noted that the first leads 141 and the second leads 142 have been prepared before being placed on the first incoming wafer 11 and the second incoming wafer 12, respectively, as shown in fig. 16 and 17; in addition, before the second chip 120 is disposed on the first surface of the first chip 110, the second incoming wafer 12 is first ground to a predetermined thickness by the processes of grinding and the like, wherein the predetermined thickness may be adaptively designed according to actual requirements, and is not limited herein.

Then, the second incoming wafer 12 is diced to form individual second chips 120, and as shown in fig. 18, the second incoming wafer 12 is diced to form individual second chips 120 after being polished to a predetermined thickness.

The cut single second chips 120 are attached to the first chips 110 on the first incoming wafer 11 through an adhesive layer such as an adhesive, and the structure shown in fig. 19 is that the second chips 120 are attached to at least one first chip 110 on the first incoming wafer 11.

Step S102: and forming a first insulating packaging layer on the first surface, wherein the first insulating packaging layer wraps the surface of the second chip.

As shown in fig. 20, after the second chip 120 is attached to the first chip 110, the first insulating encapsulation layer 130 may be formed on the first surface of the first chip 110 through an extrusion molding process, so that the first insulating encapsulation layer 130 wraps the surface of the second chip 120, thereby implementing the encapsulation of the first chip 110 and the second chip 120, the encapsulation process is simple, and the encapsulation cost can be reduced. Of course, the first insulating encapsulation layer 130 may also be formed on the first surface of the first chip 110 by processes of spraying, spin coating, film pasting, silk printing, and the like, which is not particularly limited.

Step S103: and forming a first electric connection structure on the first insulating packaging layer, wherein the first electric connection structure is electrically connected between the first chip and the second chip.

As shown in fig. 21, after the first insulating encapsulation layer 130 is formed on the first surface of the first chip 110, an electrical connection hole 131 may be formed on the first insulating encapsulation layer 130 using a laser, a machining, a plasma, an etching, or the like, such that one end of the electrical connection hole 131 exposes the pin on the first surface of the first chip 110 and the other end of the electrical connection hole 131 exposes the pin on the surface of the second chip 120.

After the electrical connection hole 131 is formed on the first insulating encapsulation layer 130, an electrical connector may be formed in the electrical connection hole 131 by a metal plating process such as sputtering, electroplating, evaporation, and the like to form a first electrical connection structure 140, such that the first electrical connection structure 140 is electrically connected to the pins of the first chip 110 and the second chip 120, respectively.

After the first electrical connection structure 140 is formed, as shown in fig. 22, a Wafer Level Chip Scale Packaging (WLCSP) process may be used to lead out the lines of the first electrical connection structure 140, for example, 2P2M, 1P1M, 2P1M, xPyM and other processes may be used; in the embodiment of the present invention, the insulating layer 160 may be formed on the first insulating packaging layer 130 by a 2P2M or 1P1M process, and the second electrical connection structure 180 may be formed on the insulating layer 160 by a metal rewiring method, so that the pad 181 on the insulating layer 160 or the electrical contact bump is formed at a proper position of the chip body by the metal rewiring method, and specifically, the insulating layer 160 may be adaptively designed as required, and the second electrical connection structure 180 that penetrates through the insulating layer 160 and the insulating layer 160 may be formed by the 2P2M or 1P1M process with reference to related technologies, which will not be described herein again.

In the xPyM, the x layer represents an organic layer, the y layer represents a metal layer, and if the insulating layer 160 is prepared by processes such as 2P2M, 1P1M, and 2P1M, xPyM, the insulating layer 160 is multi-layered, and the multi-layered insulating layer 160 is formed by alternately stacking organic layers and metal layers.

After the first electrical connection structure 140 is formed in the first insulating encapsulation layer 130, grinding the first chip 110 on a side thereof away from the first surface by a grinding process or the like so that the first chip 110 has a predetermined thickness; the predetermined thickness of the first chip 110 may be adaptively designed according to the requirement, and is not particularly limited herein.

After the first chips 110 are ground to a predetermined thickness, the ground first chips 110 are used as a reference unit to cut and separate the scribe lines between the adjacent first chips 110, thereby forming an independent 3D chip package structure.

Before the first chip 110 is cut after being ground to a predetermined thickness, an adhesive-backed film 190 may be further formed on a side of the first chip 110 away from the first surface, as shown in fig. 2, so as to protect the surface of the first chip 110 by the adhesive-backed film 190, thereby improving the safety and reliability of the first chip 110. Of course, the adhesive-backed film 190 may not be formed on the side of the first chip 110 away from the first surface.

While the 3D chip packaging method corresponding to fig. 3 to 11 can refer to the above packaging method, only the different steps of the structures of fig. 3 to 11 and fig. 2 in the manufacturing process will be described.

The structure in fig. 3 is the same as the structure in fig. 2 in the manufacturing process, except that when the second chip 120 is disposed on the first chip 110, the number of the second chips 120 is two or may be two or more, specifically, the structure is adaptively designed according to the requirement, and is disposed on the first chip 110 in an adhesion manner. The two second chips 120 may be the same chip or different chips.

The structure in fig. 8 differs from the structure in fig. 2 in the preparation: after the first electrical connection structure 140 is formed on the first insulating encapsulation layer 130 (as shown in fig. 19), the first raw wafer 11 is cut and separated into individual first chips 110, then the upper surface (i.e., the first surface) of the first chip 110 is placed on another carrier, where the carrier may be a bare silicon wafer, a carrier glass, or the like, and then the second insulating encapsulation layer 170 is formed on the surfaces of the first chip 110 and the first insulating encapsulation layer 130, after the second insulating encapsulation layer 170 is formed, the first chip 110 is peeled off from the carrier, and then the insulating layer 160 is formed on the surface of the first insulating encapsulation layer 130 away from the first chip 110, so that the insulating layer 160 covers the surface of the second insulating encapsulation layer 170, and the second electrical connection structure 180 is formed in the insulating layer 160.

The structure in fig. 9 differs from the structure in fig. 2 in the preparation: before the second chip 120 is attached to the first wafer 11, the first wafer 11 is first ground to a predetermined thickness, the first wafer 11 is then cut into individual first chips 110, the first chip 110 is then placed on another carrier with its upper surface (i.e., the first surface) facing downward, a second insulating encapsulation layer 170 is then formed on the exposed outer surface of the first chip 110, the first chip 110 is peeled off from the carrier after the second insulating encapsulation layer 170 is formed, an organic layer 200 is then formed on the surface of the first chip 110 not covered by the second insulating encapsulation layer 170, a conductive layer 210 is formed on the organic layer 200, the second chip 120 is then disposed on the side of the organic layer 200 away from the first chip 110, and a first insulating encapsulation layer 130 is formed on the surface of the organic layer 200, such that the first insulating encapsulation layer 130 covers the surface of the second chip 120, and a first electrical connection structure 140 is formed on the first insulating encapsulation layer 130.

Fig. 10 is the same as the manufacturing process of fig. 9, except that there are two first chips 110, but of course, there may be a plurality of first chips 110.

The embodiment of the application provides a 3D chip package structure includes first chip, second chip, first insulation packaging layer and first electric connection structure, and first chip has the first surface, and the second chip sets up in the first surface of first chip, and first insulation packaging layer sets up in the first surface to wrap up in the surface of second chip, first electric connection structure runs through first insulation packaging layer, and first electric connection structure electric connection is between first chip and second chip. In the above scheme, the second chip is arranged on the first surface of the first chip, and the first insulating packaging layer is formed on the first surface and wraps the surface of the second chip, so that the transmission speed of the chip can be increased, the packaging size can be optimized, the packaging process of the first chip and the second chip can be simplified, the complexity of the packaging process is reduced, and the total packaging cost is reduced.

In the description of the present application, it is to be understood that the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In the description above, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims (25)

1. The utility model provides a 3D chip package structure which characterized in that, includes the chip body, the chip body includes:

a first chip having a first surface;

the second chip is arranged on the first surface of the first chip;

the first insulating packaging layer is arranged on the first surface and wraps the surface of the second chip; and

the first electrical connection structure penetrates through the first insulating packaging layer and is electrically connected between the first chip and the second chip.

2. The 3D chip packaging structure according to claim 1, wherein projections of the second chip on the first chip are located inside edges of the first surface.

3. The 3D chip packaging structure according to claim 1, wherein the first insulating packaging layer extends to an edge of the first surface.

4. The 3D chip packaging structure according to claim 3, wherein an edge of the first insulating packaging layer is flush with an edge of the first surface.

5. The 3D chip packaging structure according to claim 1, wherein the first insulating packaging layer is an epoxy organic layer.

6. The 3D chip package structure according to any one of claims 1-5, wherein a pin is disposed on each of the first chip and the second chip, and the pin is connected to the first electrical connection structure.

7. The 3D chip packaging structure according to claim 6, wherein the leads include first leads disposed on the first chip, the first leads are disposed on the first surface, and positions of the first leads and positions of the second chip do not overlap with each other.

8. The 3D chip package structure according to claim 6, wherein the leads further comprise second leads disposed on the second chip, and the second leads are located on a side surface of the second chip facing away from the first chip.

9. The 3D chip packaging structure according to any one of claims 1-5, wherein an adhesive layer is disposed between the first chip and the second chip, the adhesive layer configured to adhere the first chip and the second chip.

10. The 3D chip package structure according to any one of claims 1-5, further comprising an optical lens, wherein the first chip has a light sensing surface facing a side away from the second chip, and the optical lens is bonded to the light sensing surface by an optical adhesive.

11. The 3D chip package structure according to claim 10, wherein the first electrical connection structure comprises a first electrical contact portion penetrating two opposite sides of the first insulating package layer and a second electrical contact portion penetrating two opposite sides of the first chip, and the first electrical contact portion is in contact conduction with the second chip and the second electrical contact portion respectively.

12. The 3D chip packaging structure according to claim 1, further comprising an insulating layer disposed on a side surface of the first insulating packaging layer facing away from the first chip.

13. The 3D chip packaging structure according to claim 12, further comprising a second insulating packaging layer, wherein the second insulating packaging layer wraps at least a part of an outer surface of the chip body.

14. The 3D chip packaging structure according to claim 13, wherein the second insulating packaging layer wraps around an outer surface of the first chip and a remaining surface of the first insulating packaging layer where the insulating layer is not disposed.

15. The 3D chip packaging structure according to claim 1, wherein the number of the second chips is at least two, and at least two of the second chips are disposed on the first surface.

16. The 3D chip packaging structure according to claim 1, wherein the number of the first chips is at least two.

17. The 3D chip package structure according to claim 12, further comprising a second electrical connection structure penetrating through the insulating layer, wherein the second electrical connection structure is in contact with the first electrical connection structure.

18. The 3D chip package structure according to claim 17, wherein a surface of a side of the insulating layer facing away from the second chip is provided with a pad, and the pad is in contact connection with the second electrical connection structure.

19. The 3D chip packaging structure according to claim 18, wherein an electrical contact bump protruding from the surface of the insulating layer is further disposed on the pad.

20. A3D chip packaging method, the method comprising:

arranging a second chip on the first surface of the first chip;

forming a first insulating packaging layer on the first surface, wherein the first insulating packaging layer wraps the surface of the second chip;

and forming a first electric connection structure on the first insulating packaging layer, wherein the first electric connection structure is electrically connected between the first chip and the second chip.

21. The 3D chip packaging method according to claim 20, wherein the forming of the first electrical connection structure on the first insulating packaging layer specifically comprises:

etching an electrical connection hole on the first insulating packaging layer; one end of the electrical connection hole exposes a part of the first pin on the surface of the first chip, and the other end of the electrical connection hole exposes a part of the second pin on the surface of the second chip;

forming an electrical connector in the electrical connection hole to form the first electrical connection structure, wherein the first electrical connection structure is electrically connected between the first pin of the first chip and the second pin of the second chip.

22. The 3D chip packaging method according to claim 20, wherein the disposing the second chip in front of the first surface of the first chip further comprises:

and forming a first pin on the first surface of the first chip, and forming a second pin on the surface of the second chip, which is far away from the first surface.

23. The 3D chip packaging method according to claim 20, further comprising, after the first insulating packaging layer forms the first electrical connection structure:

and grinding one side of the first chip, which is far away from the first surface, so that the first chip has a preset thickness.

24. The 3D chip packaging method according to claim 23, further comprising, after the grinding the side of the first chip facing away from the first surface:

and forming a back adhesive film on one side of the first chip, which is far away from the first surface.

25. The 3D chip packaging method according to claim 20, wherein the disposing the second chip in front of the first surface of the first chip further comprises:

grinding a second wafer containing a plurality of second chips to a preset thickness;

and cutting and separating the second raw material wafer ground to the preset thickness to form a plurality of single second chips.

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