CN217933791U

CN217933791U - Chip packaging structure

Info

Publication number: CN217933791U
Application number: CN202222192731.3U
Authority: CN
Inventors: 瞿宏宇; 潘远杰; 周祖源
Original assignee: Shenghejing Micro Semiconductor Jiangyin Co Ltd
Current assignee: SJ Semiconductor Jiangyin Corp
Priority date: 2022-08-19
Filing date: 2022-08-19
Publication date: 2022-11-29
Anticipated expiration: 2032-08-19

Abstract

The utility model provides a chip packaging structure, chip packaging structure forms the warpage preventing layer that has certain thickness through the scribing district lower surface in the intermediate layer panel, provides bending pressure for the intermediate layer panel through warpage preventing layer, reduces the warpage of intermediate layer panel to further reduce the yield loss that causes because of substrate panel warpage in the encapsulation process; moreover, a buffer layer is formed on the lower surface of the packaging area in the medium layer plate, and the buffer layer can prevent the packaging area from being concave and bent, so that the yield loss is avoided; the invention has simple structure, low cost and easy popularization and use.

Description

Chip packaging structure

Technical Field

The utility model relates to a semiconductor package field especially relates to a chip package structure.

Background

The packaging technology is developed along with the integrated circuit invention, the main functions are to complete power distribution, signal distribution, heat dissipation and protection, along with the development of the chip technology, the packaging technology is continuously updated, the packaging interconnection density is continuously improved, the packaging thickness is continuously reduced, the three-dimensional packaging and system packaging means are continuously evolved, along with the diversification of the application of the integrated circuit, the advanced packaging is required in the emerging fields of smart phones, internet of things, automotive electronics, high-performance computing, 5G, artificial intelligence and the like, the packaging technology is rapidly developed, and the innovation technology is continuously appeared.

On the automatic bonding line of semiconductor package, the substrate plate applied to the bonding process is very thin (the currently generally applied specification is less than 1 mm), and is far less than the length and width of the substrate plate, and the substrate plate is usually internally provided with pre-buried circuits, through holes and the like, so that partial areas are easy to warp and not flat, which can cause inaccurate positioning, a chip cannot be inserted into the holes of the plate and a surface mounting pad, the phenomena of material throwing and material leakage can be generated, and even an automatic bonding machine can be damaged by collision, which has a great influence on the yield of the packaging process.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a chip package structure, so as to solve the problem that the warpage of a substrate board affects the chip bonding yield in the prior art.

To achieve the above and other related objects, the present invention provides a chip package structure, which includes: the chip package comprises an intermediate layer plate, an anti-warping layer and a plurality of chips;

the interposer board comprises a plurality of packaging areas and scribing areas, wherein the packaging areas are arranged in an array, and the scribing areas are arranged around the periphery of the packaging areas; the packaging region is embedded with a pre-buried line, and the pre-buried line is led out to the upper surface of the packaging region through at least one connecting welding pad;

the anti-warping layer is at least formed on the lower surface of the scribing area;

and a micro bump is arranged on the active surface of the chip and is in bonding connection with the connecting welding pad.

Optionally, the warpage prevention layer includes a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer.

Optionally, the chip package structure further includes: and the buffer layer is formed on the lower surface of the packaging area.

Optionally, the buffer layer comprises a layer of a photodegradable organic gel.

Optionally, the thickness of the buffer layer is the same as that of the warp-proof layer, and the thickness of the warp-proof layer is greater than or equal to 0.5 μm.

Optionally, the thickness of the interposer sheet is between 0.2mm and 1 mm.

Optionally, the chips are bare chips, and at least one of the chips is bonded to each of the package regions.

Optionally, the chip package structure further includes: and the filling adhesive layer is formed in a gap between the packaging area and the chip.

Optionally, the chip package structure further includes: a plastic packaging material layer formed on the upper surface of the medium layer plate and coating the chip,

as described above, the present invention provides a chip package structure, which forms a warpage preventing layer with a certain thickness on the lower surface of a scribing region in an interposer board, so as to provide bending pressure for the interposer board through the warpage preventing layer, thereby reducing warpage of the interposer board, and further reducing yield loss caused by warpage of a substrate board in a packaging process; moreover, a buffer layer is formed on the lower surface of the packaging area in the medium layer plate, and the buffer layer can prevent the packaging area from being concave and bent, so that the yield loss is avoided; the invention has simple structure, low cost and easy popularization and use.

Drawings

Fig. 1 is a top view of an interposer board according to the present invention.

Fig. 2 is a side view of the interposer board according to the present invention.

Fig. 3 shows a schematic structural diagram of the anti-warp layer formed according to the present invention.

Fig. 4 is a schematic structural diagram of the buffer layer according to the present invention.

Fig. 5 shows the schematic structure diagram after the connection pads are formed.

Fig. 6 is a schematic structural diagram of the package region after being bonded to a chip according to the present invention.

Fig. 7 shows the schematic structure of the present invention after the glue filling is formed.

Fig. 8 shows a schematic structural diagram after the plastic packaging material layer is formed according to the present invention.

Description of the element reference

10. Chip packaging structure

100. Interposer sheet

110. Packaging region

111. Connection pad

120. Scribing block

200. Anti-warping layer

300. Buffer layer

400. Chip and method for manufacturing the same

410. Micro-bump

500. Filling adhesive

600. Layer of plastic packaging material

Detailed Description

The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to fig. 1 to 8. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the invention in a schematic manner, and only the components related to the invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.

As shown in fig. 6, the present example provides a chip package structure 10, where the chip package structure 10 includes: an interposer sheet 100, an anti-warpage layer 200, and a plurality of chips 400.

The interposer board 100 includes a plurality of package regions 110 and a scribe region 120, wherein the package regions 110 are arranged in an array, and the scribe region 120 is disposed around the package regions 110.

In this embodiment, in an actual packaging process, for the sake of process efficiency, the package regions 110 bonded to the chips 400 are not independent monolithic structures, and are usually arranged in an array on the interposer board 100 (as shown in fig. 1), and are cut and separated into individual package substrates only after the chip bonding and the injection molding (molding) process are completed; the interposer board 100 is generally a rectangular sheet structure, and the material thereof can be selected according to different requirements, and includes organic and/or inorganic substances, for example: polyamide fibers, polyimide, epoxy resin, polyparaphenylene benzobisoxazole fibers, FR4 epoxy glass cloth laminate, semi-cured resin, and the like, and the inorganic substance may be, for example, silicon, glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, and the like.

Specifically, the thickness of the interposer board 100 is between 0.2mm and 1 mm.

In this embodiment, the interposer 100 is a sheet structure, and the thickness thereof is much smaller than the length and width thereof, so that the warpage is easily generated.

As an example, as shown in fig. 1 and fig. 2, the interposer board 100 has a size of 20mm × 20mm and a thickness of 750 μm, and includes 24 package regions 110, which are arranged in a 3 × 8 array; each packaging region 110 has a size of 68mm × 178mm and a thickness of 750 μm, and there is a buffer region of 2mm between each packaging region 110, and a buffer region of 2mm is reserved between each packaging region 110 at the edge of the interposer 100 and the boundary of the interposer 100, and these buffer regions are defined as the scribe regions 120.

The encapsulation area 110 is embedded with a pre-buried line, and the pre-buried line is led out to the upper surface of the encapsulation area 110 through at least one connection pad 111.

In this embodiment, the type of the pre-buried line includes a wire, a through hole, a buried hole, a blind hole, or the like; it should be noted that the size or direction of the through hole, buried hole or blind hole is not particularly limited. If through holes, buried holes or blind holes are provided, the through holes, buried holes or blind holes may be filled with or contain a conductive material such as a metal or a metal alloy. Here, the metal may be, for example, gold (Au), silver (Ag), aluminum (Al), copper (Cu), or an alloy thereof. The connection pads 111 may be various types of electrical connection points, such as solder bumps and conductive pillar bumps, and connect the package region 110 and the chip 400 through the connection pads 111.

The warpage preventing layer 200 is formed at least on the lower surface of the scribe region 120.

In this embodiment, as shown in fig. 3, the anti-warping layer 200 formed on the lower surface of the scribe region 120 may be made of silicon nitride, silicon oxide, or silicon oxynitride, which are electrically insulating and can provide bending strength to the interposer 100, and not only the anti-warping layer 200 is formed on the lower surface of the scribe region 120, but also the anti-warping layer 200 is formed on the lower surface of the package region 110, that is, the anti-warping layer 200 is formed on the lower surface of the interposer 100, so that the anti-warping layer with a larger area provides a larger bending strength to the interposer 100. The method for forming the anti-warp layer 200 includes, but is not limited to, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, an Atomic Layer Deposition (ALD) process, or a Physical Vapor Deposition (PVD) process.

Specifically, the chip package structure 10 further includes: a buffer layer 300; the warpage prevention layer 200 is formed on the lower surface of the scribe region 120, and the buffer layer 300 is formed on the lower surface of the package region 110.

In this embodiment, as shown in fig. 4, the anti-warpage layer 200 is formed only on the lower surface of the scribe region 120, and the buffer layer 300 is formed on the lower surface of the package region 110, and the thickness of the buffer layer is the same as that of the anti-warpage layer 200; also, the cushioning layer 300 should be made of a material that can release its adhesiveness, such as a photodegradable organic gel; before the interposer sheet material 100 is cut into a single package substrate, a material support can be provided for the package region 110, so as to prevent the package region 110 from being recessed and deformed, and after the interposer sheet material 100 is cut into a single package substrate, the photodegradable organic gel can be photolyzed and removed, and cannot be continuously adhered to the lower surface of the package region 110, so that the normal use function of the package region 110 is not affected.

Specifically, the thickness of the anti-warp layer 200 is greater than or equal to 0.5 μm.

In this embodiment, when a silicon oxide material is used, taking the case that the anti-warpage layer 200 is formed only in the scribe region 110 as an example, when the width of the anti-warpage layer 200 is 2mm, the thickness of the anti-warpage layer 200 should be at least greater than 0.5 μm, so as to provide a bending pressure of at least 100 mpa for the interposer board 100, thereby preventing the interposer board 100 from warping; preferably, the thickness should be at least greater than 1.5 μm, which can provide a bending pressure of at least 250 MPa for the interposer web 100. In practical applications, because different materials have different bending strengths and can provide different bending pressures for the interposer board 100 under the same thickness, the material and thickness of the anti-warping layer 200 can be selected according to practical applications.

The active surface of the chip 400 is provided with a micro bump 410, and the micro bump 410 is bonded to the connection pad 111.

In this embodiment, as shown in fig. 6, the active surface of the chip 400 refers to a surface that needs to be electrically connected with a substrate in a bonding manner, and the chip 400 may be one or a combination of a bare chip and a packaged chip, and includes various active or passive elements. The active surface of the chip 400 is provided with a plurality of micro bumps 410, the micro bumps 410 are bonded and connected with the connection pads 111 through flip chip bonding, and in some embodiments, the micro bumps 410 may also be replaced by pre-solder. Also, the number of the flip-chip bonded chips 400 on each of the package regions 110 is at least one, and if the number is greater than 1, a space should be formed between the adjacent chips 400 for isolation.

The embodiment further provides a method for manufacturing the chip package structure 10, where the method for manufacturing the chip package structure 10 includes: and S1 to S6. Further, steps S7 and S8 are included.

S1): as shown in fig. 1-2, an interposer web 100 is provided. The interposer 100 includes a plurality of package regions 110 and a scribe region 120, and the package regions 110 have pre-buried lines (not shown).

As an example, taking the pre-buried lines arranged in the package region 110 as the through-silicon vias and the conductive pillars as an example: firstly, forming a silicon through hole in the packaging area 110, wherein the method for forming the silicon through hole comprises one or a combination of laser drilling, mechanical drilling, deep reactive ion etching and photo-assisted electrochemical etching; filling a conductive material in the through silicon via to form a through silicon via conductive column, wherein the conductive material is one or a combination of copper, aluminum, gold, silver, nickel, titanium, tantalum and the like, and the filling method is any one or a combination of electroplating, chemical plating, silk-screen printing and wire bonding; also, typically to prevent diffusion of the conductive material into the encapsulation region 110 and increase the adhesion strength between the conductive material and the encapsulation region 110, a layer of one or a combination of Ta, taN, ti, tiN is deposited as a diffusion barrier or adhesion layer.

S2): as shown in fig. 3, a warpage preventing layer 200 is formed on the lower surface of the scribe region 120.

As an example, the method for forming the anti-warp layer 200 on the lower surface of the scribe region 110 includes, but is not limited to, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, an Atomic Layer Deposition (ALD) process, or a Physical Vapor Deposition (PVD) process; the thickness of the anti-warping layer 200 should be at least greater than 0.5 μm, so that the anti-warping layer 200 provides a bending pressure of at least greater than 100 mpa for the interposer board material 100.

S2): as shown in fig. 4, a buffer layer 300 is formed on the lower surface of the encapsulation region 110.

As an example, the buffer layer 300 is formed on the lower surface of the package region 110 by a method including, but not limited to, coating, spraying, and the like, and the thickness of the buffer layer 300 is consistent with the thickness of the anti-warp layer 200 to prevent the package region 110 from being bent downward.

S4): as shown in fig. 5, a plurality of connection pads 111 are formed on the upper surface of the package region 110. In this embodiment, the connection pads 111 include, but are not limited to, solder balls or solder bumps, or metal micro-pillars with solder balls on top. And, the connection pad 111 is electrically connected to the pre-buried line in the substrate 110.

S5): as shown in fig. 6, at least one chip 400 is provided, and a plurality of micro bumps are formed on the active surface of the chip 120.

Specifically, the chip 400 includes one or a combination of a bare chip and a packaged chip, and is specifically configured according to actual needs, and is not particularly limited herein. In the embodiment, the number of the chips 400 on each package region 110 is shown as 1, but the number of the chips 120 is not limited thereto, and the number of the chips 120 on each package region 110 may be greater than or equal to 2 according to requirements.

S6): as shown in fig. 6, the connection pads 111 are bonded to the micro bumps 410, so as to bond the chip 400 to the package region 110.

In this example, the bumps 410 of the chip 400 and the top pads 111 of the package region 110 are bonded by flip chip bonding, that is, the connection between the chip 400 and the package region 100 is realized.

S7): as shown in fig. 7, a gap between the chip 400 and the package region 110 is filled with a filling adhesive 500.

In this embodiment, the material of the filling adhesive 140 includes, but is not limited to, epoxy resin. The filling adhesive 500 can protect the chip from the influence of the environment, reduce the influence of the thermal expansion mismatch between the chip and the substrate, and greatly improve the reliability of the element. The filling method of the filling paste 500 includes, but is not limited to, a capillary underfill method.

S8): as shown in fig. 8, a molding compound layer 600 is formed on the upper surface of the interposer 100, and the molding compound layer 600 covers the chip 400.

In this embodiment, the molding compound layer 600 covering the chip 400 includes, but is not limited to, a polyimide layer, a silicone layer, and an epoxy resin layer, and the method for forming the molding compound layer 600 includes, but is not limited to, processes such as compression molding, transfer molding, liquid sealing molding, molding underfill, capillary underfill, vacuum lamination, and spin coating.

To sum up, the chip package structure provided by the present invention forms the warpage preventing layer with a certain thickness on the lower surface of the scribing region in the interposer board, provides a bending pressure for the interposer board through the warpage preventing layer, reduces the warpage of the interposer board, and further reduces the yield loss of the package process due to the warpage of the substrate board; moreover, the buffer layer is formed on the lower surface of the packaging area in the medium layer plate, and the concave bending of the packaging area can be avoided by means of the buffer layer, so that the yield loss is avoided; the invention has simple structure, low cost and easy popularization and use. Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A chip package structure, comprising: the chip package comprises an intermediate layer plate, an anti-warping layer and a plurality of chips;

2. The chip package structure of claim 1, wherein the warpage prevention layer comprises a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer.

3. The chip package structure according to claim 1, further comprising: and the buffer layer is formed on the lower surface of the packaging area.

4. The chip package structure of claim 3, wherein the buffer layer comprises a photodegradable organic gel layer.

5. The chip package structure of claim 3, wherein the buffer layer has a thickness equal to that of the warpage prevention layer, and the warpage prevention layer has a thickness greater than or equal to 0.5 μm.

6. The chip package structure according to claim 1, wherein the interposer sheet has a thickness of 0.2mm to 1 mm.

7. The chip package structure according to claim 1, wherein the chips are bare chips, and at least one of the chips is bonded to each of the package regions.

8. The chip package structure according to claim 1, further comprising: and the filling adhesive layer is formed in a gap between the packaging area and the chip.

9. The chip package structure according to claim 1, further comprising: and the plastic packaging material layer is formed on the upper surface of the medium layer plate and covers the chip.