CN109599378A - A kind of encapsulating structure and preparation method of chip - Google Patents
A kind of encapsulating structure and preparation method of chip Download PDFInfo
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- CN109599378A CN109599378A CN201811574268.0A CN201811574268A CN109599378A CN 109599378 A CN109599378 A CN 109599378A CN 201811574268 A CN201811574268 A CN 201811574268A CN 109599378 A CN109599378 A CN 109599378A
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- chip
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- groove
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- packaging structure
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- 238000002360 preparation method Methods 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 57
- 238000004806 packaging method and process Methods 0.000 claims abstract description 53
- 235000012431 wafers Nutrition 0.000 claims description 14
- 238000009434 installation Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 14
- 239000000463 material Substances 0.000 abstract description 10
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 238000005516 engineering process Methods 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02333—Structure of the redistribution layers being a bump
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/17104—Disposition relative to the bonding areas, e.g. bond pads
- H01L2224/17106—Disposition relative to the bonding areas, e.g. bond pads the bump connectors being bonded to at least one common bonding area
Abstract
The invention discloses a kind of chip-packaging structure and preparation methods, wherein chip-packaging structure, it include: interposer substrate, with first surface and with the opposed second surface of the first surface, it is equipped at least one groove extended to second surface on the first surface, in the groove at least one embedding pre-buried route；Chip, setting in the groove, there is at least one to stretch out pin, and the pre-buried route stretched out in pin and the groove interconnects.Preparation method provided by the invention, it is in advance that route is embedding using interposer technique, it is possible to prevente effectively from when the prior art uses the high-temperature high-pressure craft of the back side TSV lead, the high temperature and pressure of generation makes the thermal expansion coefficient of multiple material in chip package mismatch bring warpage issues, a variety of permanent bonding technologies can be used, reliability is higher.Interposer substrate can use the wafer or 12 inch square plates of 12 inch, and the generally less than wafer of 6 inch, can be significantly increased production capacity compared with prior art.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, and in particular to a kind of encapsulating structure and preparation method of chip.
Background technique
Existing filter package structure is the functional surfaces bonding substrate in chip, and through silicon via is then carried out on substrate
(Through Silicon Vias, TSV) interconnection architecture, the electrical property in chip functions face is led on substrate, since silicon is heat
Good conductor, heating conduction can be obviously improved, to extend the service life of device.But the electrical property in chip functions face is drawn
It is more demanding for bonding blade technolgy out to needing on substrate using the back side TSV lead technique, need high-temperature high-pressure craft, work
Skill is unstable, which is temporarily bonded and tears open bonding movement to guarantee that subsequent sheet processing needs to do, and due to
It is high much for the thermal expansion coefficient of chip substrate material is compared with silicon substrate, it is easy to appear during back segment wafer level processing
Because the thermal expansion coefficient of multiple material mismatches bring warpage issues, even more the serious is the knots to final products itself
Structure intensity band carrys out hidden danger.
Summary of the invention
Therefore, the present invention provides the encapsulating structure and preparation method of a kind of chip, effectively prevents the prior art to filtering
When device chip is packaged, asking for mass defect hidden danger is brought in the high-temperature high-pressure craft manufacturing process using the back side TSV lead
Topic.
In a first aspect, the embodiment of the invention provides a kind of chip-packaging structures, comprising: interposer substrate has the first table
Face and with the opposed second surface of the first surface, on the first surface be equipped at least one to second surface extend it is recessed
Slot, in the groove at least one embedding pre-buried route；Chip, setting in the groove, there is at least one stretching to draw
Foot, the pre-buried route stretched out in pin and the groove interconnect.
In implementing one, the chip-packaging structure, further includes: plastic packaging layer, interposer substrate described in the plastic packaging layer plastic packaging
First surface and the chip.
In implementing one, the pre-buried route is through the groove to the second surface.
In implementing one, the chip-packaging structure, further includes: pin layer is formed in the second table of the interposer substrate
On face, interconnected with the pre-buried route.
In implementing one, pin is fanned out on the surface of the pin layer.
In implementing one, the interposer substrate is 12 inch wafers or 12 inch square plates.
In implementing one, the chip is filter chip.
Second aspect includes the following steps: to mention the embodiment of the invention provides a kind of preparation method of chip-packaging structure
For an interposer substrate, the interposer substrate have first surface and with the opposed second surface of the first surface；Described
The groove extended to second surface at least one is opened up on the first surface of interposer substrate, and in the groove embedding at least one
A pre-buried route；By chip installation in the groove, the chip have at least one stretch out pin, the stretchings pin and
The pre-buried route interconnection.
In implementing one, the preparation method of said chip encapsulating structure, further includes: by the second surface of the interposer substrate
Carry out thinned, the exposing pre-buried route.
In implementing one, the preparation method of said chip encapsulating structure, further includes: by the first table of the interposer substrate
Face and the chip carry out plastic packaging.
In implementing one, the preparation method of above-mentioned chip-packaging structure, further includes: in the second table of the interposer substrate
Pin layer is formed on face, the pin layer includes pin, is fanned out to the pin layer surface.
Technical solution of the present invention has the advantages that
1, chip-packaging structure provided in an embodiment of the present invention and preparation method, wherein chip-packaging structure, comprising: switching
Substrate, have first surface and with the opposed second surface of the first surface, on the first surface be equipped at least one to
The groove that second surface extends, in the groove at least one embedding pre-buried route；Chip, setting in the groove, have
There is at least one to stretch out pin, the pre-buried route stretched out in pin and the groove interconnects.Preparation provided in an embodiment of the present invention
Method use in interposer substrate it is in advance that route is embedding, during encapsulation, be not necessarily to the back side TSV lead technique, can be effective
When avoiding the prior art using the back side TSV lead technique, the high temperature and pressure of generation makes the heat of multiple material in chip package swollen
Swollen coefficient mismatches bring warpage issues.
2, chip-packaging structure provided in an embodiment of the present invention and preparation method can use a variety of permanent bonding technologies,
Reliability is higher.Interposer substrate can use 12 inch wafers or 12 inch square plates, compared with prior art the generally less than wafer of 6 inch,
Production capacity can be significantly increased.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is the structure chart of a specific example of chip-packaging structure provided in an embodiment of the present invention；
Fig. 2 is the structure chart of another specific example of chip-packaging structure provided in an embodiment of the present invention；
Fig. 3 is the structure chart of another specific example of chip-packaging structure provided in an embodiment of the present invention；
Fig. 4 is the structure chart of another specific example of chip-packaging structure provided in an embodiment of the present invention；
Fig. 5 is the structure chart of another specific example of chip-packaging structure provided in an embodiment of the present invention；
Fig. 6 is the structure chart of another specific example of chip-packaging structure provided in an embodiment of the present invention；
Fig. 7 is the structure chart of another specific example of chip-packaging structure provided in an embodiment of the present invention；
Fig. 8 is the flow chart of a specific example of the preparation method of chip-packaging structure provided in an embodiment of the present invention；
Fig. 9 is the structure for executing step S2 in the preparation method of chip-packaging structure provided in an embodiment of the present invention and being formed；
Figure 10 is the process of another specific example of the preparation method of chip-packaging structure provided in an embodiment of the present invention
Figure；
Figure 11 is the process of another specific example of the preparation method of chip-packaging structure provided in an embodiment of the present invention
Figure.
Appended drawing reference:
1, interposer substrate；11, first surface；12, second surface；13, groove；
14, pre-buried route；2, chip；3, pin is stretched out；4, plastic packaging layer；
5, pin layer；51, pin.
Specific embodiment
Technical solution of the present invention is clearly and completely described below in conjunction with attached drawing, it is clear that described implementation
Example is a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill
Personnel's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
As long as in addition, the non-structure each other of technical characteristic involved in invention described below different embodiments
It can be combined with each other at conflict.
Embodiment 1
The embodiment of the present invention provides a kind of chip-packaging structure, as shown in Figure 1, the structure includes: interposer substrate 1, has
First surface 11 and with the opposed second surface 12 of first surface 11, at least one is equipped on first surface 11 to the second table
The groove 13 that face 12 extends, at least one pre-buried route 14 of 13 embedded set of groove；Chip 2 is arranged in groove 13, has extremely
A few stretching pin 3 stretches out pin 3 and is electrically connected with the pre-buried route 14 in groove 13.
In the present embodiment, the chip 2 in chip-packaging structure shown in FIG. 1 is that there are two the filters for stretching out pin for tool
Chip, however, it is not limited to this in other embodiments, can be the chip with other stretching pin numbers.
Provided in this embodiment kind of chip-packaging structure will be used in advance using interposer technique (interposer substrate technique)
It is embedding in conductive pre-buried route, it is possible to prevente effectively from being produced when using the high-temperature high-pressure craft of the back side TSV lead in the prior art
Raw high temperature and pressure brings the thermal expansion coefficient of chip substrate material compared with the thermal expansion coefficient mismatch of the materials such as silicon substrate
Warpage issues.And a variety of permanent bonding technologies can be used, reliability is higher.
In a preferred embodiment, interposer substrate is 12 inch wafers or 12 inch square plates.Switching is generallyd use in the prior art
The wafer of substrate is generally less than 6 inch, and the present embodiment is recombinated to form 12 inch wafers or 12 inch square plates by inverse bonding, can be significantly increased
Production capacity.
In one embodiment, as shown in Fig. 2, said chip encapsulating structure further include: plastic packaging layer 4, the switching of 4 plastic packaging of plastic packaging layer
The first surface 11 and chip 2 of substrate 1, the plastic packaging layer 4 formed by capsulation material is by the first surface 11 and core of interposer substrate 1
Piece 2 carries out plastic packaging, and the confined space being capable of forming can preferably protect chip 2, so that chip 2 uses, the service life is longer.
In one embodiment, structure as shown in Figure 3 or Figure 4 can realize built-in line by thinned or photoetching process
14 through-going recess 13 of road is produced the function of chip 2 by pre-buried route 14 to second surface 12.
In a preferred embodiment, as shown in figure 5, said chip encapsulating structure further include: pin layer 5 is formed in switching
On the second surface 12 of substrate 1, it is electrically connected with pre-buried route 14.It is electrically connected by the pre-buried route 14 of pin layer 5, Lai Zeng great chip
2 are fanned out to area.
In a preferred embodiment, as is seen in fig. 6 or fig. 7, pin layer 5 includes: pin 51, is fanned out on 5 surface of pin layer.
Pin 51 can be soldered ball, other conductive pins such as solder joint facilitate and connect other electronic devices.
Chip-packaging structure provided in an embodiment of the present invention, comprising: interposer substrate has first surface and with described first
The opposed second surface in surface is equipped at least one groove extended to second surface, in the groove on the first surface
At least one pre-buried route of embedded set；Chip, setting in the groove, have at least one stretch out pin, stretch out pin with
Pre-buried route interconnection in the groove.It is in advance that route is embedding using interposer technique, it is possible to prevente effectively from existing skill
When art uses the high-temperature high-pressure craft of the back side TSV lead, the high temperature and pressure of generation makes the heat of multiple material in chip package swollen
Swollen coefficient mismatches bring warpage issues.And a variety of permanent bonding technologies can be used, reliability is higher.Interposer substrate can
With using the wafer or 12 inch square plates of 12 inch, the generally less than wafer of 6 inch, can be significantly increased production capacity compared with prior art.
Embodiment 2
The embodiment of the present invention provides a kind of preparation method of chip-packaging structure, as shown in figure 8, including the following steps:
Step S1: provide an interposer substrate, interposer substrate have first surface and with opposed second table of first surface
Face.
In the present embodiment, interposer substrate is 12 inch wafers, compared with the prior art the middle wafer less than 6 inch used,
Production capacity can be significantly increased, interposer substrate can be silicon substrate or glass base, only illustrate, be not limited thereto with this.
Step S2: the groove extended to second surface at least one is opened up on the first surface of interposer substrate, and recessed
At least one pre-buried route of slot embedded set.
In the present embodiment, it executes step S2 and forms structure as shown in Figure 9.In practical applications, the number of pre-buried route
Amount can determine that the quantity of pre-buried route is not less than the stretching number of pins that encapsulate chip according to the stretching pin of chip to be encapsulated
Amount.
Step S3: chip is mounted in groove, and there is chip at least one to stretch out pin, stretches out pin and pre-buried route
Interconnection.
Chip-packaging structure as shown in Figure 1 is formed by the step S1~step S3 for executing above-mentioned.It is right in the present embodiment
Filter chip is packaged, therefore is electrically connected in two pre-buried routes of groove embedded set and two stretching pins, only
It is illustrated, is not limited thereto with this.
In implementing one, after executing step S3, as shown in Figure 10, following steps are continued to execute:
Step S4: the second surface of interposer substrate being carried out thinned, exposes pre-buried route.
In the present embodiment, by reduction processing, the second surface of interposer substrate is exposed into pre-buried route, by packed core
Piece carries out function and is gone out by built-in line pass.In other embodiments, pre-buried route through-going recess can be made by other means,
Such as photoetching process.
Step S5: pin layer is formed on the second surface of interposer substrate, pin layer includes pin, is fanned out to pin layer table
Face.
It in the present embodiment, is interconnected by pin layer and pre-buried route, Lai Zeng great chip is fanned out to area, and pin can be weldering
Ball, other conductive pins such as solder joint facilitate and connect other electronic devices.
In the present embodiment, by executing above-mentioned step S1~step S5, encapsulating structure as shown in FIG. 6 can be formed.
In a preferred embodiment, after executing step S3, as shown in figure 11, following steps are continued to execute:
Step S41: the first surface of interposer substrate and chip are subjected to plastic packaging.
In the present embodiment, the first surface of interposer substrate and chip are moulded by the plastic packaging layer that capsulation material is formed
Envelope, the confined space being capable of forming can preferably protect chip, so that chip uses, the service life is longer.
Step S51: the second surface of interposer substrate being carried out thinned, exposes pre-buried route.
In the present embodiment, it can realize that pre-buried route through-going recess, will by pre-buried route to second surface by being thinned
The function of chip produces.In other embodiments, pre-buried route through-going recess, such as photoetching work can be made by other means
Skill.
Step S61: pin layer is formed on the second surface of interposer substrate, pin layer includes pin, is fanned out to pin layer table
Face.
It in the present embodiment, is interconnected by pin layer and pre-buried route, Lai Zeng great chip is fanned out to area, and pin can be weldering
Ball, other conductive pins such as solder joint facilitate and connect other electronic devices.
In the present embodiment, by executing above-mentioned step S1~step S61, encapsulating structure as shown in Figure 7 can be formed.
Chip package preparation method provided in an embodiment of the present invention, it is in advance that route is embedding using interposer technique,
It is possible to prevente effectively from the prior art uses the high-temperature high-pressure craft of the back side TSV lead, the high temperature and pressure of generation makes chip package
The thermal expansion coefficient of middle multiple material mismatches bring warpage issues；A variety of permanent bonding technologies can be used, reliability is more
It is high.Interposer substrate can use the wafer or 12 inch square plates of 12 inch, compared with prior art the generally less than wafer of 6 inch, Neng Gou great
Width increases production capacity.
Obviously, the above embodiments are merely examples for clarifying the description, and does not limit the embodiments.It is right
For those of ordinary skill in the art, can also make on the basis of the above description it is other it is various forms of variation or
It changes.There is no necessity and possibility to exhaust all the enbodiments.And thus amplify out it is obvious variation or
It changes still within the protection scope of the invention.
Claims (10)
1. a kind of chip-packaging structure characterized by comprising
Interposer substrate, have first surface and with the opposed second surface of the first surface, on the first surface be equipped with extremely
Lack the groove extended to second surface, in the groove at least one embedding pre-buried route；
Chip, setting in the groove, have at least one stretch out pin, the stretching pin with it is pre-buried in the groove
Route interconnection.
2. chip-packaging structure according to claim 1, which is characterized in that further include: plastic packaging layer, the plastic packaging layer plastic packaging
The first surface of the interposer substrate and the chip.
3. chip-packaging structure according to claim 1 or 2, which is characterized in that the pre-buried route runs through the groove
To the second surface.
4. chip-packaging structure according to claim 3, which is characterized in that further include:
Pin layer is formed on the second surface of the interposer substrate, is interconnected with the pre-buried route.
5. chip-packaging structure according to claim 4, which is characterized in that the pin layer includes:
Pin is fanned out on the surface of the pin layer.
6. -5 any chip-packaging structure according to claim 1, which is characterized in that the interposer substrate is 12 inch wafers
Or 12 inch square plate.
7. a kind of preparation method of chip-packaging structure, which comprises the steps of:
One interposer substrate is provided, the interposer substrate have first surface and with the opposed second surface of the first surface；
The groove extended to second surface at least one is opened up on the first surface of the interposer substrate, and in the groove
At least one embedding pre-buried route；
By chip installation in the groove, the chip have at least one stretch out pin, the stretching pin with it is described pre-
Sunken cord road interconnection.
8. the preparation method of chip-packaging structure according to claim 7, which is characterized in that further include:
The first surface of the interposer substrate and the chip are subjected to plastic packaging.
9. the preparation method of chip-packaging structure according to claim 7 or 8, which is characterized in that further include:
The second surface of the interposer substrate is carried out to thinned, the exposing pre-buried route.
10. the preparation method of chip-packaging structure according to claim 9, which is characterized in that further include:
Pin layer is formed on the second surface of the interposer substrate, the pin layer includes pin, is fanned out to the pin layer table
Face.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811574268.0A CN109599378A (en) | 2018-12-21 | 2018-12-21 | A kind of encapsulating structure and preparation method of chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811574268.0A CN109599378A (en) | 2018-12-21 | 2018-12-21 | A kind of encapsulating structure and preparation method of chip |
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| CN109599378A true CN109599378A (en) | 2019-04-09 |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030164551A1 (en) * | 2002-03-04 | 2003-09-04 | Lee Teck Kheng | Method and apparatus for flip-chip packaging providing testing capability |
| US20060151870A1 (en) * | 2002-11-21 | 2006-07-13 | Nec Corporation | Semiconductor device, wiring substrate, and method for manufacturing wiring substrate |
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| US20030164551A1 (en) * | 2002-03-04 | 2003-09-04 | Lee Teck Kheng | Method and apparatus for flip-chip packaging providing testing capability |
| US20060151870A1 (en) * | 2002-11-21 | 2006-07-13 | Nec Corporation | Semiconductor device, wiring substrate, and method for manufacturing wiring substrate |
| CN101794738A (en) * | 2009-01-15 | 2010-08-04 | 索尼公司 | Semiconductor device and manufacturing method thereof |
| CN101877341A (en) * | 2009-04-29 | 2010-11-03 | 国际商业机器公司 | Reworkable electronic device assembly and method |
| CN107342747A (en) * | 2017-06-27 | 2017-11-10 | 华进半导体封装先导技术研发中心有限公司 | SAW device wafer-thin encapsulating structure and its manufacture method |
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