JPH1117307A - Semiconductor device packaging structure - Google Patents
Semiconductor device packaging structureInfo
- Publication number
- JPH1117307A JPH1117307A JP9169772A JP16977297A JPH1117307A JP H1117307 A JPH1117307 A JP H1117307A JP 9169772 A JP9169772 A JP 9169772A JP 16977297 A JP16977297 A JP 16977297A JP H1117307 A JPH1117307 A JP H1117307A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- connection
- guide pins
- guide
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3447—Lead-in-hole components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置の実装構
造に関し、特に半導体パッケージの底面に多数の接続端
子を有する半導体装置の実装構造に関する。The present invention relates to a semiconductor device mounting structure, and more particularly to a semiconductor device mounting structure having a large number of connection terminals on the bottom surface of a semiconductor package.
【０００２】[0002]
【従来の技術】近年の半導体装置の高集積化に伴い、半
導体パッケージに設けられる外部接続用の端子の数も増
大される傾向にある。このような高集積化された半導体
装置においては、接続端子を半導体パッケージの底面に
格子状に配列したＰＧＡ（PinGrid Array) 型半導体装
置や、ＢＧＡ（Ball Grid Array ）型半導体装置が提案
されており、半導体装置プリント基板上に実装したとき
に、半導体装置のパッケージの底面において前記接続端
子がプリント基板に設けられたパッドに接続される構成
とされている。この場合、ＰＧＡ型半導体装置では、パ
ッケージの底面から突出されている接続ピンをプリント
基板に設けた孔に挿通させた上で半田により接続を行っ
ている。また、ＢＧＡ型半導体装置では、パッケージの
底面に配設された半田バンプをプリント基板に設けたパ
ッドに半田付けして接続を行っている。2. Description of the Related Art With the recent increase in the degree of integration of semiconductor devices, the number of external connection terminals provided on a semiconductor package tends to increase. In such a highly integrated semiconductor device, a PGA (Pin Grid Array) type semiconductor device and a BGA (Ball Grid Array) type semiconductor device in which connection terminals are arranged in a lattice pattern on the bottom surface of a semiconductor package have been proposed. When mounted on a semiconductor device printed board, the connection terminals are connected to pads provided on the printed board on the bottom surface of the package of the semiconductor device. In this case, in the PGA type semiconductor device, connection is performed by soldering after connecting pins projecting from the bottom surface of the package are inserted into holes provided in the printed circuit board. In the BGA type semiconductor device, solder bumps provided on the bottom surface of the package are connected to pads provided on a printed circuit board by soldering.
【０００３】[0003]
【発明が解決しようとする課題】このようなＰＧＡ型半
導体装置やＢＧＡ型半導体装置では、前記したように半
導体装置の実装時に、接続ピンや半田バンプ等の接続端
子がパッケージの下側に隠れてしまうため、半導体装置
を実装したときに各接続端子が正しくプリント基板に接
続されているのかを観察することができない。このた
め、接続用の半田が溶融されて隣接する接続ピンや半田
バンプと短絡してしまうこともあり、実装に際しての半
田の溶融を厳しく管理する必要があり、実装が難しいも
のとなっている。また、一旦実装した半導体装置をプリ
ント基板から取り外す際には、全ての接続ピンや半田バ
ンプにおける半田を溶融させるためにプリント基板を加
熱する必要があり、プリント基板に実装されている他の
電子部品、特に耐熱性の低い電子部品にダメージを与え
てしまうことがある。In such a PGA type semiconductor device or BGA type semiconductor device, as described above, when mounting the semiconductor device, connection terminals such as connection pins and solder bumps are hidden under the package. Therefore, it is not possible to observe whether each connection terminal is correctly connected to the printed circuit board when the semiconductor device is mounted. For this reason, the solder for connection may be melted and short-circuited with adjacent connection pins or solder bumps, and it is necessary to strictly control the melting of the solder at the time of mounting, making mounting difficult. Also, when the semiconductor device once mounted is removed from the printed circuit board, it is necessary to heat the printed circuit board in order to melt the solder on all connection pins and solder bumps, and other electronic components mounted on the printed circuit board are required. In particular, it may damage electronic components having particularly low heat resistance.
【０００４】本発明の目的は、パッケージの底面に隠さ
れる接続端子におけるプリント基板との接続の信頼性を
高めるとともに、実装作業及び半導体装置の取り外しを
容易に行うことを可能にした半導体装置の実装構造を提
供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to improve the reliability of connection between a connection terminal hidden on the bottom surface of a package and a printed circuit board, and to facilitate the mounting work and the removal of the semiconductor device. It is to provide a structure.
【０００５】[0005]
【課題を解決するための手段】本発明は、底面に接続端
子が配列された半導体装置と、前記半導体装置を実装す
るプリント基板とで構成され、半導体装置にはプリント
基板に対する位置決めを行うためのガイドピンが設けら
れ、またプリント基板には前記ガイドピンを案内するた
めのガイドホールと、前記接続端子に接触されて電気接
続される接続パッドとが設けられていることを特徴とす
る。前記接続端子は、半球状または球状に突出形成され
た導電バンプで構成され、前記接続パッドは前記導電バ
ンプの外形に対応した球面状に凹設された導電膜で形成
されることが好ましい。また、前記半導体装置は矩形の
パッケージを有し、このパッケージの底面の四隅にガイ
ドピンが突出形成され、前記プリント基板には前記ガイ
ドピンが挿入されるガイドホールが開口され、前記ガイ
ドピンは前記ガイドホールにろう付けされる構成である
ことが好ましい。SUMMARY OF THE INVENTION The present invention comprises a semiconductor device having connection terminals arranged on a bottom surface thereof, and a printed circuit board on which the semiconductor device is mounted. Guide pins are provided, and the printed circuit board is provided with guide holes for guiding the guide pins, and connection pads that are in contact with the connection terminals and are electrically connected. It is preferable that the connection terminal is formed of a conductive bump formed in a hemispherical or spherical shape, and the connection pad is formed of a conductive film that is concavely formed in a spherical shape corresponding to the outer shape of the conductive bump. Further, the semiconductor device has a rectangular package, and guide pins are formed at four corners of a bottom surface of the package, and a guide hole for inserting the guide pins is formed in the printed circuit board. It is preferable that the structure is brazed to the guide hole.
【０００６】[0006]
【発明の実施の形態】次に、本発明の実施形態を図面を
参照して説明する。図１は本発明をＢＧＡ型半導体装置
に適用した実施形態を示す図であり、同図（ａ）は正面
方向の断面図、（ｂ）はその底面図である。ＢＧＡ型半
導体装置１は、ベース２上にＩＣチップ３が搭載され、
ベース２の上面に形成された配線４にボンディングワイ
ヤ５により電気接続される。また、前記ベース２の下面
には格子状に電極パッド６が配設されており、各電極パ
ッド６には半球状をした金属バンプ７、例えば、銅やア
ルミニウム等の金属バンプが形成されている。また、前
記ベース２の下面の四隅位置には、それぞれガイドピン
８が突出されている。そして、前記ベース２を厚さ方向
に貫通するスルーホール９が設けられ、このスルーホー
ル９によって前記ベース２の上面の配線４と下面の電極
パッド６とがそれぞれ電気接続されている。さらに、前
記ベース２の上面には、前記ＩＣチップ３やボンディン
グワイヤ５を覆うキャップ１０が被せられ、内部が封止
されている。Next, embodiments of the present invention will be described with reference to the drawings. 1A and 1B show an embodiment in which the present invention is applied to a BGA type semiconductor device. FIG. 1A is a cross-sectional view in the front direction, and FIG. 1B is a bottom view thereof. The BGA type semiconductor device 1 has an IC chip 3 mounted on a base 2,
It is electrically connected to a wiring 4 formed on the upper surface of the base 2 by a bonding wire 5. On the lower surface of the base 2, electrode pads 6 are arranged in a grid pattern, and each electrode pad 6 is formed with a hemispherical metal bump 7, for example, a metal bump made of copper, aluminum, or the like. . Further, guide pins 8 project from four corners of the lower surface of the base 2. A through hole 9 penetrating the base 2 in the thickness direction is provided, and the through hole 9 electrically connects the wiring 4 on the upper surface of the base 2 and the electrode pad 6 on the lower surface. Further, a cap 10 covering the IC chip 3 and the bonding wires 5 is put on the upper surface of the base 2 to seal the inside.
【０００７】一方、図２（ａ），（ｂ）は前記半導体装
置１を実装するためのプリント基板１１の平面図と断面
図であり、その絶縁基板１２の表面には前記４本のガイ
ドピン８が挿入可能なガイドホール１３が開設されてい
る。また、これらガイドホール１３で囲まれる領域に
は、前記金属バンプ７に対応して格子状に配列された接
続パッド１４が形成されている。ここで、前記接続パッ
ド１４は、前記絶縁基板１２の表面に半球に近い形状の
凹部１５が形成され、この凹部１５を含む絶縁基板１２
の表面にそれぞれ金属膜１６が形成された構成とされて
いる。このような構成のプリント基板１は、例えば、フ
ォトリソグラフィ技術を利用して形成しており、図示は
省略するが、絶縁基板１２の表面に格子状の窓を有する
マスクを形成した上で、絶縁基板１２の表面を等方性エ
ッチングして半球状の凹部１５を形成する。その後、全
面に金属薄膜を形成し、さらにその上に前記マスクを利
用して露光を行って形成したフォトレジストマスクを用
いてこの金属薄膜をエッチングして前記金属膜１６を形
成すればよい。なお、この金属膜１６の一部は前記ガイ
ドホール１３部位にも形成されている。2 (a) and 2 (b) are a plan view and a sectional view of a printed circuit board 11 for mounting the semiconductor device 1, and the four guide pins are provided on the surface of an insulating substrate 12. A guide hole 13 into which a hole 8 can be inserted is provided. In regions surrounded by the guide holes 13, connection pads 14 arranged in a lattice pattern corresponding to the metal bumps 7 are formed. Here, the connection pad 14 has a recess 15 having a shape close to a hemisphere formed on the surface of the insulating substrate 12.
And a metal film 16 is formed on each surface. The printed circuit board 1 having such a configuration is formed by using, for example, a photolithography technique, and although not shown, a mask having a lattice-shaped window is formed on the surface of the insulating substrate 12, and then the insulating substrate 12 is formed. The surface of the substrate 12 is isotropically etched to form a hemispherical concave portion 15. Then, a metal thin film is formed on the entire surface, and the metal thin film is etched by using a photoresist mask formed by performing exposure using the mask thereon. A part of the metal film 16 is also formed at the guide hole 13.
【０００８】このように構成された半導体装置１を前記
プリント基板１１に実装する際には、図３に示すよう
に、プリント基板１１のガイドホール１３に半導体装置
１のガイドピン８を挿通し、このガイドピン８をガイド
ホール１３の金属膜１６において半田１７により接続す
る。このとき、半導体装置１をプリント基板１１に強く
押圧した状態で半田付けを行う。この半田付けにより、
半導体装置１の金属バンプ７はプリント基板１１の接続
パッド１４に押圧され、この接続パッド１４において表
面の金属膜１６に当接される。したがって、金属バンプ
７と金属膜１６は押圧力によって接触状態となり、相互
に電気接続されることなる。なお、このとき押圧力の強
さによっては、金属バンプ７と金属膜１７の表面が幾分
押し潰され、両者がより密接状態となり、良好な接続状
態となる。When mounting the semiconductor device 1 thus configured on the printed board 11, the guide pins 8 of the semiconductor device 1 are inserted into the guide holes 13 of the printed board 11 as shown in FIG. The guide pins 8 are connected to the metal film 16 of the guide hole 13 by solder 17. At this time, soldering is performed while the semiconductor device 1 is strongly pressed against the printed circuit board 11. By this soldering,
The metal bumps 7 of the semiconductor device 1 are pressed by the connection pads 14 of the printed board 11, and the connection pads 14 contact the metal film 16 on the surface. Therefore, the metal bump 7 and the metal film 16 are brought into contact with each other by the pressing force, and are electrically connected to each other. At this time, depending on the strength of the pressing force, the surfaces of the metal bump 7 and the metal film 17 are slightly crushed, and the two are brought into a closer contact state, resulting in a good connection state.
【０００９】したがって、この実装構造では、半導体装
置１の４本のガイドピン８に対して半田付けを行うのみ
で実装が完成されることになり、実装を容易に行うこと
ができる。そして、実装された半導体装置１では、金属
バンプ７と金属膜１６との接触のみであるため、溶融半
田によって隣接する接続端子間での短絡が生じるような
こともなく、信頼性が向上される。これにより、より高
密度な端子配列が可能となり、半導体装置の高集積化に
有利となる。さらに、一旦実装した半導体装置１をプリ
ント基板１１から取り外す際には、ガイドピン８を接続
している半田１７を溶融して取り外せばよく、多数個の
金属バンプにおける取り外しは不要であるため、極めて
容易に取り外しが可能となる。Therefore, in this mounting structure, the mounting is completed only by soldering to the four guide pins 8 of the semiconductor device 1, and the mounting can be easily performed. In the mounted semiconductor device 1, there is only contact between the metal bump 7 and the metal film 16, so that short circuit does not occur between adjacent connection terminals due to the molten solder, and the reliability is improved. . As a result, a higher-density terminal arrangement can be achieved, which is advantageous for high integration of a semiconductor device. Further, when the semiconductor device 1 once mounted is removed from the printed circuit board 11, the solder 17 connecting the guide pins 8 may be melted and removed, and it is not necessary to remove a large number of metal bumps. It can be easily removed.
【００１０】ここで、半導体装置１に形成される金属バ
ンプ７の径寸法は、プリント基板１１に形成される接続
パッド１４の凹状球面をした金属膜１６の径寸法に等し
く形成すれば、金属バンプ７と金属膜１６とがほぼ全面
で接触され、接触抵抗の小さな接続が実現できる。ま
た、両者の寸法が必ずしも一致しなくとも、前記したよ
うに金属ハンプ７と金属膜１６の表面での潰れにより、
両者を密接して良好な接触状態を得ることも可能であ
る。さらに、金属バンプ７や金属膜１６は必ずしも金属
で形成される必要はなく、導電バンプおよび導電膜とし
て弾力性のある素材を用いれば、両者を弾性力を利用し
て接触させることができ、好適な接続を得ることができ
る。Here, if the diameter of the metal bump 7 formed on the semiconductor device 1 is equal to the diameter of the metal film 16 having the concave spherical surface of the connection pad 14 formed on the printed circuit board 11, the metal bump 7 can be formed. 7 and the metal film 16 are almost in contact with each other, and a connection with low contact resistance can be realized. Further, even if the two dimensions do not always match, as described above, the metal hump 7 and the metal film 16 are crushed on the surface,
It is also possible to obtain a good contact state by bringing both into close contact. Further, the metal bumps 7 and the metal film 16 do not necessarily need to be formed of metal. If an elastic material is used for the conductive bumps and the conductive film, they can be brought into contact with each other by utilizing elastic force. Connection can be obtained.
【００１１】なお、本発明における半導体装置に設けら
れる導電バンプの形状は、角錐状、紡錘状等、適宜の形
状変更は可能であり、導電膜の凹部形状もこれに対応し
て適宜の形状変更は可能である。また、本発明ではＰＧ
Ａ型半導体装置においても、各接続端子としての接続ピ
ンの長さを短めに形成し、かつプリント基板にはこの接
続ピンを受け入れるための微小な凹部を形成して接続パ
ッドを形成することで、前記実施形態と同様に本発明を
実現することが可能である。The shape of the conductive bumps provided on the semiconductor device according to the present invention can be appropriately changed such as a pyramid shape or a spindle shape, and the concave shape of the conductive film is changed accordingly. Is possible. In the present invention, PG
Also in the A-type semiconductor device, the length of the connection pin as each connection terminal is formed short, and the connection pad is formed by forming a minute concave portion for receiving the connection pin on the printed circuit board. The present invention can be realized in the same manner as in the above embodiment.
【００１２】[0012]
【発明の効果】以上説明したように本発明は、半導体装
置に設けたガイドピンをプリント基板のガイドホールに
案内させた状態で、半導体装置に設けた接続端子をプリ
ント基板に設けた接続パッドに接触させてその実装を行
う構成であり、半導体装置をプリント基板に実装する際
には、ガイドピンをろう付けすればよく、多数の接続端
子をろう付けする必要はない。このため、ろう付けする
箇所が少なくてすみ、実装作業が容易であるとともに、
隣接する接続端子や接続パッドでのろう材の溶融による
短絡が生じることはない。また、半導体装置を取り外す
場合にも、ガイドピンのろう付けを取り外すだけでよ
く、容易に取り外すことができる。As described above, according to the present invention, the connection terminals provided on the semiconductor device are connected to the connection pads provided on the printed circuit board while the guide pins provided on the semiconductor device are guided in the guide holes of the printed circuit board. The mounting is performed by contacting the semiconductor devices. When mounting the semiconductor device on a printed circuit board, the guide pins may be brazed, and it is not necessary to braze a large number of connection terminals. For this reason, there are few places to braze, mounting work is easy,
No short circuit occurs due to melting of the brazing material at the adjacent connection terminals or connection pads. Also, when removing the semiconductor device, it is only necessary to remove the brazing of the guide pin, and the semiconductor device can be easily removed.
【図１】本発明にかかる半導体装置の正面方向の断面図
と底面図である。FIG. 1 is a front sectional view and a bottom view of a semiconductor device according to the present invention.
【図２】本発明にかかるプリント基板の平面図と断面図
である。FIG. 2 is a plan view and a sectional view of a printed circuit board according to the present invention.
【図３】半導体装置をプリント基板に実装した状態の断
面図である。FIG. 3 is a cross-sectional view illustrating a state where the semiconductor device is mounted on a printed circuit board.
１ 半導体装置 ２ ベース ３ ＩＣチップ ７ 金属バンプ ８ ガイドピン ９ スルーホール １１ プリント基板 １２ 絶縁基板 １３ ガイドホール １４ 接続パッド １６ 金属膜 １７ 半田 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Base 3 IC chip 7 Metal bump 8 Guide pin 9 Through hole 11 Printed circuit board 12 Insulating substrate 13 Guide hole 14 Connection pad 16 Metal film 17 Solder
Claims (4)
と、前記半導体装置を実装するプリント基板とで構成さ
れ、前記半導体装置には前記プリント基板に対する位置
決めを行うためのガイドピンが設けられ、前記プリント
基板には前記ガイドピンを案内するためのガイドホール
と、前記接続端子に接触されて電気接続される接続パッ
ドとが設けられていることを特徴とする半導体装置の実
装構造。1. A semiconductor device having connection terminals arranged on a bottom surface, and a printed circuit board on which the semiconductor device is mounted, wherein the semiconductor device is provided with guide pins for positioning the semiconductor device with respect to the printed circuit board. The mounting structure of a semiconductor device, wherein the printed board is provided with a guide hole for guiding the guide pin and a connection pad that is electrically connected to the connection terminal.
出形成された導電バンプで構成され、前記接続パッドは
前記導電バンプの外形に対応した球面状に凹設された導
電膜で形成される請求項１に記載の半導体装置の実装構
造。2. The connection terminal is formed of a conductive bump protruding in a hemispherical or spherical shape, and the connection pad is formed of a conductive film concaved in a spherical shape corresponding to the outer shape of the conductive bump. A mounting structure for the semiconductor device according to claim 1.
う付けされる構成である請求項１または２に記載の半導
体装置の実装構造。3. The mounting structure for a semiconductor device according to claim 1, wherein the guide pins are brazed to the guide holes.
し、前記接続端子はこのパッケージの底面に配設され、
かつ前記ガイドピンはこのパッケージの底面の四隅に突
出形成される請求項３に記載の半導体装置の実装構造。4. The semiconductor device has a rectangular package, and the connection terminals are disposed on a bottom surface of the package.
4. The semiconductor device mounting structure according to claim 3, wherein said guide pins are formed to project from four corners of a bottom surface of said package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9169772A JP3055496B2 (en) | 1997-06-26 | 1997-06-26 | Semiconductor device mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9169772A JP3055496B2 (en) | 1997-06-26 | 1997-06-26 | Semiconductor device mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1117307A true JPH1117307A (en) | 1999-01-22 |
| JP3055496B2 JP3055496B2 (en) | 2000-06-26 |
Family
ID=15892585
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9169772A Expired - Fee Related JP3055496B2 (en) | 1997-06-26 | 1997-06-26 | Semiconductor device mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3055496B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6806562B2 (en) | 2001-01-25 | 2004-10-19 | Infineon Technologies Ag | Device with at least one semiconductor component and a printed circuit board and method of establishing an electromechanical connection between the two |
| KR101006619B1 (en) | 2008-10-20 | 2011-01-07 | 삼성전기주식회사 | A printed circuit board comprising a round solder bump and a method of manufacturing the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102650478B1 (en) * | 2018-12-14 | 2024-03-25 | 에이지씨 가부시키가이샤 | Method for Preparing Coated Textile for Supporting Glass Base Plate |
-
1997
- 1997-06-26 JP JP9169772A patent/JP3055496B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6806562B2 (en) | 2001-01-25 | 2004-10-19 | Infineon Technologies Ag | Device with at least one semiconductor component and a printed circuit board and method of establishing an electromechanical connection between the two |
| KR101006619B1 (en) | 2008-10-20 | 2011-01-07 | 삼성전기주식회사 | A printed circuit board comprising a round solder bump and a method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3055496B2 (en) | 2000-06-26 |
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