JPS58124260A - Circuit board - Google Patents

Circuit board

Info

Publication number
JPS58124260A
JPS58124260A JP57007279A JP727982A JPS58124260A JP S58124260 A JPS58124260 A JP S58124260A JP 57007279 A JP57007279 A JP 57007279A JP 727982 A JP727982 A JP 727982A JP S58124260 A JPS58124260 A JP S58124260A
Authority
JP
Japan
Prior art keywords
wiring
channel
substrate
rows
columns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57007279A
Other languages
Japanese (ja)
Inventor
Yoneo Funo
布野　米雄
Noriaki Hyodo
兵頭　典明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57007279A priority Critical patent/JPS58124260A/en
Publication of JPS58124260A publication Critical patent/JPS58124260A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To perform the high density of a circuit board without decreasing the wiring property by forming different channel capacities of wiring regions formed between integrated circuit chips depending upon the positions on the substrate. CONSTITUTION:An internal wiring region 2 is formed on the substrate 1, and an integrated circuit chip 3 is arranged in the region 2. The chips 3 are placed on m rows and n columns array in such a manner that the intervals between the rows and the columns are set wide at the center of the substrate 1 and narrow at the periphery, thereby forming the capacity of the wiring channel 4 more at the center and less at the periphery. When the different wiring channel capacities are formed at the positions on the substrate, the channel capacities Bi of the substrate can be set corresponding to the channel capacity Ci necessary for the wiring pattern with slight margin. As a result, the demand cap of the channel capacities between the center and the periphery can be largely improved.

Description

【発明の詳細な説明】 本発明は、集積回路チップ′ｔｍ行ｎ列のアレイ状に搭
載して成る配線基板の配線チャネルに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wiring channel of a wiring board having integrated circuit chips mounted in an array of m rows and n columns.

従来、この種の基板の配線チャネル容量は、第１図に示
すように、集積回路チップ３の行間及び列間は、基板１
上のどの位置も尋しく設定しである。しかし、実際の配
線作業において必要とするチャネル容量は、行間及び列
間の位ｋＫより異なり、一般には、基板１の中央部付近
はど多く必要とする。従って、行間１列間のチャネル容
置が一定だと、上記中央部付近のチャネル不足による配
線性の低下、或いは周辺部のチャネルに未使用部分が生
じ、結果としてチャネルが有効に活用されなくなると込
う欠点があった。Conventionally, the wiring channel capacitance of this type of substrate is as shown in FIG.
Every position above is set in a strange way. However, the channel capacitance required in actual wiring work differs depending on the distance kK between rows and columns, and generally a large amount is required near the center of the substrate 1. Therefore, if the channel capacity between rows and columns is constant, wiring performance will deteriorate due to the lack of channels near the center, or unused portions will occur in the peripheral areas, resulting in the channels not being used effectively. There were some drawbacks.

本発明の目的は、ｍ行ｎ列のアレイ状に搭載された集積
回路チップの行間及び列間に形成される配線領域のチャ
ネル容ｉｔを行間１列間位ｔＫよシ異ならせることによ
り、上記欠点を解決し、配線性の向上した基板を提供す
る事にある。An object of the present invention is to make the channel capacity it of the wiring region formed between the rows and columns of integrated circuit chips mounted in an array of m rows and n columns different by the distance tK between the rows and one column. The purpose is to solve the drawbacks and provide a board with improved wiring performance.

即ち、本発明は、集積回路チップがｍ行ｎ列のアレイ状
に搭載される配線基板において、上記集積回路チップの
行間及び列間の間隔を基板上の位置に対応して異ならし
め、これらの行間及び列間に形成される配線領域の配線
チャネル容量を基板上の位置により異ならしめるよう構
成して成るものである。That is, the present invention provides a wiring board on which integrated circuit chips are mounted in an array of m rows and n columns, in which the intervals between the rows and columns of the integrated circuit chips are made to vary depending on the position on the board, and these The wiring channel capacitance of wiring regions formed between rows and columns is configured to vary depending on the position on the substrate.

以下、本発明配線基板の実施例を図面に基づいて説明す
る。Embodiments of the wiring board of the present invention will be described below based on the drawings.

第２図は本発明配線基板の一実施例を示す平面図である
。FIG. 2 is a plan view showing an embodiment of the wiring board of the present invention.

本実施例は、高密度を要求される多層配線基板に適用し
たもので、斯かる基板では、パターンの収容量を向上す
るため、一つの層内では配線パターンは特定の一方向（
Ｘ方向）にのみ設けられ、他の層では上記と直角の方向
（Ｙ方向）にのみ設けて、必要とする２点間の配線は、
これらＸ−Ｙ方向の直線配線の組合せで行なわれる。方
向転換する場合には、スルーホール等により一方の層か
ら他の層への接続が行なわれる。This example is applied to a multilayer wiring board that requires high density. In such a board, in order to improve the capacity of the pattern, the wiring pattern is arranged in one specific direction (
(X direction), and in other layers only in the direction perpendicular to the above (Y direction), the required wiring between two points is
This is done by a combination of these straight line wirings in the X-Y directions. In the case of a change in direction, connections are made from one layer to the other by through holes or the like.

上記基板１には、内部配線領域２が設けてあり、該領域
２内に集積回路チップ３が配設しである。The substrate 1 is provided with an internal wiring area 2, and an integrated circuit chip 3 is disposed within the area 2.

この集積回路チップ３は、ｍ行ｎ列のアレイ状に搭載さ
れ、その行間及び列間の間隔を基板１の中央部で広く、
周辺部で狭くなるように設定して、配線チャネル４の容
量を、中央部に多く、周辺部に少なく配分している。The integrated circuit chips 3 are mounted in an array of m rows and n columns, and the intervals between the rows and columns are wide at the center of the substrate 1.
The capacitance of the wiring channel 4 is set to be narrower at the periphery, and the capacitance of the wiring channel 4 is distributed more to the center and less to the periphery.

今、一つの層に注目し、配線パターンと直角方向にみた
時の配線基板の持つチャネル容量Ｂｉ　と配線パターン
が必要とするチャネル容量ＣＩ　との関係を第３図に示
す。第３図は、配線チャネル容量が基板上どこも一様々
従来技術による配線基板の例を示している。もし、Ｂ≧
Ｃｍａｘなら配線性は良いが、周辺部には有効に活用さ
れないチャネルが残るため、結果として基板は必要以上
に大きな形状となり、高密度化に反することに々る。逆
に、ＢくＣｍａｘならば中央部でチャネル不足が生じ、
配線性の低下を引き起すため、これも置密度化に反する
ことになる。Now, focusing on one layer, FIG. 3 shows the relationship between the channel capacitance Bi of the wiring board and the channel capacitance CI required by the wiring pattern when viewed in a direction perpendicular to the wiring pattern. FIG. 3 shows an example of a prior art wiring board in which the wiring channel capacitance is uniform throughout the board. If B≧
If Cmax is used, wiring performance is good, but channels that are not effectively utilized remain in the peripheral area, resulting in a board that is larger than necessary, which often goes against the grain of high density. Conversely, if B is Cmax, there will be a lack of channels in the center,
Since this causes a decrease in wiring performance, this also goes against increasing the layout density.

これに対し、本発明のように配線チャネル容量を基板上
の位置により異なるようにす、れば、第４図に示すよう
に、基板の持つチャネル容量Ｂｉ　を、若干の余裕を持
って配線パターンが必要とするチャネル容量Ｃ１に対応
させて設定できる。その結果、中央部と周辺部のチャネ
ル容量の需給ギャップを大幅に改善することができ、配
線性の低下をきたすことがない。　　、 以上説明したように、本発明は、集積回路チップ間に形
成される配線領域のチャネル容祉金、基板上の位置によ
り異ならしめることにより、配線性の低下をきたすこと
なく高密度化を実現できる効果がある。On the other hand, if the wiring channel capacitance is made to differ depending on the position on the board as in the present invention, as shown in FIG. can be set in accordance with the channel capacity C1 required. As a result, the gap between demand and supply of channel capacity between the center and the periphery can be significantly improved, without deteriorating the wiring performance. As explained above, the present invention realizes high density without deteriorating wiring performance by varying the channel thickness of the wiring area formed between integrated circuit chips and its position on the substrate. There is an effect that can be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の配線基板を示す平面図、第２図は本発明
配線基板の一実施例を示す平面図、第３図は従来の配線
基板におけるチャネル容量と配線パターンが必要とする
チャネル容量との関係を示すグラフ、第４図は本発明配
線基板におけるチャネル容量と配線パターンが必要とす
るチャネル容量との関係を示すグラフである。 １・・・配線基板　　　　２・・・内部配線領域３・・
・集積回路チップ　４・・・配線チャネルＢｉ・・・基
板の持つチャネル容量 Ｃ１・・・配線パターンが必要とするチャネル容量出願
人　　日本電気株式会社 第１図 第２図 第３図 第４図 ナマネ）しFig. 1 is a plan view showing a conventional wiring board, Fig. 2 is a plan view showing an embodiment of the wiring board of the present invention, and Fig. 3 is a plan view showing the channel capacitance in the conventional wiring board and the channel capacitance required by the wiring pattern. FIG. 4 is a graph showing the relationship between the channel capacitance in the wiring board of the present invention and the channel capacitance required by the wiring pattern. 1... Wiring board 2... Internal wiring area 3...
・Integrated circuit chip 4...Wiring channel Bi...Channel capacitance of the board C1...Channel capacity required by the wiring pattern Applicant: NEC Corporation Figure 1 Figure 2 Figure 3 Figure 4 Namane )death

Claims (2)

【特許請求の範囲】[Claims] （１）集積回路チップがｍ行ｎ列のアレイ状に搭載され
る配線基板において、 上記集積回路チップの行間及び列間の間隔を基板上の位
置に対応して異ならしめ、これらの行間及び列間に形成
される配線領域の配線チャネル容置を基板上の位置によ
り異ならしめるよう構成したことを特徴とする配線基板
。(1) In a wiring board on which integrated circuit chips are mounted in an array of m rows and n columns, the intervals between the rows and columns of the integrated circuit chips are varied depending on the position on the board, and the intervals between these rows and columns are changed. 1. A wiring board, characterized in that the wiring channel capacity of the wiring area formed between the wiring areas is configured to vary depending on the position on the board. （２）上記配線領域の配線チャネル容量を、基板の中央
部に多く、周辺部に少々く配分した上記第１項記載の配
線基板。(2) The wiring board according to item 1 above, wherein the wiring channel capacitance of the wiring region is distributed more to the center of the board and less to the peripheral part.
JP57007279A 1982-01-20 1982-01-20 Circuit board Pending JPS58124260A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57007279A JPS58124260A (en) 1982-01-20 1982-01-20 Circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57007279A JPS58124260A (en) 1982-01-20 1982-01-20 Circuit board

Publications (1)

Publication Number Publication Date
JPS58124260A true JPS58124260A (en) 1983-07-23

Family

ID=11661583

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57007279A Pending JPS58124260A (en) 1982-01-20 1982-01-20 Circuit board

Country Status (1)

Country Link
JP (1) JPS58124260A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0644596A1 (en) * 1993-09-21 1995-03-22 Fujitsu Limited Method for multi-layer printed wiring board design
JPH08298264A (en) * 1995-04-27 1996-11-12 Hitachi Ltd Electronic circuit device
JP2008110324A (en) * 2006-10-31 2008-05-15 Figla Co Ltd Heater dispenser and heater dispenser vessel

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5508938A (en) * 1992-08-13 1996-04-16 Fujitsu Limited Special interconnect layer employing offset trace layout for advanced multi-chip module packages
EP0644596A1 (en) * 1993-09-21 1995-03-22 Fujitsu Limited Method for multi-layer printed wiring board design
JPH08298264A (en) * 1995-04-27 1996-11-12 Hitachi Ltd Electronic circuit device
JP2008110324A (en) * 2006-10-31 2008-05-15 Figla Co Ltd Heater dispenser and heater dispenser vessel

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