JPH0624220B2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH0624220B2
JPH0624220B2 JP1198338A JP19833889A JPH0624220B2 JP H0624220 B2 JPH0624220 B2 JP H0624220B2 JP 1198338 A JP1198338 A JP 1198338A JP 19833889 A JP19833889 A JP 19833889A JP H0624220 B2 JPH0624220 B2 JP H0624220B2
Authority
JP
Japan
Prior art keywords
wiring layer
connection hole
wiring
connection
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1198338A
Other languages
Japanese (ja)
Other versions
JPH0277139A (en
Inventor
幸広 牛久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP1198338A priority Critical patent/JPH0624220B2/en
Publication of JPH0277139A publication Critical patent/JPH0277139A/en
Publication of JPH0624220B2 publication Critical patent/JPH0624220B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor device.

(従来の技術) 近年の半導体製造技術の向上は目覚しく、特に半導体装
置上の配線においては、2層から3層、更に4層以上の
多層化が実現されるに至っている。しかし、一方では配
線層の増加に伴い半導体表面の段差形状が益々複雑化し
ており、断線を含む配線特性の劣化や信頼性の低下等の
問題が表面化している。特に、所望の配線層間を接続す
るための接続孔に関しては、従来出来るだけ大きく開口
するのが一般的であり、かつ有利であると考えられてい
たが、このような接続孔では以下に述べるような不都合
があった。
(Prior Art) In recent years, semiconductor manufacturing technology has been remarkably improved, and in particular, in wiring on a semiconductor device, multi-layering of two to three layers and four or more layers has been realized. However, on the other hand, as the number of wiring layers increases, the stepped shape of the semiconductor surface becomes more and more complicated, and problems such as deterioration of wiring characteristics including disconnection and deterioration of reliability have come to the surface. In particular, with regard to connection holes for connecting desired wiring layers, it has been generally considered that it is common and advantageous to open the connection holes as large as possible in the past. There was an inconvenience.

第1図は従来の半導体装置の要部の構造を示す平面図
で、第2図は第1図の矢視A−A断面を示す図である。
図中1は半導体基板で、この基板1の表面には第1の配
線層としての拡散層2が形成されている。半導体基板1
上には第1の絶縁層3が設けられ、この絶縁層3の拡散
層2上には接続孔4が開孔されている。絶縁層3上には
Al膜からなる第2の配線層5が設けられており、この
配線層5は接続孔4を介して拡散層2と接続されてい
る。
FIG. 1 is a plan view showing a structure of a main part of a conventional semiconductor device, and FIG. 2 is a view showing a cross section taken along the line AA of FIG.
In the figure, reference numeral 1 denotes a semiconductor substrate, and a diffusion layer 2 as a first wiring layer is formed on the surface of the substrate 1. Semiconductor substrate 1
A first insulating layer 3 is provided on the upper side, and a connection hole 4 is opened on the diffusion layer 2 of the insulating layer 3. A second wiring layer 5 made of an Al film is provided on the insulating layer 3, and the wiring layer 5 is connected to the diffusion layer 2 via the connection hole 4.

ここで、接続孔4を拡散層2と配線層5との間の接続を
確実にするため拡散層2、配線層5の重なる領域で比較
的大きく、かつ、配線層5の長さ方向に長く形成されて
いる。
Here, in order to ensure the connection between the diffusion layer 2 and the wiring layer 5, the connection hole 4 is relatively large in the region where the diffusion layer 2 and the wiring layer 5 overlap and is long in the length direction of the wiring layer 5. Has been formed.

また、第1の絶縁層3及び2の配線層5上には、第2の
絶縁層6を介してAl膜からなる第3の配線層7が設け
られている。なお、この第3の配線層7は第1の配線層
5と交差する関係に形成され、かつ前記接続孔4上を通
過している。
A third wiring layer 7 made of an Al film is provided on the first insulating layers 3 and 2 and the wiring layer 5 with a second insulating layer 6 interposed therebetween. The third wiring layer 7 is formed so as to intersect with the first wiring layer 5 and passes over the connection hole 4.

(発明が解決しようとする課題) このような構成では、第3の配線層7は、第1の絶縁層
3の表面形状に起因する第2の絶縁層6の段差により、
絶縁層6への被覆性が悪くなり、段差部においてその膜
厚が極めて薄くなる。このため、第3の配線層7の段切
れや配線抵抗増大等の配線特性の劣化を招き、またマイ
グレーション等による信頼性低下を招くと言う問題があ
った。
(Problems to be Solved by the Invention) In such a configuration, the third wiring layer 7 is formed by the step difference of the second insulating layer 6 due to the surface shape of the first insulating layer 3.
The insulating layer 6 is poorly covered, and the film thickness becomes extremely thin at the step portion. Therefore, there is a problem that the wiring characteristics are deteriorated such as disconnection of the third wiring layer 7 and the wiring resistance is increased, and the reliability is lowered due to migration or the like.

なお、上述した問題は第3の配線層7の幅よりも接続孔
4の長手方向の方が長く、配線層7が接続孔4にて完全
に横切られるために生じるものであり、これを避けるた
めには接続孔4を配線層7の幅より短く形成すればよ
い。しかしながら、この場合には接続孔4の面積が狭く
なり、拡散層2と第2の配線層5との接続が不確実とな
るため、好ましくない。
The above-mentioned problem occurs because the length of the connection hole 4 in the longitudinal direction is longer than the width of the third wiring layer 7 and the wiring layer 7 is completely crossed by the connection hole 4, which is avoided. For this purpose, the connection hole 4 may be formed shorter than the width of the wiring layer 7. However, in this case, the area of the connection hole 4 becomes small, and the connection between the diffusion layer 2 and the second wiring layer 5 becomes uncertain, which is not preferable.

本発明の目的は、配線層が接続孔上の段差を通過するこ
とに起因する該配線僧の段切れや抵抗増大化等を未然に
防止することができ、配線特性及び信頼性の向上をはか
り得る半導体装置を提供することにある。
An object of the present invention is to prevent disconnection of the wiring monastery, increase in resistance, etc. due to a wiring layer passing through a step on a connection hole, and to improve wiring characteristics and reliability. It is to provide a semiconductor device to be obtained.

[発明の構成] (課題を解決するための手段) 本発明の半導体第1乃至第3の配線層が絶縁層を挟んで
交互に積層された多層配線構造を有し、第1の配線層と
第2の配線層とが前記絶縁層に設けられた接続孔を通し
て相互接続され、この接続孔上を第3の配線層が通過す
る半導体装であって、この第3の配線層より幅広の前記
接続孔が、前記第3の配線層が通過する領域で、前記第
3の配線層の幅方向に並ぶ複数の接続孔と前記第3の配
線層の通過領域外に設けられた接続孔とに分割されてな
ることを特徴とする。
[Structure of the Invention] (Means for Solving the Problems) The semiconductor first to third wiring layers of the present invention have a multilayer wiring structure in which insulating layers are alternately stacked, A semiconductor device which is interconnected with a second wiring layer through a connection hole provided in the insulating layer, and through which a third wiring layer passes, the semiconductor device being wider than the third wiring layer. In the region where the third wiring layer passes, the connection holes include a plurality of connection holes arranged in the width direction of the third wiring layer and a connection hole provided outside the passage region of the third wiring layer. It is characterized by being divided.

(作用) 上述の構成においては、接続孔の上を通る第3の配線層
が通過する領域で接続孔を複数に分割したことにより、
接続孔上の段差を横切らせていた第3の配線層の一部
が、段差の無い領域(分割された接続孔と接続孔との間
の領域)を通過するようになる。これにより、第3の配
線層の段切れや、抵抗増大化等が防止される。
(Operation) In the above configuration, the connection hole is divided into a plurality of areas in the region where the third wiring layer passing over the connection hole passes,
A part of the third wiring layer, which has crossed the step on the connection hole, passes through the area without the step (the area between the divided connection holes). This prevents disconnection of the third wiring layer, increase in resistance, and the like.

また、第3の配線層より幅広の接続孔を複数に分割する
際に、接続孔を上を通る第3の配線層が通過する領域外
にも分割された接続孔が設けられている。このため、第
3の配線層が通過する領域で接続孔を複数に分割したこ
とに起因する、第1の配線層と第2の配線層との間のコ
ンタクト抵抗の増大という不都合は生じない。
Further, when the connection hole wider than the third wiring layer is divided into a plurality of connection holes, the connection hole is also provided outside the region where the third wiring layer passing above the connection hole passes. Therefore, there is no inconvenience that the contact resistance between the first wiring layer and the second wiring layer increases due to the connection hole being divided into a plurality of portions in the region through which the third wiring layer passes.

即ち、接続孔を介する配線層間の接続特性は、接続孔の
面積のみならず周囲長に依存する。本発明のように第3
の配線層が通過する領域で第3の配線層の幅方向に並ぶ
複数の接続孔と第3の配線層の通過領域外に設けられた
接続孔とに分割すると、面積は狭くなるが、周囲長が増
大するので、接続孔を小分割することによる接続特性の
劣化は殆ど問題とならない。
That is, the connection characteristic between the wiring layers via the connection hole depends not only on the area of the connection hole but also on the peripheral length. Third like the present invention
If a plurality of connection holes arranged in the width direction of the third wiring layer in a region through which the wiring layer passes and a connection hole provided outside the passage region of the third wiring layer are divided, the area becomes smaller, but Since the length is increased, the deterioration of the connection characteristics due to the subdivision of the connection hole hardly poses a problem.

また、接続孔を分割することによるパターンの追加やパ
ターン面積の増大等を招くことがなく、さらに接続孔パ
ターンの分割には、プロセスの変更を伴わうこともな
い。従って、レイアウトやプロセス等の変更なしに、配
線特性および信頼性の向上が図られる。
Further, the addition of a pattern and the increase of the pattern area due to the division of the connection hole are not caused, and further, the division of the connection hole pattern does not involve a process change. Therefore, the wiring characteristics and reliability can be improved without changing the layout or the process.

(実施例) 第3図は本発明の一実施例に係わる半導体装置の要部の
構造を示す平面図である。なお、第1図と同一部分には
同一符号を付して、その詳しい説明は省略する。この実
施例が先に説明した従来例と異なる点は、前記接続孔4
の代わりに複数の接続孔を形成したことである。即ち、
第1の絶縁層3には、第2の配線層5の長さ方向に沿っ
て4個の接続小孔8a,8b,8c,8dが直線状に配
列形成されている。
(Embodiment) FIG. 3 is a plan view showing a structure of a main part of a semiconductor device according to an embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. The difference between this embodiment and the conventional example described above is that the connection hole 4
That is, a plurality of connection holes are formed instead of. That is,
In the first insulating layer 3, four connection small holes 8a, 8b, 8c, 8d are linearly arranged along the length direction of the second wiring layer 5.

ここで、本実施例においては接続孔によって接続される
第1の配線層としての拡散層2と第2の配線層5より上
層側にある第3の配線層7が通過する領域で、この第3
の配線層7より幅広の接続孔が、第3の配線層7の幅方
向に並ぶ接続孔8b,8cと第3の配線層7の通過領域
外に設けられた接続孔8aあるいは接続孔8dとに分割
されていることが重要である。
Here, in this embodiment, in the region where the diffusion layer 2 as the first wiring layer connected by the connection hole and the third wiring layer 7 on the upper side of the second wiring layer 5 pass through, Three
Connection holes wider than the wiring layer 7 are connected to the connection holes 8b and 8c arranged in the width direction of the third wiring layer 7 and the connection hole 8a or the connection hole 8d provided outside the passage area of the third wiring layer 7. It is important to be divided into.

このような構成であれば、第3の配線層7の一部を段差
のない領域を通過させることができる。即ち、第3図の
孔8cを通る矢視B−B断面では、第2図に示す如く第
3の配線層7は段差を横切るが、第3図の孔8bと8c
との間を通る矢視C−C断面では、第4図に示す如く段
差のない領域を横切ることになる。従って、段差部での
段切れや膜厚減少等に起因する第3の配線層7の断線や
抵抗増大化を防止でき、配線特性及び信頼性の向上を図
ることができる。
With such a configuration, a part of the third wiring layer 7 can pass through a region without steps. That is, in the BB cross section taken through the hole 8c in FIG. 3, the third wiring layer 7 crosses the step as shown in FIG. 2, but the holes 8b and 8c in FIG.
In the cross section taken along the line C-C passing through between and, as shown in FIG. Therefore, it is possible to prevent disconnection of the third wiring layer 7 and increase in resistance due to step disconnection at the step portion, reduction in film thickness, and the like, and it is possible to improve wiring characteristics and reliability.

なお、本発明は上述した実施例に限定されるものではな
く、その要旨を逸脱しない範囲で、種々変形して実施す
ることができる。例えば、前記接続孔の分割数は4個に
限るものではなく、適宜増減できる。また、配線層の数
も3層に限るものではなく、4層以上であってもよいの
は勿論のことである。
It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be carried out without departing from the scope of the invention. For example, the number of divisions of the connection hole is not limited to four and can be increased or decreased as appropriate. Further, the number of wiring layers is not limited to three and needless to say, it may be four or more.

[発明の効果] 本発明によれば、第1の配線と第2の配線層とを接続す
るための接続孔を、この接続孔の上を通る第3の配線層
が通過する領域で複数に分割したことにより、接続孔上
の段差を横切る第3の配線層の一部を段差の無い領域を
通過させることが可能となるので、第3の配線層の段切
れや抵抗増大化等を防止することができる。また、第3
の配線層よりも幅広の接続孔を複数に分割する際に、接
続孔の上を通る第3の配線層が通過する領域外にも分解
された接続孔が設けられている。このため、第3の配線
層が通過する領域で接続孔を複数に分割したことに起因
する、第1の配線層と第2の配線層との間のコンタクト
抵抗の増大という不都合は生じない。
EFFECTS OF THE INVENTION According to the present invention, a plurality of connection holes for connecting the first wiring and the second wiring layer are provided in a region where the third wiring layer passing above the connection hole passes. Due to the division, it is possible to pass a part of the third wiring layer that crosses the step on the connection hole through a region having no step, so that the disconnection of the third wiring layer and the increase in resistance are prevented. can do. Also, the third
When the connection hole wider than the wiring layer is divided into a plurality of parts, the disassembled connection hole is provided outside the region where the third wiring layer passing over the connection hole passes. Therefore, there is no inconvenience that the contact resistance between the first wiring layer and the second wiring layer increases due to the connection hole being divided into a plurality of portions in the region through which the third wiring layer passes.

即ち、第1および第2の配線層間の接続特性は、接続孔
を面積のみならず周囲長に依存し、本発明のように第3
の配線層が通過する領域で第3の配線層の幅方向に並ぶ
複数の接続孔と第3の配線層の通過領域外に設けられた
接続孔とに分割すると、その面積は狭くなるが、周囲長
が増大するため、接続孔を小分割することによる接続特
性の劣化は殆ど問題とならない。
That is, the connection characteristic between the first and second wiring layers depends not only on the area of the connection hole but also on the peripheral length, and the connection characteristic of the third embodiment is the same as in the present invention.
When the wiring layer is divided into a plurality of connection holes arranged in the width direction of the third wiring layer and a connection hole provided outside the passage area of the third wiring layer, the area becomes smaller, Since the peripheral length is increased, the deterioration of the connection characteristics due to the subdivision of the connection hole is hardly a problem.

また、接続孔を分割することによるパターンの追加やパ
ターン面積の増大等を招くことがなく、さらに接続孔パ
ターンの分割であるのでプロセスの変更も伴わない。従
って、レイアウトやプロセス等の変更なしに、配線特性
および信頼性の向上を図ることができる。
Further, there is no need to add a pattern or increase a pattern area by dividing the connection hole, and since the connection hole pattern is divided, the process is not changed. Therefore, it is possible to improve the wiring characteristics and the reliability without changing the layout and the process.

【図面の簡単な説明】[Brief description of drawings]

第1図は従来の半導体装置の要部の構造を示す平面図、
第2図は第1図の矢視A−A断面図、第3図は本発明の
一実施例に係わる半導体装置の要部の構造を示す平面
図、第4図は第3図の矢視C−C断面図である。 1……半導体基板、2……拡散層、3……第1の絶縁
層、4……接続孔、5……第2の配線層、6……第2の
絶縁層、7……第3の配線層、8a,8b,8c……接
続小孔。
FIG. 1 is a plan view showing a structure of a main part of a conventional semiconductor device,
2 is a sectional view taken along the line AA of FIG. 1, FIG. 3 is a plan view showing the structure of the main part of the semiconductor device according to one embodiment of the present invention, and FIG. 4 is the view of FIG. It is CC sectional drawing. 1 ... Semiconductor substrate, 2 ... Diffusion layer, 3 ... First insulating layer, 4 ... Connection hole, 5 ... Second wiring layer, 6 ... Second insulating layer, 7 ... Third Wiring layers, 8a, 8b, 8c ... Connection small holes.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】第1乃至第3の配線層が絶縁層が挟んで交
互に積層された多層配線構造を有し、第1の配線層と第
2の配線層とが前記絶縁層に設けられた接続孔を通して
相互接続され、この接続孔上を第3の配線層が通過する
半導体装置であって、この第3の配線層より幅広の前記
接続孔が、前記第3の配線層が通過する領域で、前記第
3の配線層の幅方向に並ぶ複数の接続孔と前記第3の配
線層の通過領域外に設けられた接続孔とに分割されてな
ることを特徴とする半導体装置。
1. A multilayer wiring structure in which first to third wiring layers are alternately laminated with an insulating layer sandwiched therebetween, and a first wiring layer and a second wiring layer are provided in the insulating layer. In the semiconductor device, the third wiring layer is interconnected through the connection hole, and the third wiring layer passes over the connection hole. The connection hole wider than the third wiring layer passes through the third wiring layer. A region is divided into a plurality of connection holes arranged in the width direction of the third wiring layer and a connection hole provided outside the passage region of the third wiring layer.
JP1198338A 1989-07-31 1989-07-31 Semiconductor device Expired - Lifetime JPH0624220B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1198338A JPH0624220B2 (en) 1989-07-31 1989-07-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1198338A JPH0624220B2 (en) 1989-07-31 1989-07-31 Semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP57096032A Division JPS58213450A (en) 1982-06-04 1982-06-04 Structure of multilayer wiring of semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP5240153A Division JPH0783054B2 (en) 1993-09-27 1993-09-27 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0277139A JPH0277139A (en) 1990-03-16
JPH0624220B2 true JPH0624220B2 (en) 1994-03-30

Family

ID=16389457

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1198338A Expired - Lifetime JPH0624220B2 (en) 1989-07-31 1989-07-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0624220B2 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5839380B2 (en) * 1977-02-28 1983-08-30 沖電気工業株式会社 Semiconductor integrated circuit device
JPS558082A (en) * 1978-07-03 1980-01-21 Nec Corp Multi-wiring semiconductor device

Also Published As

Publication number Publication date
JPH0277139A (en) 1990-03-16

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