JP2693750B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device. 2. Description of the Related Art In recent years, semiconductor manufacturing technology has been remarkably improved, and especially in wiring on a semiconductor device, two to three layers have been formed.
The number of layers and the number of layers of four or more have been realized.
However, on the other hand, as the number of wiring layers increases, the stepped shape of the semiconductor surface becomes more and more complicated, and problems such as deterioration of wiring characteristics including disconnection and deterioration of reliability have come to the surface. In particular, with regard to connection holes (contact holes) for connecting desired wiring layers, it has been generally considered that it is common and advantageous to open the connection holes as large as possible. There were inconveniences as described below. FIG. 1 is a plan view showing a structure of a main part of a conventional semiconductor device, and FIG. 2 is a view showing a cross section taken along the line AA of FIG. In the figure, reference numeral 1 is a semiconductor substrate, and a first substrate is provided on the surface of the substrate 1.
A diffusion layer 2 as a wiring layer is formed. A first insulating layer 3 is provided on the semiconductor substrate 1, and a connection hole 4 is opened on the diffusion layer 2 of the insulating layer 3. A first wiring layer 5 as a second wiring layer made of an Al film is provided on the insulating layer 3, and the wiring layer 5 is connected to the diffusion layer 2 via a connection hole 4. Here, the connection hole 4 is relatively large in the region where the diffusion layer 2 and the wiring layer 5 overlap in order to ensure the connection between the diffusion layer 2 and the wiring layer 5, and the length of the wiring layer 5 is large. It is formed long in the direction. Further, the first insulating layer 3 and the first wiring layer 5
A second wiring layer 7 as a third wiring layer made of an Al film is provided on the second insulating layer 6 via the second insulating layer 6. In addition,
The second wiring layer 7 is formed so as to intersect with the first wiring layer 5 and passes over the connection hole 4. [0006] In such a configuration,
The second wiring layer 7 has poor step coverage of the second insulating layer 6 due to the surface shape of the first insulating layer 3 and thus has poor coverage with the insulating layer 6, resulting in a very thin film thickness at the step portion. Become.
For this reason, there is a problem that the wiring characteristics are deteriorated such as a step break of the second wiring layer 7 and the wiring resistance is increased, and the reliability is lowered due to migration and the like. The above-mentioned problem occurs because the connecting hole 4 is longer in the longitudinal direction than the width of the second wiring layer 7 and the wiring layer 7 is completely crossed by the connecting hole 4. In order to avoid this, the connection hole 4 may be formed shorter than the width of the wiring layer 7. However, in this case, the area of the connection hole 4 becomes small, and the connection between the diffusion layer 2 and the first wiring layer 5 becomes uncertain, which is not preferable. An object of the present invention is to prevent the wiring layer from being stepped or having its resistance increased due to the wiring layer passing through a step on the connection hole, thereby improving the characteristics and reliability of the wiring layer. An object of the present invention is to provide a semiconductor device capable of improving the property. [Summary] In order to achieve the above-mentioned object, a semiconductor device of the present invention includes a semiconductor substrate and first, second and third semiconductor substrates formed on the surface of the semiconductor substrate. A third wiring layer, a first insulating layer provided between the first wiring layer and the second wiring layer and separating these two wiring layers, and between the second wiring layer and the third wiring layer. A second insulating layer for separating these two wiring layers, and a first and a second insulating layer provided on the first insulating layer for obtaining a desired connection between the first wiring layer and the second wiring layer. Connecting means including two connecting holes, wherein the first connecting hole is located in an intersecting area defined as an area where the second wiring layer and the third wiring layer overlap in plan view, and the second connecting hole is formed. The hole is located outside the intersection region, and the cross-sectional area of the first connection hole is larger than the area of the intersection region. Narrow characterized. [Operation] According to the present invention, the first connection hole is located in the intersection region defined as a region where the second wiring layer and the third wiring layer overlap in plan view, and the second connection hole is formed in the intersection region. Since the area of the cross section of the first connection hole located outside is smaller than the area of the intersecting region, the second wiring layer also passes through the region without steps. As a result, the disconnection of the second wiring layer and the increase in resistance are prevented. Further, since the connection hole is provided in a region other than the intersecting region, the disadvantage of increasing the contact resistance between the first wiring layer and the second wiring layer does not occur. Embodiments of the present invention (hereinafter referred to as embodiments) will be described below with reference to the drawings. FIG. 3 is a plan view showing the structure of the main part of the semiconductor device according to one embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. This embodiment differs from the conventional example described above in that
That is, a plurality of connection holes are formed instead of the connection holes 4. That is, the first insulating layer 3 is for ensuring a desired connection between the diffusion layer 2 and the first wiring layer 5 along the length direction of the first wiring layer 5. Four connecting small holes 8a, 8b, 8c, 8d as connecting means are linearly arranged. In other words, the connection holes 8b and 8c are located in an intersection region defined as a region where the first wiring layer 5 and the second wiring layer 7 overlap in a plane, and the connection holes 8a and 8c are formed in the intersection region. The cross-sectional area of the connection holes 8b and 8c located outside is smaller than the area of the intersection region. Here, in the present embodiment, in the region where the diffusion layer 2 connected by the connection hole and the second wiring layer 7 above the first wiring layer 5 pass through, the second wiring layer The connection hole wider than 7 is divided into the connection holes 8b and 8c arranged in the width direction of the second wiring layer 7 and the connection hole 8a or the connection hole 8d provided outside the passage area of the second wiring layer 7. Is important. With such a configuration, the second wiring layer 7
Can pass through a stepless region. That is, in the BB cross section taken through the hole 8c in FIG. 3, the second wiring layer 7 crosses the step as shown in FIG. 2, but the hole 8b in FIG.
In the cross-section taken along the line C-C as seen from the arrow passing through between No. 8c and No. 8c, as shown in FIG. Therefore, it is possible to prevent disconnection of the second wiring layer 7 and increase in resistance due to step disconnection at the step portion, reduction in film thickness, and the like, and it is possible to improve wiring characteristics and reliability. Further, the connection hole 4 wider than the second wiring layer 7 is formed.
Connection holes 8a and 8d, which are also divided outside the region where the second wiring layer 7 passing over the connection hole 4 passes when dividing
Is provided, the contact resistance between the diffusion layer 2 and the first wiring layer 5 is increased due to the connection hole 4 being divided into a plurality of areas in the region where the second wiring layer 7 passes. Does not occur. That is, the connection characteristic between the wiring layers via the connection hole depends not only on the area of the connection hole but also on the peripheral length. As in the present embodiment, the plurality of connection holes 8b and 8c arranged in the width direction of the second wiring layer 7 in the region where the second wiring layer 7 passes and the second
Connection holes 8a and 8d provided outside the passage area of the wiring layer 7 of
Although the area is narrowed by dividing into, the peripheral length increases, so that the deterioration of the connection characteristics due to the small division of the connection hole 4 is hardly a problem. Further, there is no need to add a pattern or increase a pattern area by dividing the connection hole 4,
Furthermore, the division of the connection hole pattern does not involve any process change. Therefore, the wiring characteristics and reliability can be improved without changing the layout or the process. The present invention is not limited to the above-described embodiment, and various modifications can be carried out without departing from the scope of the invention. For example, the number of divisions of the connection hole is not limited to four and can be increased or decreased as appropriate. According to the present invention, the first connection hole is located in the intersection area defined as the area where the second wiring layer and the third wiring layer overlap in a plane, and the second connection hole is formed in the intersection area. Since the area of the cross section of the first connection hole located outside is smaller than the area of the intersecting region, the second wiring layer also passes through the region having no step. This prevents step breakage of the second mutual coupling layer, increase in resistance, and the like. Further, since the connection hole is provided in a region other than the intersecting region, the disadvantage of increasing the contact resistance between the first wiring layer and the second wiring layer does not occur.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing a structure of a main part of a conventional semiconductor device. FIG. 2 is a sectional view taken along the line AA of FIG. 1. FIG. 3 is a diagram showing an embodiment of the present invention. FIG. 4 is a plan view showing the structure of the main part of the semiconductor device. FIG. 4 is a cross-sectional view taken along the line CC in FIG. 3 [Description of symbols] 1 ... Semiconductor substrate 2 ... Diffusion layer (first wiring layer) 3 ... First insulation Layer 4 ... Connection hole 5 ... First wiring layer (second wiring layer) 6 ... Second insulating layer 7 ... Second wiring layer (third wiring layer) 8a, 8d ... Connection small hole (first connection hole) , Connecting means) 8b, 8c ... connecting small hole (second connecting hole, connecting means)

Claims (1)

(57) [Claims] A semiconductor substrate, first, second and third wiring layers formed on the surface of the semiconductor substrate, and provided between the first wiring layer and the second wiring layer and separating these two wiring layers. A first insulating layer, and a second insulating layer that is provided between the second wiring layer and the third wiring layer and separates these two wiring layers from each other, and between the first wiring layer and the second wiring layer. Connecting means including first and second connection holes provided in the first insulating layer to obtain a desired connection, the first connection hole including the second wiring layer and the third wiring layer. Is located within an intersecting region defined as a region overlapping in plan view, the second connecting hole is located outside the intersecting region, and the cross-sectional area of the first connecting hole is smaller than the area of the intersecting region. A semiconductor device characterized by: