JPS6037749A - Formation of wiring layer - Google Patents

Abstract

PURPOSE:To obtain the titled layer generating disconnections by a method wherein a polycrystalline Si wiring layer is formed on a semiconductor substrate, the entire surface including it then covered with the first insulation film, and, when the first metallic wiring layer parallel with the Si wiring layer is formed thereon, the Si wiring layer is deformed to the opposite side of the first metallic wiring layer only the crossing part of the second metallic wiring layer provided via insulation layer without the shift of the whole of the parallel Si wiring layer. CONSTITUTION:A polycrystalline Si wiring layer 2 is provided on the semiconductor substrate 1, the entire surface including the layer being covered with the first insulation layer 3, and the first metallic wiring layer adjacent to and parallel with the layer 2 being then formed thereon. At this time, the gap between the wiring layers 2 and 4 are kept enlarged by deformation of the wiring layer 2 to the opposite side of the wiring layer 4 only in the parts in which the second metallic wiring layer 6 provided on the second insulation layer 5 provided over the entire surface cross these layers 2 and 4 parallel with each other, the other parts being then made parallel as in the beginning. The numeral 8 shown by the separate figure represents the layer 4, 9 the layer 6 and 7 the layer 2 deformed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of forming a wiring layer of a semiconductor device.

As shown in FIG. 3, the conventional method for forming a wiring layer of a semiconductor device is to form a poly wiring layer 12 on a semiconductor substrate 11,
An insulating layer 13 is formed thereon, and a first metal interconnection layer 14 is formed on the insulating layer 13 from the polysilicon interconnection layer 12 with an overlapping margin A.
Formed in close proximity to each other. Further, a second insulating layer 15 is formed thereon. However, the method of forming the insulating layer 16 and the second insulation layer 15 is usually a chemical vapor deposition method, but this method does not provide good coverage especially under the stepped portion, and sometimes grooves are formed. be done. Moreover, when forming the second insulating layer 15, if the distance A between the void IJ Si wiring layer 12 and the @11 metal helix 14 is small, the insulating layer 13 and the first metal helix 140 locations will form grooves. This is the same as if the second insulating layer 15 formed thereon was not covered and a thin and deep crack had formed (section B in FIG. 1), and the second metal wiring layer 16 formed thereon was exposed to the crack. There is a greater possibility that a wire breakage will occur at some point. .

In addition, as a means to prevent the above-mentioned wire breakage, BoIJS
i wiring layer 12 and first metal wiring J? To increase the distance A of v14, in order to increase this distance MA,
For example, if the position of the first metal wiring layer 14 is laterally shifted, disconnections will not occur, but the degree of integration as a semiconductor device will deteriorate, the size of one semiconductor device will increase, and cost performance will be significantly impaired. Become.

The present invention eliminates this drawback, and its purpose is to provide a method for forming a wiring layer that does not cause disconnection σ. Another major objective is to provide a method for forming a wiring layer that can achieve the above objective without deteriorating the degree of integration.

Therefore, the present invention achieves the above object by changing the shape of the poly 1J 81 wiring layer 12 at the position where the second gold H wiring layer 16 crosses, without shifting the entire poly 81 wiring layer 12 laterally. It is characterized by what it achieves.

Examples will be explained below.

FIG. 1 is a sectional view of Example 1. 2 is a poly 81 wiring layer according to the present invention. This poly S1 wiring layer 2 is
The poly 8j wiring layer 7 (or 2) and the first
0-A, where the distance A of the metal wiring N8C or 4) is set to the distance where the second metal wiring layer 9 (or 6) crosses.
As shown in FIG.
The second metal wiring layer 6 has a structure in which the second metal wiring layer 6 is not disconnected. Also, the values of A and C according to the example are A
= 1. C1μm, C”=2.0μm,
A sufficient effect was obtained by deforming the poly wiring layer 2 by about 1.0 μm. Also, the work was easy as it was only a partial change to the pattern. Furthermore, since the pitch between wiring layers has not been changed, the degree of integration has not deteriorated.

As described above, the present invention can be implemented by partially changing the method of forming wiring layers, and is a method that does not deteriorate the degree of integration, and is an effective means for manufacturing semiconductor devices.

[Brief explanation of drawings]

FIG. 1: A sectional view of an embodiment according to the present invention. 1... Semiconductor substrate 2... Poly 81 wiring layer 6...Insulating layer 4...First metal wiring layer 5...Second insulating layer 6...Second metal wiring layer FIG. 2: A plan view of Embodiment 1 according to the present invention. 7...Poly wiring layer 8...First metal wiring layer 9...Second metal wiring layer Figure 6: Cross-sectional view of the conventional method. 11...Semiconductor substrate 12...Poly S1 wiring layer 13...Insulating layer 14...first metal wiring layer 15...Second insulating layer 16...Second metal wiring layer

Claims (1)

[Claims] A PO IJ S I wiring layer having a step in a part thereof is formed on a semiconductor substrate, and an insulating layer is formed on the soil of the IJ F3 I wiring layer. When forming a first metal wiring layer at a position close to the board, and further forming a second metal wiring across the board and the first metal wiring layer,
The method is characterized in that the distance between the step of the I381 wiring layer and the first metal wiring layer is increased by deforming a portion of the JSl wiring layer located below the second metal wiring layer. A method for forming a wiring layer.