JP2001068653A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit which can make the design of its wiring pattern easier by significantly improving the wiring efficiency and degree of freedom for wiring. SOLUTION: On a basic cell 10, the gate electrodes 11 and 12 of a p-type MOS transistor and the gate electrodes 14 and 15 of an N-type MOS transistor are provided. A P-type impurity diffusion region 13 is formed below the gate electrodes 11 and 12 and an N-type impurity diffusion region 16 is formed below the gate electrodes 14 and 15. At both end sections of the basic cell 10, power supply wiring regions 17 and 18 are respectively formed. Each impurity diffusion region 13 or 16 is formed in a projecting shape as a whole with an extension 13a or 16a which is formed in such a way that the front end section of the section 13a or 16a is extended to a spot below the wiring region 17 or 18 so that the region 13 or 16 may be utilized as wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit, and more particularly to an improvement in a cell layout structure in the semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, the above-mentioned semiconductor integrated circuits are processed uniformly from LSI design to diffusion processing in order to promptly respond to requests from customers, and only the subsequent circuit wiring is used. 2. Description of the Related Art There is known a master slice type semiconductor integrated circuit which is performed every time. This master-slice type semiconductor integrated circuit is realized by connecting a plurality of basic cells arranged in a matrix or in one direction in accordance with the specifications of a finished product. It has an advantage suitable for the production of many kinds of small quantities, such as reduction of the amount.

For example, as shown in FIG. 5, a general basic cell 100 mounted on a master slice type semiconductor integrated circuit includes a gate electrode 1 of a P-type MOS transistor.
01, 102, a P-type impurity diffusion region 103 serving as a drain terminal or a source terminal, gate electrodes 104 and 105 of an N-type MOS transistor, an N-type impurity diffusion region 106 serving as a drain terminal or a source terminal, and two power supply wiring regions 107 and 108.

FIG. 2A shows an inverter circuit 110 as an example of a conventional circuit manufactured using such a basic cell 100. The inverter circuit 110 is configured using each one of a P-type transistor group 111 and an N-type transistor group 112, and includes the power supply wiring regions 107 and 108, and the P-type and N-type impurity diffusion region 1
03, 106, the other (drain region D) of the P-type impurity diffusion region 103, the other (drain region D) of the N-type impurity diffusion region 106, and the gate electrode 102 of the P-type MOS transistor. The gate electrode 105 of the N-type MOS transistor is connected to the first metal layer wiring 113, 114, 115, 116, 117, 118, respectively.
Connected by the inverter circuit 110
As a result, a desired function is realized.

[0005]

As described above, in a master-slice type semiconductor integrated circuit, a plurality of basic cells 100 arranged in advance are arbitrarily connected by metal wiring, so that each of the basic cells 100 has a desired configuration. A functional circuit is realized.

However, in the above-described conventional basic cell 100, in order to secure electrical connection between the P-type and N-type impurity diffusion regions 103 and 106 and the power supply wiring regions 107 and 108, a metal one-layer wiring is required. In addition to the 113 and 114, it is also necessary to lay the metal 1 layer wirings 115 and 116.
This is a major obstacle in designing wiring patterns, such as laying layer wiring. That is, as shown in FIG. 3A, in the above-described conventional semiconductor integrated circuit, the metal single-layer wiring 119 for passing through a plurality of cells is parallel to the metal single-layer wirings 113 and 114 serving as power supply wirings. However, there is a situation in which only about two wirings 119 can be laid in total because of the presence of the metal one-layer wirings 115 and 116. For this reason, conventionally, when it is necessary to further increase the metal one-layer wiring 119 for such over-through, the wiring area has to be prepared around the basic cell 100, and the wiring efficiency and the freedom of wiring are required. The degree is extremely low. Note that, not only in the above-described master-slice type semiconductor integrated circuit but also in a semiconductor integrated circuit having an impurity diffusion region and requiring an electrical connection to an arbitrary wiring, such a situation is generally common. It has become something.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor integrated circuit capable of greatly improving wiring efficiency and wiring freedom and making it easier to design a wiring pattern. To provide.

[0008]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit in which an impurity diffusion region is formed in a semiconductor substrate, wherein the impurity diffusion region is used as a wiring. Has an extension area.

As described above, the extension region is provided for the impurity diffusion region formed in the semiconductor substrate and can be used as a wiring, so that the wiring can be laid on the semiconductor substrate. Can be reduced. In particular, when the wiring to be reduced is laid in a direction intersecting with other wiring, the wiring efficiency on the semiconductor substrate and the degree of freedom of wiring are greatly increased, and these wirings are reduced. The design of the pattern is also very easy.

[0010] Further, by improving the wiring efficiency on the semiconductor substrate in this way, it is possible to reduce the chip area and further increase the integration of the semiconductor integrated circuit. Note that the salicidation of a transistor in recent process technology or the silicidation of the impurity diffusion region tends to lower the sheet resistance of the diffusion region. It is in.

According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the extension region extends to a metal wiring region of the semiconductor integrated circuit and is laid in the metal wiring region. The presence / absence of electrical connection between the metal interconnection and the impurity diffusion region is selected depending on the presence / absence of contact with the interconnection.

According to the above configuration, the disposition of the extension region with respect to the impurity diffusion region can be realized as a common process, and whether or not this disposition is used as a wiring is determined as described above. It is determined only by the presence or absence of the contact with the metal wiring. Therefore, the above-described wiring pattern design can be made easier and more flexible.

According to a third aspect of the present invention, in the semiconductor integrated circuit according to the second aspect, the metal wiring to be contacted is a power wiring. According to the above configuration,
The structure of the present invention can be easily applied by using the metal wiring to be contacted as the power supply wiring.

According to a fourth aspect of the present invention, in the semiconductor integrated circuit, a number of basic cells are arranged and formed in advance on a semiconductor substrate, and a desired function is realized by arbitrarily wiring these basic cells. The basic cell has an impurity diffusion region, and the impurity diffusion region has one or a plurality of extension regions used as the wiring.

As described above, the extension region is provided for the impurity diffusion region in the basic cell and formed in the semiconductor substrate, and the extension region can be used as a wiring. Wiring can be reduced to be laid on the basic cell. And also in this case,
In particular, when the wiring to be reduced is laid in a direction intersecting with other wiring, the wiring efficiency on the basic cell and the degree of freedom of wiring are greatly increased, and the wiring pattern Also becomes very easy to design.

In addition, by improving the wiring efficiency on the basic cell in this way, it is possible to reduce or omit the wiring area prepared exclusively for the semiconductor integrated circuit. It is also possible to reduce the chip area as a semiconductor integrated circuit and further increase the degree of integration.

Incidentally, the salicidation of the transistor in the recent process technology or the silicidation of the impurity diffusion region tends to lower the sheet resistance of the diffusion region. The possible levels are as described above.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit according to the fourth aspect, the extended region extends to a wiring region of the semiconductor integrated circuit, and a metal wiring laid in the wiring region. The presence or absence of the contact determines whether or not there is an electrical connection between the metal wiring and the impurity diffusion region.

According to the above configuration, whether or not the extension region provided in advance in the impurity diffusion region as a basic cell is used as a wiring is determined only by the presence or absence of a contact with the metal wiring. Therefore, the above-described wiring pattern design as a semiconductor integrated circuit can be made easier and more flexible.

According to a sixth aspect of the present invention, in the semiconductor integrated circuit according to the fifth aspect, the metal wiring to be contacted is a metal one-layer wiring of the semiconductor integrated circuit.

In a semiconductor integrated circuit, the wiring efficiency of the metal one-layer wiring is a major factor that affects the utilization efficiency of the basic cell. In this regard, according to the above configuration, the wiring efficiency of the metal one-layer wiring is improved together with the degree of freedom of the wiring, so that the utilization efficiency of the basic cell is greatly improved.

According to a seventh aspect of the present invention, in the semiconductor integrated circuit according to the sixth aspect, the metal one-layer wiring to be contacted is a common wiring between the basic cells. In a semiconductor integrated circuit, it is desirable that all of the basic cell structures are shared. In this regard, according to the above-described configuration in which the metal 1-layer wiring to be contacted with the extension region is a common interconnection between the basic cells, the shape and extension mode of the extension region are all It becomes possible to standardize. Therefore, even when the extension region is provided in the impurity diffusion region, the versatility as a semiconductor integrated circuit can be maintained at a high level.

According to an eighth aspect of the present invention, in the semiconductor integrated circuit according to the seventh aspect, the common wiring to be contacted is a power supply wiring. According to the above configuration, by setting the common wiring to be a contact target to the power supply wiring,
The structure of the present invention can be easily applied.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment in which the semiconductor integrated circuit of the present invention is embodied as a master slice type semiconductor integrated circuit will be described below with reference to FIGS.

As shown in FIG. 1, in the semiconductor integrated circuit of this embodiment, a P-type MOS made of, for example, polysilicon is provided on a basic cell 10 formed on the semiconductor substrate.
Gate electrodes 11 and 12 of transistor and N-type MOS
Gate electrodes 14 and 15 of the transistor are provided. The end of each of the gate electrodes 11, 12, 14, and 15 is wide and is used for connection to a metal wiring through a contact hole. In the same basic cell 10, a P-type impurity diffusion region 13 is formed below the gate electrodes 11 and 12, and an N-type impurity diffusion region 16 is formed below the gate electrodes 14 and 15. I have. As shown in FIG. 1, in the present embodiment, these P
The N-type and N-type impurity diffusion regions 13 and 16 have extended portions (extended regions) 13a and 16a, respectively, and are formed in a convex shape as a whole when viewed from a plane.
The tip of 16a is located below the power supply wiring regions 17 and 18 provided at both ends of the basic cell 10, respectively.

FIG. 2B shows an inverter circuit 20 as an example of a circuit manufactured using such a basic cell 10.
It shows. The inverter circuit 20 is configured using each one of a P-type transistor group 21 and an N-type transistor group 22. The P-type impurity diffusion region 13
Drain regions D and D and a source region S are formed by being divided into three by the gate electrodes 11 and 12. Similarly, the N-type impurity diffusion region 16 is divided into three by gate electrodes 14 and 15, and drain regions D, D and a source region S are formed. In addition to the power supply wiring regions 17 and 18, the drain region D of the P-type impurity diffusion region 13, the drain region D of the N-type impurity diffusion region 16, and the P-type MO
The gate electrode 12 of the S transistor and the gate electrode 15 of the N-type MOS transistor are
3, 24, 27, and 28 are connected. The metal 1 layer wiring 23 is formed on the extension 1 of the P-type impurity diffusion region 13.
The contact portion 25 provided on 3a is connected to the source region S of the P-type transistor group 21. Similarly, the metal 1 layer wiring 24 is formed in the N-type impurity diffusion region 1.
6 are connected to the source region S of the N-type transistor group 22 by a contact portion 26 provided on the extension 16a. The desired function as the inverter circuit 20 is realized by the electrical connection of the components in this manner. Note that the “x” mark in the drawing indicates a contact portion.

As described above, in the basic cell 10 of the present embodiment, since the extension portions 13a and 16a are provided in the P-type and N-type impurity diffusion regions 13 and 16, respectively, the basic cell 10 is used, for example. Even in the inverter circuit 20, the conventional inverter circuit 110 illustrated in FIG.
2A, it is not necessary to provide the metal one-layer wirings 115 and 116 in FIG. Therefore, even when it is necessary to lay a single-layer metal wiring for over-through between a plurality of basic cells 10, there is a margin in the space on the basic cells 10. That is,
As shown in FIG. 3B in comparison with FIG. 3A, when a metal single-layer wiring 29 for passing through a plurality of cells is laid on the basic cell 10, a total of 6 It becomes possible to lay the wiring of this level. In other words, this means that the wiring efficiency and the degree of freedom of wiring on the basic cell 10 are greatly increased, thereby making it easy to design a wiring pattern for the metal single-layer wiring. It becomes something.

As described above, according to the semiconductor integrated circuit of the present embodiment, the following effects can be obtained. (1) In the basic cell 10 of the present embodiment, the extension portions 13a and 16a are provided for the P-type and N-type impurity diffusion regions 13 and 16.
, Which can be used as wiring, so that the number of wirings to be laid on the basic cell 10 can be reduced. In this case, particularly when the wiring to be reduced is laid in a direction intersecting with other wirings, the wiring efficiency on the basic cell 10 and the degree of freedom of wiring are greatly increased. Also, the design of these wiring patterns becomes extremely easy. In addition, by improving the wiring efficiency on the basic cell in this way, it is possible to reduce or omit the wiring area dedicated to the master slice type semiconductor integrated circuit, and consequently, It is also possible to reduce the chip area and further increase the integration as the semiconductor integrated circuit. Note that the salicidation of a transistor in recent process technology or the silicidation of the impurity diffusion region tends to lower the sheet resistance of the diffusion region. It is in.

(2) The metal wirings to be contacted are the metal first-layer wirings 23, 24. In particular, in a semiconductor integrated circuit of the master slice type, the wiring efficiency of the metal one-layer wiring influences the utilization efficiency of the basic cell, so that the wiring efficiency is increased together with the degree of freedom of the wiring,
The use efficiency of the basic cell 10 is also greatly improved.

(3) Since the first metal wirings 23 and 24 to be contacted with the extending portions 13a and 16a are common wirings between the basic cells 10, the extending portions 13a and 16a
The same can be applied to the shape and the extension mode of 16a. In particular, in a master-slice semiconductor integrated circuit, it is desirable that all of the basic cells have a common structure, so that versatility as a master-slice semiconductor integrated circuit can be maintained at a high level.

(4) Since the common wiring to be contacted is used as the power supply wiring areas 17 and 18, the structure of the basic cell 10 can be easily applied. In addition,
The above embodiment may be modified as follows.

In the basic cell 10 of the above embodiment, the P-type and N-type impurity diffusion regions 13 and 16 are formed in a convex shape, but the shapes of the P-type and N-type impurity diffusion regions are changed as shown in FIG. May be. In the basic cell 30 shown in FIG. 4A, the entirety of the P-type and N-type impurity diffusion regions 33 and 36 is formed in an L shape when viewed from a plane. In the basic cell 40 shown in FIG. 4B, the whole of the P-type and N-type impurity diffusion regions 43 and 46 is formed in a concave shape when viewed from a plane. In the basic cell 50 shown in FIG. 4C, the P-type and N-type impurity diffusion regions 43,
46 was formed substantially in the shape of a mountain when viewed from above. Also in these basic cells 30, 40, and 50, a contact portion (contact hole) is provided at the tip of the extension of each impurity diffusion region.
Through C, it is electrically connected to power supply wiring (metal 1 layer wiring) laid in the power supply wiring areas 17 and 18.

By changing the shape of the basic cell in this way, it can be applied to various types of semiconductor integrated circuits, and the degree of freedom in layout as a large-scale gate array LSI using the master slice method can be increased. become able to.

The respective basic cells 10, 30, 40, 50
In the embodiment, the P-type impurity diffusion region and the N-type impurity diffusion region are formed in the same shape. However, these different shapes may be appropriately combined. Here, for convenience of explanation, the impurity diffusion regions 13 and 16 of the basic cell 10 are convex,
The impurity diffusion regions 33 and 36 of the basic cell 40 are L-shaped, the impurity diffusion regions 43 and 46 of the basic cell 40 are concave, and the impurity diffusion regions 53 and 56 of the basic cell 50 are chevron-shaped.
When the impurity diffusion regions 103 and 106 of No. 00 are square, the combination pattern is square and convex, square and L-shaped, square and concave, square and chevron, convex and L-shaped. Shape, convex and concave, convex and chevron, L-shaped and concave, L
There are a letter shape and a chevron shape, and an L shape and a chevron shape. With such a configuration, it can be applied to various types of semiconductor integrated circuits.

In the basic cells 10, 30, 40, and 50, the case where all of the diffusion region extension portions are used as wirings by contacting metal wirings is shown. A configuration may be adopted in which the use or non-use of the protrusion as the wiring, that is, the presence or absence of the electrical connection between the metal wiring and the diffusion region is selected. According to such a configuration, whether to use the diffusion region extension as a wiring in advance as a basic cell is determined only by the presence or absence of a contact with the metal wiring. Therefore, the design of a wiring pattern as a master slice type semiconductor integrated circuit can be made easier and more flexible.

In each of the above embodiments, both ends of the basic cell are formed as the power supply wiring regions 17 and 18. However, these regions are not limited to the power supply wiring and may be used as signal line regions. Further, the wiring to be contacted with the diffusion region extension is not limited to the common wiring between the basic cells.

The above embodiments are not limited to those applied to the master slice type semiconductor integrated circuit, but are also applicable to standard cell type semiconductor integrated circuits and dedicated LSIs. Therefore, for example, in each of the above-described basic cells, the configuration may be such that the presence or absence of the contact portion can determine whether or not the metal wiring and the impurity diffusion region are electrically connected. In this case, the disposition of the extension portion with respect to the impurity diffusion region can be realized as a common process,
Whether or not the provided extension portion is used as a wiring is determined only by the presence or absence of a contact portion with a metal wiring. Therefore, the design of the wiring pattern can be made easier and more flexible.

[0038]

As described in detail above, according to the first to third aspects of the present invention, the number of wirings to be laid on a semiconductor substrate can be reduced. In particular, when the wiring to be reduced is laid in a direction intersecting with other wiring, the wiring efficiency on the semiconductor substrate and the degree of freedom of wiring are greatly increased, and these wirings are reduced. The design of the pattern is also very easy. In addition, by improving the wiring efficiency on the semiconductor substrate in this way, it is possible to reduce the chip area and further increase the integration of the semiconductor integrated circuit.

According to the fourth to eighth aspects of the present invention, the number of wirings to be laid on the basic cell can be reduced. Also in this case, particularly when the wiring to be reduced is laid in a direction intersecting with other wiring, the wiring efficiency on the basic cell and the degree of freedom of wiring are greatly increased. Also, the design of these wiring patterns becomes extremely easy. In addition, by improving the wiring efficiency on the basic cell in this way, it is possible to reduce or omit the wiring area prepared exclusively for the semiconductor integrated circuit. It is also possible to reduce the chip area and further increase the degree of integration.

[Brief description of the drawings]

FIG. 1 is a plan view showing the structure of a basic cell according to an embodiment of the present invention.

FIG. 2 is a plan view showing an inverter circuit obtained by connecting basic cells in comparison with a conventional circuit and that of the same embodiment.

FIG. 3 is a plan view showing a state in which another metal wiring is laid on the inverter circuit in comparison with a conventional one and the same embodiment.

FIG. 4 is a plan view showing a structure of a basic cell according to another embodiment of the present invention.

FIG. 5 is a plan view showing the structure of a conventional basic cell.

[Explanation of symbols]

11, 12, 14, 15 ... gate electrode, 13 ... P-type impurity diffusion region, 16 ... N-type impurity diffusion region, 13a, 16
a: extension part (extension area), 17, 18 ... power supply wiring area as metal wiring area.

Claims (8)

[Claims] 1. A semiconductor integrated circuit in which an impurity diffusion region is formed in a semiconductor substrate, wherein the impurity diffusion region has an extension region used as a wiring. 2. The semiconductor device according to claim 1, wherein the extension region extends to a metal wiring region of the semiconductor integrated circuit, and an electrical connection between the metal wiring and the impurity diffusion region depends on the presence or absence of a contact with the metal wiring laid in the metal wiring region. 2. The semiconductor integrated circuit according to claim 1, wherein the presence or absence of a temporary connection is selected. 3. The semiconductor integrated circuit according to claim 2, wherein the metal wiring to be contacted is a power wiring. 4. In a semiconductor integrated circuit in which a number of basic cells are arranged and formed in advance on a semiconductor substrate, and a desired function is realized by providing an arbitrary wiring to the basic cells, the basic cells have impurity diffusion regions. A semiconductor integrated circuit, wherein the impurity diffusion region has one or a plurality of extension regions used as the wiring. 5. The extension region extends to a wiring region of the semiconductor integrated circuit, and an electrical connection between the metal wiring and the impurity diffusion region depends on the presence or absence of contact with a metal wiring laid in the wiring region. 5. The semiconductor integrated circuit according to claim 4, wherein presence or absence of connection is selected. 6. The semiconductor integrated circuit according to claim 5, wherein the metal wiring to be contacted is a metal one-layer wiring of the semiconductor integrated circuit. 7. The semiconductor integrated circuit according to claim 6, wherein the metal one-layer wiring to be contacted is a common wiring between the basic cells. 8. The semiconductor integrated circuit according to claim 7, wherein the common wiring to be contacted is a power wiring.