JP3338050B2 - アナログ／デイジタル変換器 - Google Patents

アナログ／デイジタル変換器

Info

Publication number
JP3338050B2
JP3338050B2 JP50061192A JP50061192A JP3338050B2 JP 3338050 B2 JP3338050 B2 JP 3338050B2 JP 50061192 A JP50061192 A JP 50061192A JP 50061192 A JP50061192 A JP 50061192A JP 3338050 B2 JP3338050 B2 JP 3338050B2
Authority
JP
Japan
Prior art keywords
voltage
output
terminal
input terminal
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP50061192A
Other languages
English (en)
Japanese (ja)
Other versions
JPH05509214A (ja
Inventor
サウアー，ドナルド・ジヨン
Original Assignee
サーノフ コーポレイション
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by サーノフ コーポレイション filed Critical サーノフ コーポレイション
Publication of JPH05509214A publication Critical patent/JPH05509214A/ja
Application granted granted Critical
Publication of JP3338050B2 publication Critical patent/JP3338050B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M1/1023—Offset correction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1033—Calibration over the full range of the converter, e.g. for correcting differential non-linearity
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Manipulation Of Pulses (AREA)
JP50061192A 1990-07-02 1991-07-02 アナログ／デイジタル変換器 Expired - Fee Related JP3338050B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB909014679A GB9014679D0 (en) 1990-07-02 1990-07-02 Sequential successive approximation a/d converter
GB9014679,6 1990-07-02
PCT/US1991/004551 WO1992001336A1 (en) 1990-07-02 1991-07-02 Analog to digital converter

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2001238268A Division JP2002094377A (ja) 1990-07-02 2001-08-06 アナログ／ディジタル変換器

Publications (2)

Publication Number Publication Date
JPH05509214A JPH05509214A (ja) 1993-12-16
JP3338050B2 true JP3338050B2 (ja) 2002-10-28

Family

ID=10678554

Family Applications (2)

Application Number Title Priority Date Filing Date
JP50061192A Expired - Fee Related JP3338050B2 (ja) 1990-07-02 1991-07-02 アナログ／デイジタル変換器
JP2001238268A Ceased JP2002094377A (ja) 1990-07-02 2001-08-06 アナログ／ディジタル変換器

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2001238268A Ceased JP2002094377A (ja) 1990-07-02 2001-08-06 アナログ／ディジタル変換器

Country Status (7)

Country Link
US (1) US5262779A (enExample)
EP (2) EP0537304B1 (enExample)
JP (2) JP3338050B2 (enExample)
DE (2) DE69133008T2 (enExample)
ES (1) ES2129443T3 (enExample)
GB (1) GB9014679D0 (enExample)
WO (1) WO1992001336A1 (enExample)

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US5543795A (en) * 1995-06-02 1996-08-06 Intermedics, Inc. Hybrid analog-to-digital convertor for low power applications, such as use in an implantable medical device
US5748134A (en) * 1996-03-01 1998-05-05 Ericsson Inc. Method and apparatus for converting an analog signal into digital format
US6289070B1 (en) 1997-04-22 2001-09-11 Silicon Laboratories, Inc. Digital isolation system with ADC offset calibration including coarse offset
US6144326A (en) 1997-04-22 2000-11-07 Silicon Laboratories, Inc. Digital isolation system with ADC offset calibration
US6307891B1 (en) 1997-04-22 2001-10-23 Silicon Laboratories, Inc. Method and apparatus for freezing a communication link during a disruptive event
US6389134B1 (en) 1997-04-22 2002-05-14 Silicon Laboratories, Inc. Call progress monitor circuitry and method for a communication system
US6298133B1 (en) 1997-04-22 2001-10-02 Silicon Laboratories, Inc. Telephone line interface architecture using ringer inputs for caller ID data
US6516024B1 (en) 1997-04-22 2003-02-04 Silicon Laboratories Inc. Digital access arrangement circuitry and method for connecting to phone lines having a DC holding circuit with low distortion and current limiting
US5870046A (en) 1997-04-22 1999-02-09 Silicon Laboratories Inc. Analog isolation system with digital communication across a capacitive barrier
US6480602B1 (en) 1997-04-22 2002-11-12 Silicon Laboratories, Inc. Ring-detect interface circuitry and method for a communication system
US6359983B1 (en) 1997-04-22 2002-03-19 Silicon Laboratories, Inc. Digital isolation system with data scrambling
US6442213B1 (en) * 1997-04-22 2002-08-27 Silicon Laboratories Inc. Digital isolation system with hybrid circuit in ADC calibration loop
US6587560B1 (en) 1997-04-22 2003-07-01 Silicon Laboratories Inc. Low voltage circuits powered by the phone line
US6456712B1 (en) 1997-04-22 2002-09-24 Silicon Laboratories Inc. Separation of ring detection functions across isolation barrier for minimum power
US6498825B1 (en) 1997-04-22 2002-12-24 Silicon Laboratories Inc. Digital access arrangement circuitry and method for connecting to phone lines having a DC holding circuit with programmable current limiting
US6385235B1 (en) 1997-04-22 2002-05-07 Silicon Laboratories, Inc. Direct digital access arrangement circuitry and method for connecting to phone lines
US6442271B1 (en) 1997-04-22 2002-08-27 Silicon Laboratories, Inc. Digital isolation system with low power mode
US6430229B1 (en) 1997-04-22 2002-08-06 Silicon Laboratories Inc. Capacitive isolation system with digital communication and power transfer
US6137827A (en) 1997-04-22 2000-10-24 Silicon Laboratories, Inc. Isolation system with digital communication across a capacitive barrier
US6167134A (en) 1997-04-22 2000-12-26 Silicon Laboratories, Inc. External resistor and method to minimize power dissipation in DC holding circuitry for a communication system
US6504864B1 (en) 1997-04-22 2003-01-07 Silicon Laboratories Inc. Digital access arrangement circuitry and method for connecting to phone lines having a second order DC holding circuit
US6408034B1 (en) 1997-04-22 2002-06-18 Silicon Laboratories, Inc. Framed delta sigma data with unlikely delta sigma data patterns
US5929667A (en) * 1997-06-10 1999-07-27 International Business Machines Corporation Method and apparatus for protecting circuits subjected to high voltage
US5955978A (en) * 1997-09-08 1999-09-21 Lsi Logic Corporation A/D converter with auto-zeroed latching comparator and method
US5914681A (en) * 1997-10-02 1999-06-22 Burr-Brown Corporation Fast wakeup biasing circuit for analog-to-digital converter
US6097244A (en) * 1998-12-17 2000-08-01 Centillium Communications, Inc. Highly-linear continuous-time filter for a 3-volt supply with PLL-controlled resistor and digitally-controlled capacitor
SE513434C2 (sv) * 1999-01-20 2000-09-11 Ericsson Telefon Ab L M Lågenergi PARALLELL ADC
SE517675C2 (sv) 2000-03-14 2002-07-02 Ericsson Telefon Ab L M Ett förfarande för A/D-omvandling samt ett A/D- omvandlingssystem
US6366231B1 (en) * 2000-04-10 2002-04-02 General Electric Company Integrate and fold analog-to-digital converter with saturation prevention
US6654594B1 (en) * 2000-05-30 2003-11-25 Motorola, Inc. Digitized automatic gain control system and methods for a controlled gain receiver
DE10066029B4 (de) * 2000-08-23 2005-11-10 Infineon Technologies Ag Analog/Digital-Wandler
US6559689B1 (en) 2000-10-02 2003-05-06 Allegro Microsystems, Inc. Circuit providing a control voltage to a switch and including a capacitor
US7102559B2 (en) * 2003-01-17 2006-09-05 Koninklijke Philips Electronics, N.V. Analog-to-digital converter having interleaved coarse sections coupled to a single fine section
US7095354B2 (en) * 2004-08-12 2006-08-22 General Electric Company Very linear wide-range pipelined charge-to-digital converter
JP4827627B2 (ja) * 2006-06-16 2011-11-30 キヤノン株式会社 撮像装置及びその処理方法
US8212697B2 (en) 2010-06-15 2012-07-03 Csr Technology Inc. Methods of and arrangements for offset compensation of an analog-to-digital converter
US9160293B2 (en) 2013-09-07 2015-10-13 Robert C. Schober Analog amplifiers and comparators
ITMI20132037A1 (it) 2013-12-06 2015-06-07 St Microelectronics Int Nv Metodo per la correzione di errori digitali per convertitore analogico digitale binario ad approssimazioni successive.
KR102094469B1 (ko) 2013-12-10 2020-03-27 삼성전자주식회사 디지털-아날로그 변환 장치 및 방법
KR102188059B1 (ko) 2013-12-23 2020-12-07 삼성전자 주식회사 Ldo 레귤레이터, 전원 관리 시스템 및 ldo 전압 제어 방법
EP3114690B1 (en) * 2014-03-07 2020-02-12 Intel Corporation Physically unclonable function circuit using resistive memory device
TWI566530B (zh) * 2014-11-03 2017-01-11 瑞昱半導體股份有限公司 連續逼近式類比至數位轉換器與轉換方法
US9543974B1 (en) * 2015-09-18 2017-01-10 Analog Devices, Inc. Reducing switching error in data converters
JP6445746B2 (ja) * 2016-12-21 2018-12-26 オリンパス株式会社 逐次比較型ａ／ｄ変換装置、撮像装置、内視鏡および設定方法
US9941894B1 (en) 2017-05-04 2018-04-10 Analog Devices Global Multiple string, multiple output digital to analog converter
US10782263B2 (en) 2017-05-04 2020-09-22 Analog Devices Global Systems and methods for determining the condition of a gas sensor
US10075179B1 (en) 2017-08-03 2018-09-11 Analog Devices Global Multiple string, multiple output digital to analog converter
US10454488B1 (en) * 2018-05-31 2019-10-22 Analog Devices Global Unlimited Company Variable speed comparator
US10291251B1 (en) * 2018-09-21 2019-05-14 Semiconductor Components Industries, Llc Imaging systems with sub-radix-2 charge sharing successive approximation register (SAR) analog-to-digital converters
US11558061B2 (en) * 2021-04-22 2023-01-17 Ciena Corporation ADC self-calibration with on-chip circuit and method
JP2024055052A (ja) * 2022-10-06 2024-04-18 株式会社ソシオネクスト 比較回路、アナログデジタル変換回路、及び半導体集積回路

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Also Published As

Publication number Publication date
JPH05509214A (ja) 1993-12-16
DE69131099T2 (de) 1999-11-04
DE69133008T2 (de) 2002-11-21
WO1992001336A1 (en) 1992-01-23
EP0798864B1 (en) 2002-05-08
EP0537304A1 (en) 1993-04-21
ES2129443T3 (es) 1999-06-16
EP0537304A4 (enExample) 1995-01-18
DE69131099D1 (de) 1999-05-12
GB9014679D0 (en) 1990-08-22
EP0537304B1 (en) 1999-04-07
DE69133008D1 (de) 2002-06-13
US5262779A (en) 1993-11-16
JP2002094377A (ja) 2002-03-29
EP0798864A1 (en) 1997-10-01

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LAPS Cancellation because of no payment of annual fees