JP3191302B2 - メモリ回路 - Google Patents

メモリ回路

Info

Publication number
JP3191302B2
JP3191302B2 JP41752290A JP41752290A JP3191302B2 JP 3191302 B2 JP3191302 B2 JP 3191302B2 JP 41752290 A JP41752290 A JP 41752290A JP 41752290 A JP41752290 A JP 41752290A JP 3191302 B2 JP3191302 B2 JP 3191302B2
Authority
JP
Japan
Prior art keywords
circuit
address
signal
data
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP41752290A
Other languages
English (en)
Japanese (ja)
Other versions
JPH04279945A (ja
Inventor
豊雄 木内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP41752290A priority Critical patent/JP3191302B2/ja
Priority to US07/816,396 priority patent/US5488712A/en
Priority to DE69129739T priority patent/DE69129739T2/de
Priority to EP91312091A priority patent/EP0493138B1/en
Publication of JPH04279945A publication Critical patent/JPH04279945A/ja
Application granted granted Critical
Publication of JP3191302B2 publication Critical patent/JP3191302B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Information Transfer Systems (AREA)
  • Advance Control (AREA)
  • Memory System (AREA)
  • Static Random-Access Memory (AREA)
JP41752290A 1990-12-28 1990-12-28 メモリ回路 Expired - Fee Related JP3191302B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP41752290A JP3191302B2 (ja) 1990-12-28 1990-12-28 メモリ回路
US07/816,396 US5488712A (en) 1990-12-28 1991-12-27 Memory circuit with pipeline processing
DE69129739T DE69129739T2 (de) 1990-12-28 1991-12-30 Speicherschaltung
EP91312091A EP0493138B1 (en) 1990-12-28 1991-12-30 Memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP41752290A JP3191302B2 (ja) 1990-12-28 1990-12-28 メモリ回路

Publications (2)

Publication Number Publication Date
JPH04279945A JPH04279945A (ja) 1992-10-06
JP3191302B2 true JP3191302B2 (ja) 2001-07-23

Family

ID=18525613

Family Applications (1)

Application Number Title Priority Date Filing Date
JP41752290A Expired - Fee Related JP3191302B2 (ja) 1990-12-28 1990-12-28 メモリ回路

Country Status (4)

Country Link
US (1) US5488712A (enExample)
EP (1) EP0493138B1 (enExample)
JP (1) JP3191302B2 (enExample)
DE (1) DE69129739T2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5410670A (en) * 1993-06-02 1995-04-25 Microunity Systems Engineering, Inc. Accessing system that reduces access times due to transmission delays and I/O access circuitry in a burst mode random access memory
US5696990A (en) * 1995-05-15 1997-12-09 Nvidia Corporation Method and apparatus for providing improved flow control for input/output operations in a computer system having a FIFO circuit and an overflow storage area
US5790813A (en) * 1996-01-05 1998-08-04 Unisys Corporation Pre-arbitration system allowing look-around and bypass for significant operations
US5838631A (en) 1996-04-19 1998-11-17 Integrated Device Technology, Inc. Fully synchronous pipelined ram
US6567903B1 (en) 1996-08-23 2003-05-20 Emc Corporation Data storage system having master/slave addressable memories
US6115320A (en) 1998-02-23 2000-09-05 Integrated Device Technology, Inc. Separate byte control on fully synchronous pipelined SRAM
US7069406B2 (en) * 1999-07-02 2006-06-27 Integrated Device Technology, Inc. Double data rate synchronous SRAM with 100% bus utilization
JP4749689B2 (ja) * 2004-08-31 2011-08-17 三洋電機株式会社 メモリ制御回路及びメモリ制御方法
US20150095551A1 (en) * 2013-09-30 2015-04-02 Micron Technology, Inc. Volatile memory architecutre in non-volatile memory devices and related controllers

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59136859A (ja) * 1983-01-27 1984-08-06 Nec Corp バツフア制御装置
JPS62126440A (ja) * 1985-11-27 1987-06-08 Nec Corp 情報処理装置
JP3255908B2 (ja) * 1988-06-30 2002-02-12 エルジー・セミコン・カンパニー・リミテッド メモリー制御ユニット
US4882709A (en) * 1988-08-25 1989-11-21 Integrated Device Technology, Inc. Conditional write RAM
JP2976429B2 (ja) * 1988-10-20 1999-11-10 日本電気株式会社 アドレス制御回路
US5093809A (en) * 1989-04-21 1992-03-03 Siemens Aktiengesellschaft Static memory having pipeline registers

Also Published As

Publication number Publication date
JPH04279945A (ja) 1992-10-06
EP0493138A3 (enExample) 1994-02-09
EP0493138B1 (en) 1998-07-08
US5488712A (en) 1996-01-30
DE69129739T2 (de) 1999-03-11
EP0493138A2 (en) 1992-07-01
DE69129739D1 (de) 1998-08-13

Similar Documents

Publication Publication Date Title
US4712190A (en) Self-timed random access memory chip
JP2003510732A (ja) ２倍データ速度同期式動的ランダムアクセスメモリのための構成可能同期装置
US7349285B2 (en) Dual port memory unit using a single port memory core
JP3191302B2 (ja) メモリ回路
US6684301B1 (en) Out of order execution memory access request FIFO
US4853848A (en) Block access system using cache memory
US6546451B1 (en) Method and apparatus for decoupling processor speed from memory subsystem speed in a node controller
EP0840203B1 (en) Semiconductor FIFO memory
US5267199A (en) Apparatus for simultaneous write access to a single bit memory
US5732011A (en) Digital system having high speed buffering
JP2638484B2 (ja) データ処理装置
JP2544886B2 (ja) デ―タ転送システムおよびデ―タ転送方法
US6421280B1 (en) Method and circuit for loading data and reading data
JPH05151142A (ja) インタフエース回路
JP2634609B2 (ja) データ転送装置
JP2637319B2 (ja) 直接メモリアクセス回路
JP3255429B2 (ja) メモリ・インタフェース回路
CN115878532A (zh) 数据传输系统及数据传输方法
JP2001526810A (ja) プロセッサをａｓｉｃに接続する方法及び構成体
JPH09139083A (ja) 半導体メモリ装置
JP2001160001A (ja) 半導体集積回路及びチップ間記憶部同期化方法
JPH05334184A (ja) ライトバッファ回路
JPH0589026A (ja) プロセツサ、メモリ、およびデータ処理装置
JPH05189305A (ja) メモリ制御方法
JPH06324862A (ja) 演算用記憶装置

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees