JP3180669B2 - 不揮発性半導体メモリおよびその書き込み方法 - Google Patents

不揮発性半導体メモリおよびその書き込み方法

Info

Publication number
JP3180669B2
JP3180669B2 JP14049796A JP14049796A JP3180669B2 JP 3180669 B2 JP3180669 B2 JP 3180669B2 JP 14049796 A JP14049796 A JP 14049796A JP 14049796 A JP14049796 A JP 14049796A JP 3180669 B2 JP3180669 B2 JP 3180669B2
Authority
JP
Japan
Prior art keywords
memory cell
voltage
writing
write
upper limit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP14049796A
Other languages
English (en)
Japanese (ja)
Other versions
JPH09320285A (ja
Inventor
俊夫 竹島
寛 菅原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP14049796A priority Critical patent/JP3180669B2/ja
Priority to US08/862,965 priority patent/US5757699A/en
Priority to KR1019970022916A priority patent/KR100247576B1/ko
Publication of JPH09320285A publication Critical patent/JPH09320285A/ja
Application granted granted Critical
Publication of JP3180669B2 publication Critical patent/JP3180669B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
JP14049796A 1996-06-03 1996-06-03 不揮発性半導体メモリおよびその書き込み方法 Expired - Fee Related JP3180669B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP14049796A JP3180669B2 (ja) 1996-06-03 1996-06-03 不揮発性半導体メモリおよびその書き込み方法
US08/862,965 US5757699A (en) 1996-06-03 1997-06-03 Programming which can make threshold voltages of programmed memory cells have a narrow distribution in a nonvolatile semiconductor memory
KR1019970022916A KR100247576B1 (ko) 1996-06-03 1997-06-03 비휘발성 반도체 메모리에서 프로그램된 메모리 셀의 임계 전압 이 협소 분포를 갖도록 하는 프로그래밍 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14049796A JP3180669B2 (ja) 1996-06-03 1996-06-03 不揮発性半導体メモリおよびその書き込み方法

Publications (2)

Publication Number Publication Date
JPH09320285A JPH09320285A (ja) 1997-12-12
JP3180669B2 true JP3180669B2 (ja) 2001-06-25

Family

ID=15270012

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14049796A Expired - Fee Related JP3180669B2 (ja) 1996-06-03 1996-06-03 不揮発性半導体メモリおよびその書き込み方法

Country Status (3)

Country Link
US (1) US5757699A (ko)
JP (1) JP3180669B2 (ko)
KR (1) KR100247576B1 (ko)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
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KR100477494B1 (ko) * 1995-01-31 2005-03-23 가부시끼가이샤 히다치 세이사꾸쇼 반도체 메모리 장치
JPH0982097A (ja) * 1995-07-10 1997-03-28 Hitachi Ltd 半導体不揮発性記憶装置およびそれを用いたコンピュータシステム
US5774670A (en) * 1995-10-06 1998-06-30 Netscape Communications Corporation Persistent client state in a hypertext transfer protocol based client-server system
US6320785B1 (en) 1996-07-10 2001-11-20 Hitachi, Ltd. Nonvolatile semiconductor memory device and data writing method therefor
JP3062730B2 (ja) 1996-07-10 2000-07-12 株式会社日立製作所 不揮発性半導体記憶装置および書込み方法
US6134148A (en) * 1997-09-30 2000-10-17 Hitachi, Ltd. Semiconductor integrated circuit and data processing system
JP3409986B2 (ja) * 1997-01-31 2003-05-26 株式会社東芝 多値メモリ
JP3481817B2 (ja) * 1997-04-07 2003-12-22 株式会社東芝 半導体記憶装置
JPH1196774A (ja) * 1997-09-25 1999-04-09 Sharp Corp 不揮発性半導体メモリセルのデータ書き込み方法
EP0913832B1 (en) * 1997-11-03 2003-07-23 STMicroelectronics S.r.l. Method for multilevel programming of a nonvolatile memory, and a multilevel nonvolatile memory
DE59810754D1 (de) * 1998-02-12 2004-03-18 Infineon Technologies Ag Elektrisch programmierbarer Nur-Lese-Speicher sowie Verfahren zum Programmieren und Lesen dieses Speichers
US6453337B2 (en) * 1999-10-25 2002-09-17 Zaplet, Inc. Methods and systems to manage and track the states of electronic media
US6205055B1 (en) * 2000-02-25 2001-03-20 Advanced Micro Devices, Inc. Dynamic memory cell programming voltage
JP2001266598A (ja) * 2000-03-22 2001-09-28 Denso Corp 不揮発性半導体メモリの特性検査方法
US6233175B1 (en) * 2000-10-21 2001-05-15 Advanced Micro Devices, Inc. Self-limiting multi-level programming states
US6556481B1 (en) 2001-02-21 2003-04-29 Aplus Flash Technology, Inc. 3-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cell
US6620682B1 (en) 2001-02-27 2003-09-16 Aplus Flash Technology, Inc. Set of three level concurrent word line bias conditions for a nor type flash memory array
US6621739B2 (en) * 2002-01-18 2003-09-16 Sandisk Corporation Reducing the effects of noise in non-volatile memories through multiple reads
US6862223B1 (en) * 2002-07-05 2005-03-01 Aplus Flash Technology, Inc. Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
JP2005235287A (ja) * 2004-02-19 2005-09-02 Nec Electronics Corp 不揮発性半導体記憶装置のプログラミング方法、プログラミング装置、及び、不揮発性半導体記憶装置
ITMI20041904A1 (it) * 2004-10-07 2005-01-07 Atmel Corp "metodo e sistema per un approccio di programmazione per un dispositivo elettronico non volatile"
WO2006041730A2 (en) * 2004-10-07 2006-04-20 Atmel Corporation Method and system for a programming approach for a nonvolatile electronic device
JP4786171B2 (ja) 2004-12-10 2011-10-05 株式会社東芝 半導体記憶装置
US7656710B1 (en) 2005-07-14 2010-02-02 Sau Ching Wong Adaptive operations for nonvolatile memories
US7372732B2 (en) * 2005-11-23 2008-05-13 Macronix International Co., Ltd. Pulse width converged method to control voltage threshold (Vt) distribution of a memory cell
TWI312969B (en) * 2005-12-08 2009-08-01 Mstar Semiconductor Inc Operating nonvolatile memory method
US7729165B2 (en) * 2007-03-29 2010-06-01 Flashsilicon, Incorporation Self-adaptive and self-calibrated multiple-level non-volatile memories
KR100888847B1 (ko) 2007-06-28 2009-03-17 삼성전자주식회사 불휘발성 반도체 메모리 장치 및 그것의 프로그램 방법
US7813188B2 (en) * 2007-09-10 2010-10-12 Hynix Semiconductor Inc. Non-volatile memory device and a method of programming a multi level cell in the same
JP5172555B2 (ja) 2008-09-08 2013-03-27 株式会社東芝 半導体記憶装置
JP5075992B2 (ja) * 2011-02-02 2012-11-21 株式会社東芝 半導体記憶装置
JP2014053060A (ja) 2012-09-07 2014-03-20 Toshiba Corp 半導体記憶装置及びその制御方法
JP2014063551A (ja) 2012-09-21 2014-04-10 Toshiba Corp 半導体記憶装置
CN111863083A (zh) * 2019-04-29 2020-10-30 北京兆易创新科技股份有限公司 一种NOR flash存储器编程的方法、装置以及NOR flash存储器

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3152720B2 (ja) * 1991-03-12 2001-04-03 株式会社東芝 不揮発性半導体記憶装置
JP3213434B2 (ja) * 1993-03-25 2001-10-02 新日本製鐵株式会社 不揮発性半導体記憶装置
JP2707970B2 (ja) * 1994-04-11 1998-02-04 日本電気株式会社 不揮発性半導体記憶装置の消去方法
JPH07312093A (ja) * 1994-05-13 1995-11-28 Hitachi Ltd 半導体記憶装置
US5608679A (en) * 1994-06-02 1997-03-04 Intel Corporation Fast internal reference cell trimming for flash EEPROM memory

Also Published As

Publication number Publication date
KR980005031A (ko) 1998-03-30
JPH09320285A (ja) 1997-12-12
US5757699A (en) 1998-05-26
KR100247576B1 (ko) 2000-03-15

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